Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	720796785	0	0	634
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	720796785	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	720796785	720599345	0	0
tb.dut.CheckAccuCntDw	0	0	634	634	0	0
tb.dut.CheckEscCntDw	0	0	634	634	0	0
tb.dut.CheckNAlerts	0	0	634	634	0	0
tb.dut.CheckNClasses	0	0	634	634	0	0
tb.dut.CheckNEscSev	0	0	634	634	0	0
tb.dut.CrashdumpKnownO_A	0	0	720796785	720599345	0	0
tb.dut.EdnKnownO_A	0	0	720796785	720599345	0	0
tb.dut.EscPKnownO_A	0	0	720796785	720599345	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	720796785	100	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	720796785	100	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	720796785	100	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	720796785	100	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	720796785	100	0	0
tb.dut.IrqAKnownO_A	0	0	720796785	720599345	0	0
tb.dut.IrqBKnownO_A	0	0	720796785	720599345	0	0
tb.dut.IrqCKnownO_A	0	0	720796785	720599345	0	0
tb.dut.IrqDKnownO_A	0	0	720796785	720599345	0	0
tb.dut.TlAReadyKnownO_A	0	0	720796785	720599345	0	0
tb.dut.TlDValidKnownO_A	0	0	720796785	720599345	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	750048771	4060539	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	750048771	25856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	750048771	22648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	750048771	23353	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	750048771	23014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	750048771	21965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	750048771	25572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	750048771	24804	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	750048771	23606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	750048771	23512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	750048771	21859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	750048771	21846	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	750048771	23030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	750048771	22289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	750048771	21993	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	750048771	23899	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	750048771	22025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	750048771	22807	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	750048771	22145	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	750048771	24165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	750048771	22917	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	750048771	22988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	750048771	24044	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	750048771	24217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	750048771	22136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	750048771	23908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	750048771	23120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	750048771	22385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	750048771	25394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	750048771	22563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	750048771	21960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	750048771	23698	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	750048771	21999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	750048771	22435	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	750048771	22547	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	750048771	22468	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	750048771	22882	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	750048771	24394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	750048771	25389	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	750048771	23263	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	750048771	22581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	750048771	23014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	750048771	24348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	750048771	24103	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	750048771	23922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	750048771	26507	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	750048771	22093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	750048771	23060	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	750048771	25582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	750048771	22164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	750048771	23426	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	750048771	24614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	750048771	23508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	750048771	24693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	750048771	25141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	750048771	22801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	750048771	22894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	750048771	23159	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	750048771	22921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	750048771	23115	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	750048771	21681	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	750048771	24026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	750048771	23968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	750048771	22964	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	750048771	24475	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	750048771	23782	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	750048771	21943	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	750048771	23255	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	750048771	26005	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	750048771	24907	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	750048771	42160	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	750048771	24711	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	750048771	25353	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	750048771	23374	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	750048771	23617	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	750048771	21433	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	750048771	21852	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	750048771	22876	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	750048771	22980	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	720796785	4572	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	720796785	236921	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	720796785	379641037	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	720796785	315	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	720796785	867	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	720796785	55	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	720796785	419	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	720608589	301789681	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	720796785	962	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	720796785	934	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	720796785	910	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	720796785	883	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	720796785	1684	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	720796785	162279	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	720796785	1569	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	720796785	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	720796785	1774	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	720796785	1474	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	720607632	720537232	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	634	634	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	720796785	720599345	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	720796785	4263	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	720796785	177265	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	720796785	431573708	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	720796785	352	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	720796785	512	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	720796785	19	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	720796785	230	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	720608589	314370368	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	720796785	604	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	720796785	591	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	720796785	575	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	720796785	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	720796785	834	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	720796785	100145	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	720796785	738	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	720796785	77	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	720796785	1839	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	720796785	1539	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	720607632	720537232	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	634	634	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	720796785	720599345	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	720796785	1788	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	720796785	144201	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	720796785	450903122	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	720796785	401	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	720796785	473	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	720796785	19	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	720796785	208	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	720608589	365615591	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	720796785	556	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	720796785	546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	720796785	539	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	720796785	524	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	720796785	1609	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	720796785	168553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	720796785	1517	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	720796785	71	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	720796785	1813	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	720796785	1513	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	720607632	720537232	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	634	634	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	720796785	720599345	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	720796785	100	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	720796785	3306	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	720796785	215539	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	720796785	417919460	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	720796785	382	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	720796785	543	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	720796785	30	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	720796785	259	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	720608589	336705464	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	720796785	638	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	720796785	625	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	720796785	608	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	720796785	596	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	720796785	914	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	720796785	103609	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	720796785	807	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	720796785	75	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	720796785	1823	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	720796785	1523	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	720607632	720537232	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	634	634	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	720796785	720599345	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	750048771	152187739	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	750048771	749334258	0	0
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