Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T8	1		T77	1		T23	1
class_index[0x1]	77	1			T8	3		T20	2		T21	1
class_index[0x2]	71	1			T20	1		T27	1		T77	1
class_index[0x3]	75	1			T20	2		T77	1		T23	8

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	130	1			T8	1		T20	1		T77	2
intr_timeout_cnt[1]	42	1			T8	1		T77	1		T23	2
intr_timeout_cnt[2]	28	1			T8	1		T20	2		T21	1
intr_timeout_cnt[3]	15	1			T20	1		T118	1		T33	2
intr_timeout_cnt[4]	18	1			T8	1		T32	1		T33	1
intr_timeout_cnt[5]	12	1			T45	1		T33	1		T276	1
intr_timeout_cnt[6]	17	1			T23	9		T94	1		T63	1
intr_timeout_cnt[7]	12	1			T20	1		T27	1		T23	1
intr_timeout_cnt[8]	5	1			T124	1		T277	1		T188	1
intr_timeout_cnt[9]	3	1			T93	1		T278	1		T65	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	33	1			T52	5		T25	2		T84	6
class_index[0x0]	intr_timeout_cnt[1]	12	1			T77	1		T23	1		T82	1
class_index[0x0]	intr_timeout_cnt[2]	1	1			T94	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	2	1			T33	1		T94	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	7	1			T8	1		T32	1		T279	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T276	1		T189	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T280	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T124	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	34	1			T8	1		T23	1		T72	7
class_index[0x1]	intr_timeout_cnt[1]	11	1			T8	1		T23	1		T52	1
class_index[0x1]	intr_timeout_cnt[2]	11	1			T8	1		T20	2		T21	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T124	1		T281	1		T282	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T283	2		T278	1		T262	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T45	1		T33	1		T19	1
class_index[0x1]	intr_timeout_cnt[6]	4	1			T23	4		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T284	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T188	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T93	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	32	1			T77	1		T85	1		T86	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T88	1		T285	1		T234	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T109	1		T286	1		T106	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T109	1		T285	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T262	1		T188	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T287	1		T235	2		-	-
class_index[0x2]	intr_timeout_cnt[6]	8	1			T23	5		T63	1		T199	1
class_index[0x2]	intr_timeout_cnt[7]	5	1			T20	1		T27	1		T89	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T288	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T65	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	31	1			T20	1		T77	1		T23	7
class_index[0x3]	intr_timeout_cnt[1]	10	1			T33	1		T58	1		T110	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T262	1		T188	2		T289	1
class_index[0x3]	intr_timeout_cnt[3]	8	1			T20	1		T118	1		T33	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T33	1		T274	2		T290	2
class_index[0x3]	intr_timeout_cnt[5]	1	1			T291	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	5	1			T94	1		T292	3		T275	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T23	1		T124	1		T280	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T277	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T278	1		-	-		-	-