Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368759	1			T1	589		T2	961		T3	23
all_values[1]	368759	1			T1	589		T2	961		T3	23
all_values[2]	368759	1			T1	589		T2	961		T3	23
all_values[3]	368759	1			T1	589		T2	961		T3	23

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

733075

1

T1

1150

T2

1902

T3

50

auto[1]

741961

1

T1

1206

T2

1942

T3

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

886470

1

T1

1187

T2

2759

T3

81

auto[1]

588566

1

T1

1169

T2

1085

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103308	1			T1	145		T2	276		T3	8
all_values[0]	auto[0]	auto[1]	80459	1			T1	144		T2	171		T3	7
all_values[0]	auto[1]	auto[0]	104474	1			T1	149		T2	328		T3	4
all_values[0]	auto[1]	auto[1]	80518	1			T1	151		T2	186		T3	4
all_values[1]	auto[0]	auto[0]	110269	1			T1	143		T2	296		T3	13
all_values[1]	auto[0]	auto[1]	72658	1			T1	140		T2	187		T16	2
all_values[1]	auto[1]	auto[0]	112658	1			T1	153		T2	307		T3	10
all_values[1]	auto[1]	auto[1]	73174	1			T1	153		T2	171		T16	6
all_values[2]	auto[0]	auto[0]	112737	1			T1	146		T2	297		T3	13
all_values[2]	auto[0]	auto[1]	70585	1			T1	137		T2	185		T16	7
all_values[2]	auto[1]	auto[0]	114370	1			T1	155		T2	295		T3	10
all_values[2]	auto[1]	auto[1]	71067	1			T1	151		T2	184		T4	10
all_values[3]	auto[0]	auto[0]	113301	1			T1	148		T2	489		T3	9
all_values[3]	auto[0]	auto[1]	69758	1			T1	147		T2	1		T16	4
all_values[3]	auto[1]	auto[0]	115353	1			T1	148		T2	471		T3	14
all_values[3]	auto[1]	auto[1]	70347	1			T1	146		T4	2		T16	4