Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	368759	1			T1	589		T2	961		T3	23
all_pins[1]	368759	1			T1	589		T2	961		T3	23
all_pins[2]	368759	1			T1	589		T2	961		T3	23
all_pins[3]	368759	1			T1	589		T2	961		T3	23

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1179930	1			T1	1755		T2	3303		T3	88
values[0x1]	295106	1			T1	601		T2	541		T3	4
transitions[0x0=>0x1]	196559	1			T1	379		T2	411		T3	4
transitions[0x1=>0x0]	196812	1			T1	379		T2	412		T3	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	288241	1			T1	438		T2	775		T3	19
all_pins[0]	values[0x1]	80518	1			T1	151		T2	186		T3	4
all_pins[0]	transitions[0x0=>0x1]	79820	1			T1	148		T2	185		T3	4
all_pins[0]	transitions[0x1=>0x0]	69902	1			T1	143		T4	2		T16	4
all_pins[1]	values[0x0]	295585	1			T1	436		T2	790		T3	23
all_pins[1]	values[0x1]	73174	1			T1	153		T2	171		T16	6
all_pins[1]	transitions[0x0=>0x1]	39627	1			T1	75		T2	104		T16	4
all_pins[1]	transitions[0x1=>0x0]	46971	1			T1	73		T2	119		T3	4
all_pins[2]	values[0x0]	297692	1			T1	438		T2	777		T3	23
all_pins[2]	values[0x1]	71067	1			T1	151		T2	184		T4	10
all_pins[2]	transitions[0x0=>0x1]	38910	1			T1	79		T2	122		T4	10
all_pins[2]	transitions[0x1=>0x0]	41017	1			T1	81		T2	109		T16	6
all_pins[3]	values[0x0]	298412	1			T1	443		T2	961		T3	23
all_pins[3]	values[0x1]	70347	1			T1	146		T4	2		T16	4
all_pins[3]	transitions[0x0=>0x1]	38202	1			T1	77		T4	2		T16	4
all_pins[3]	transitions[0x1=>0x0]	38922	1			T1	82		T2	184		T4	10