Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 269 1 T165 4 T166 7 T167 4
all_values[1] 269 1 T165 4 T166 7 T167 4
all_values[2] 269 1 T165 4 T166 7 T167 4
all_values[3] 269 1 T165 4 T166 7 T167 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 552 1 T165 7 T166 10 T167 12
auto[1] 524 1 T165 9 T166 18 T167 4



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 422 1 T165 4 T166 6 T167 9
auto[1] 654 1 T165 12 T166 22 T167 7



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 646 1 T165 9 T166 13 T167 11
auto[1] 430 1 T165 7 T166 15 T167 5



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 52 1 T166 2 T231 2 T345 1
all_values[0] auto[0] auto[0] auto[1] 28 1 T167 1 T346 2 T345 1
all_values[0] auto[0] auto[1] auto[0] 50 1 T165 1 T231 3 T346 1
all_values[0] auto[0] auto[1] auto[1] 30 1 T165 1 T166 3 T347 1
all_values[0] auto[1] auto[0] auto[1] 56 1 T165 1 T166 1 T167 3
all_values[0] auto[1] auto[1] auto[1] 53 1 T165 1 T166 1 T347 3
all_values[1] auto[0] auto[0] auto[0] 49 1 T165 1 T167 3 T231 4
all_values[1] auto[0] auto[0] auto[1] 32 1 T166 1 T347 2 T348 2
all_values[1] auto[0] auto[1] auto[0] 55 1 T165 1 T166 1 T167 1
all_values[1] auto[0] auto[1] auto[1] 32 1 T165 1 T166 1 T348 1
all_values[1] auto[1] auto[0] auto[1] 58 1 T166 2 T347 2 T231 1
all_values[1] auto[1] auto[1] auto[1] 43 1 T165 1 T166 2 T231 1
all_values[2] auto[0] auto[0] auto[0] 57 1 T165 1 T167 1 T231 2
all_values[2] auto[0] auto[0] auto[1] 29 1 T165 1 T166 1 T349 2
all_values[2] auto[0] auto[1] auto[0] 47 1 T347 1 T231 1 T350 2
all_values[2] auto[0] auto[1] auto[1] 23 1 T167 1 T347 1 T231 1
all_values[2] auto[1] auto[0] auto[1] 56 1 T165 1 T166 2 T347 1
all_values[2] auto[1] auto[1] auto[1] 57 1 T165 1 T166 4 T167 2
all_values[3] auto[0] auto[0] auto[0] 54 1 T166 1 T167 4 T347 2
all_values[3] auto[0] auto[0] auto[1] 24 1 T165 1 T231 1 T346 1
all_values[3] auto[0] auto[1] auto[0] 58 1 T166 2 T347 2 T345 1
all_values[3] auto[0] auto[1] auto[1] 26 1 T165 1 T166 1 T231 2
all_values[3] auto[1] auto[0] auto[1] 57 1 T165 1 T231 1 T346 1
all_values[3] auto[1] auto[1] auto[1] 50 1 T165 1 T166 3 T231 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%