Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83749	1			T8	820		T6	1297		T13	587
accum_cnt_1000	215525	1			T1	71		T2	540		T8	2064
accum_cnt_100	26837	1			T1	139		T2	103		T8	206
accum_cnt_50	62352	1			T1	162		T2	55		T3	11
accum_cnt_10	224262	1			T1	502		T2	1434		T3	5
accum_cnt_0	433616	1			T1	494		T2	728		T3	52

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	271845	1			T1	342		T2	715		T3	17
class_index[0x1]	271845	1			T1	342		T2	715		T3	17
class_index[0x2]	271845	1			T1	342		T2	715		T3	17
class_index[0x3]	271845	1			T1	342		T2	715		T3	17

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24083	1			T8	591		T6	363		T13	496
class_index[0x0]	accum_cnt_1000	60505	1			T1	37		T8	741		T6	565
class_index[0x0]	accum_cnt_100	8326	1			T1	41		T8	68		T6	33
class_index[0x0]	accum_cnt_50	15373	1			T1	36		T3	11		T4	3
class_index[0x0]	accum_cnt_10	57856	1			T1	34		T2	715		T3	5
class_index[0x0]	accum_cnt_0	93082	1			T1	194		T3	1		T4	13
class_index[0x1]	accum_cnt_2000	18262	1			T6	487		T68	47		T294	208
class_index[0x1]	accum_cnt_1000	49270	1			T1	17		T2	540		T8	669
class_index[0x1]	accum_cnt_100	5417	1			T1	21		T2	103		T8	54
class_index[0x1]	accum_cnt_50	18954	1			T1	19		T2	55		T8	1515
class_index[0x1]	accum_cnt_10	58070	1			T1	11		T2	13		T16	14
class_index[0x1]	accum_cnt_0	112626	1			T1	274		T2	4		T3	17
class_index[0x2]	accum_cnt_2000	18784	1			T8	229		T7	654		T74	610
class_index[0x2]	accum_cnt_1000	49921	1			T1	17		T8	532		T20	46
class_index[0x2]	accum_cnt_100	6704	1			T1	39		T8	54		T20	55
class_index[0x2]	accum_cnt_50	13824	1			T1	65		T5	19		T8	98
class_index[0x2]	accum_cnt_10	53037	1			T1	203		T5	24		T8	67
class_index[0x2]	accum_cnt_0	122441	1			T1	18		T2	715		T3	17
class_index[0x3]	accum_cnt_2000	22620	1			T6	447		T13	91		T7	485
class_index[0x3]	accum_cnt_1000	55829	1			T8	122		T6	398		T13	93
class_index[0x3]	accum_cnt_100	6390	1			T1	38		T8	30		T6	26
class_index[0x3]	accum_cnt_50	14201	1			T1	42		T8	55		T6	30
class_index[0x3]	accum_cnt_10	55299	1			T1	254		T2	706		T4	1
class_index[0x3]	accum_cnt_0	105467	1			T1	8		T2	9		T3	17