Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5970	1			T13	560		T31	201		T51	1
alert[0x1]	3480	1			T5	1		T8	418		T73	1
alert[0x2]	2893	1			T4	1		T5	1		T13	66
alert[0x3]	2429	1			T9	1		T23	1		T24	41
alert[0x4]	5327	1			T27	9		T23	3		T24	2
alert[0x5]	2809	1			T23	3		T24	9		T101	576
alert[0x6]	5401	1			T8	630		T20	181		T9	1
alert[0x7]	3244	1			T8	1404		T9	1		T72	8
alert[0x8]	4724	1			T9	1		T68	1		T104	1
alert[0x9]	2684	1			T9	1		T27	2		T31	119
alert[0xa]	2864	1			T117	1		T24	20		T197	1
alert[0xb]	6408	1			T24	1		T197	3		T296	254
alert[0xc]	1836	1			T5	1		T8	61		T232	1
alert[0xd]	4546	1			T23	7		T82	12		T24	215
alert[0xe]	3774	1			T5	1		T46	26		T97	2
alert[0xf]	11937	1			T8	657		T13	2719		T20	17
alert[0x10]	2462	1			T4	1		T8	105		T13	10
alert[0x11]	4481	1			T4	1		T20	7		T77	13
alert[0x12]	1937	1			T5	1		T72	6		T24	35
alert[0x13]	7672	1			T9	1		T23	5		T82	1
alert[0x14]	1962	1			T13	851		T232	1		T117	1
alert[0x15]	2489	1			T8	43		T13	48		T117	1
alert[0x16]	7164	1			T8	172		T13	42		T27	4
alert[0x17]	3755	1			T8	16		T20	21		T117	2
alert[0x18]	1877	1			T8	46		T20	5		T97	2
alert[0x19]	9198	1			T5	1		T46	2		T97	3
alert[0x1a]	10002	1			T4	1		T5	1		T8	1
alert[0x1b]	2524	1			T4	2		T5	1		T8	243
alert[0x1c]	5109	1			T5	1		T20	2		T9	1
alert[0x1d]	5240	1			T8	11		T13	15		T77	197
alert[0x1e]	3996	1			T4	1		T20	4		T24	174
alert[0x1f]	5939	1			T8	39		T13	179		T20	113
alert[0x20]	5982	1			T9	1		T23	1		T24	133
alert[0x21]	13099	1			T77	95		T23	1		T117	1
alert[0x22]	11079	1			T8	1147		T13	222		T77	195
alert[0x23]	9640	1			T4	2		T8	102		T13	18
alert[0x24]	3888	1			T4	1		T5	1		T232	1
alert[0x25]	9127	1			T13	3290		T77	26		T23	5
alert[0x26]	2917	1			T4	2		T5	1		T24	38
alert[0x27]	3411	1			T8	1		T24	11		T31	14
alert[0x28]	2570	1			T9	1		T31	4		T259	27
alert[0x29]	5893	1			T8	29		T13	11		T20	342
alert[0x2a]	3160	1			T9	1		T82	26		T25	77
alert[0x2b]	5672	1			T4	1		T5	1		T117	1
alert[0x2c]	6710	1			T5	1		T8	4		T23	1
alert[0x2d]	11534	1			T2	1		T5	1		T8	70
alert[0x2e]	10529	1			T2	1		T8	33		T13	212
alert[0x2f]	2786	1			T13	57		T9	1		T46	1
alert[0x30]	5617	1			T5	2		T13	6		T27	2
alert[0x31]	7384	1			T4	1		T45	1		T27	1
alert[0x32]	3659	1			T8	9		T13	120		T23	26
alert[0x33]	3824	1			T13	415		T24	26		T296	30
alert[0x34]	6181	1			T4	1		T5	1		T20	96
alert[0x35]	6267	1			T20	60		T27	1		T117	1
alert[0x36]	6224	1			T4	1		T5	1		T27	4
alert[0x37]	7821	1			T20	3344		T27	3		T23	21
alert[0x38]	2787	1			T5	1		T232	1		T77	3
alert[0x39]	5843	1			T8	92		T13	4		T20	3
alert[0x3a]	4541	1			T8	53		T9	1		T23	8
alert[0x3b]	2909	1			T8	26		T73	1		T25	35
alert[0x3c]	5228	1			T8	520		T13	6		T77	149
alert[0x3d]	3154	1			T4	1		T8	1096		T13	32
alert[0x3e]	8356	1			T8	3069		T13	1593		T9	1
alert[0x3f]	6672	1			T20	1		T23	4		T24	38
alert[0x40]	3688	1			T8	21		T9	1		T24	83

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	68610	1			T4	14		T13	32		T20	5
class_i[0x1]	100396	1			T5	1		T20	4422		T9	12
class_i[0x2]	98367	1			T2	2		T4	1		T5	18
class_i[0x3]	76912	1			T4	2		T13	10676		T20	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

343599

1

T8

10118

T13

10708

T20

4431

alert_ping_fail

686

1

T2

2

T4

17

T5

19

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5961	1			T13	560		T31	201		T51	1
alert_integrity_fail	alert[0x1]	3472	1			T8	418		T31	125		T32	85
alert_integrity_fail	alert[0x2]	2887	1			T13	66		T23	7		T24	76
alert_integrity_fail	alert[0x3]	2422	1			T23	1		T24	41		T25	24
alert_integrity_fail	alert[0x4]	5315	1			T27	9		T23	3		T24	2
alert_integrity_fail	alert[0x5]	2799	1			T23	3		T24	9		T101	576
alert_integrity_fail	alert[0x6]	5385	1			T8	630		T20	181		T77	2
alert_integrity_fail	alert[0x7]	3236	1			T8	1404		T72	8		T24	48
alert_integrity_fail	alert[0x8]	4714	1			T68	1		T32	212		T33	6
alert_integrity_fail	alert[0x9]	2674	1			T27	2		T31	119		T296	32
alert_integrity_fail	alert[0xa]	2856	1			T24	20		T296	177		T225	64
alert_integrity_fail	alert[0xb]	6392	1			T24	1		T296	254		T225	28
alert_integrity_fail	alert[0xc]	1829	1			T8	61		T24	295		T31	15
alert_integrity_fail	alert[0xd]	4535	1			T23	7		T82	12		T24	215
alert_integrity_fail	alert[0xe]	3763	1			T46	26		T97	2		T31	18
alert_integrity_fail	alert[0xf]	11931	1			T8	657		T13	2719		T20	17
alert_integrity_fail	alert[0x10]	2452	1			T8	105		T13	10		T46	3
alert_integrity_fail	alert[0x11]	4464	1			T20	7		T77	13		T23	3
alert_integrity_fail	alert[0x12]	1924	1			T72	6		T24	35		T297	25
alert_integrity_fail	alert[0x13]	7659	1			T23	5		T82	1		T24	1
alert_integrity_fail	alert[0x14]	1945	1			T13	851		T24	11		T32	169
alert_integrity_fail	alert[0x15]	2474	1			T8	43		T13	48		T296	41
alert_integrity_fail	alert[0x16]	7154	1			T8	172		T13	42		T27	4
alert_integrity_fail	alert[0x17]	3740	1			T8	16		T20	21		T31	687
alert_integrity_fail	alert[0x18]	1870	1			T8	46		T20	5		T97	2
alert_integrity_fail	alert[0x19]	9189	1			T46	2		T97	3		T82	1
alert_integrity_fail	alert[0x1a]	9993	1			T8	1		T13	42		T77	14
alert_integrity_fail	alert[0x1b]	2513	1			T8	243		T20	200		T118	1
alert_integrity_fail	alert[0x1c]	5094	1			T20	2		T24	13		T31	12
alert_integrity_fail	alert[0x1d]	5228	1			T8	11		T13	15		T77	197
alert_integrity_fail	alert[0x1e]	3987	1			T20	4		T24	174		T25	70
alert_integrity_fail	alert[0x1f]	5924	1			T8	39		T13	179		T20	113
alert_integrity_fail	alert[0x20]	5975	1			T23	1		T24	133		T31	38
alert_integrity_fail	alert[0x21]	13088	1			T77	95		T23	1		T31	59
alert_integrity_fail	alert[0x22]	11066	1			T8	1147		T13	222		T77	195
alert_integrity_fail	alert[0x23]	9625	1			T8	102		T13	18		T20	21
alert_integrity_fail	alert[0x24]	3879	1			T23	6		T25	1877		T296	3
alert_integrity_fail	alert[0x25]	9119	1			T13	3290		T77	26		T23	5
alert_integrity_fail	alert[0x26]	2909	1			T24	38		T31	93		T51	41
alert_integrity_fail	alert[0x27]	3407	1			T8	1		T24	11		T31	14
alert_integrity_fail	alert[0x28]	2555	1			T31	4		T259	27		T227	87
alert_integrity_fail	alert[0x29]	5883	1			T8	29		T13	11		T20	342
alert_integrity_fail	alert[0x2a]	3150	1			T82	26		T25	77		T296	135
alert_integrity_fail	alert[0x2b]	5658	1			T72	1		T296	15		T297	333
alert_integrity_fail	alert[0x2c]	6691	1			T8	4		T23	1		T24	10
alert_integrity_fail	alert[0x2d]	11520	1			T8	70		T13	190		T31	254
alert_integrity_fail	alert[0x2e]	10518	1			T8	33		T13	212		T20	9
alert_integrity_fail	alert[0x2f]	2771	1			T13	57		T46	1		T27	1
alert_integrity_fail	alert[0x30]	5602	1			T13	6		T27	2		T23	7
alert_integrity_fail	alert[0x31]	7379	1			T45	1		T27	1		T23	31
alert_integrity_fail	alert[0x32]	3646	1			T8	9		T13	120		T23	26
alert_integrity_fail	alert[0x33]	3819	1			T13	415		T24	26		T296	30
alert_integrity_fail	alert[0x34]	6170	1			T20	96		T23	2		T24	1118
alert_integrity_fail	alert[0x35]	6257	1			T20	60		T27	1		T82	1
alert_integrity_fail	alert[0x36]	6215	1			T27	4		T31	53		T25	448
alert_integrity_fail	alert[0x37]	7811	1			T20	3344		T27	3		T23	21
alert_integrity_fail	alert[0x38]	2778	1			T77	3		T24	61		T31	27
alert_integrity_fail	alert[0x39]	5837	1			T8	92		T13	4		T20	3
alert_integrity_fail	alert[0x3a]	4532	1			T8	53		T23	8		T24	39
alert_integrity_fail	alert[0x3b]	2897	1			T8	26		T25	35		T296	34
alert_integrity_fail	alert[0x3c]	5218	1			T8	520		T13	6		T77	149
alert_integrity_fail	alert[0x3d]	3145	1			T8	1096		T13	32		T20	5
alert_integrity_fail	alert[0x3e]	8346	1			T8	3069		T13	1593		T77	3
alert_integrity_fail	alert[0x3f]	6668	1			T20	1		T23	4		T24	38
alert_integrity_fail	alert[0x40]	3684	1			T8	21		T24	83		T25	638
alert_ping_fail	alert[0x0]	9	1			T298	1		T299	1		T300	1
alert_ping_fail	alert[0x1]	8	1			T5	1		T73	1		T298	1
alert_ping_fail	alert[0x2]	6	1			T4	1		T5	1		T301	1
alert_ping_fail	alert[0x3]	7	1			T9	1		T302	1		T303	1
alert_ping_fail	alert[0x4]	12	1			T304	1		T272	1		T301	2
alert_ping_fail	alert[0x5]	10	1			T305	1		T301	1		T91	2
alert_ping_fail	alert[0x6]	16	1			T9	1		T40	1		T298	1
alert_ping_fail	alert[0x7]	8	1			T9	1		T197	2		T306	1
alert_ping_fail	alert[0x8]	10	1			T9	1		T104	1		T298	1
alert_ping_fail	alert[0x9]	10	1			T9	1		T197	1		T263	1
alert_ping_fail	alert[0xa]	8	1			T117	1		T197	1		T221	1
alert_ping_fail	alert[0xb]	16	1			T197	3		T272	1		T301	1
alert_ping_fail	alert[0xc]	7	1			T5	1		T232	1		T301	1
alert_ping_fail	alert[0xd]	11	1			T306	1		T298	1		T301	1
alert_ping_fail	alert[0xe]	11	1			T5	1		T272	1		T263	1
alert_ping_fail	alert[0xf]	6	1			T9	1		T300	1		T307	1
alert_ping_fail	alert[0x10]	10	1			T4	1		T306	1		T298	1
alert_ping_fail	alert[0x11]	17	1			T4	1		T73	1		T197	1
alert_ping_fail	alert[0x12]	13	1			T5	1		T306	3		T298	1
alert_ping_fail	alert[0x13]	13	1			T9	1		T306	1		T298	1
alert_ping_fail	alert[0x14]	17	1			T232	1		T117	1		T197	1
alert_ping_fail	alert[0x15]	15	1			T117	1		T263	1		T308	2
alert_ping_fail	alert[0x16]	10	1			T218	1		T306	1		T298	1
alert_ping_fail	alert[0x17]	15	1			T117	2		T197	1		T298	1
alert_ping_fail	alert[0x18]	7	1			T306	1		T304	1		T301	1
alert_ping_fail	alert[0x19]	9	1			T5	1		T309	1		T310	2
alert_ping_fail	alert[0x1a]	9	1			T4	1		T5	1		T301	2
alert_ping_fail	alert[0x1b]	11	1			T4	2		T5	1		T117	1
alert_ping_fail	alert[0x1c]	15	1			T5	1		T9	1		T306	1
alert_ping_fail	alert[0x1d]	12	1			T73	3		T299	1		T302	2
alert_ping_fail	alert[0x1e]	9	1			T4	1		T311	1		T312	1
alert_ping_fail	alert[0x1f]	15	1			T232	1		T218	1		T293	3
alert_ping_fail	alert[0x20]	7	1			T9	1		T272	1		T308	1
alert_ping_fail	alert[0x21]	11	1			T117	1		T301	1		T299	1
alert_ping_fail	alert[0x22]	13	1			T197	1		T304	1		T313	1
alert_ping_fail	alert[0x23]	15	1			T4	2		T298	1		T299	2
alert_ping_fail	alert[0x24]	9	1			T4	1		T5	1		T232	1
alert_ping_fail	alert[0x25]	8	1			T117	1		T298	1		T309	1
alert_ping_fail	alert[0x26]	8	1			T4	2		T5	1		T306	1
alert_ping_fail	alert[0x27]	4	1			T314	1		T315	1		T316	1
alert_ping_fail	alert[0x28]	15	1			T9	1		T306	1		T304	1
alert_ping_fail	alert[0x29]	10	1			T304	1		T298	1		T301	1
alert_ping_fail	alert[0x2a]	10	1			T9	1		T104	1		T306	1
alert_ping_fail	alert[0x2b]	14	1			T4	1		T5	1		T117	1
alert_ping_fail	alert[0x2c]	19	1			T5	1		T104	1		T306	1
alert_ping_fail	alert[0x2d]	14	1			T2	1		T5	1		T263	1
alert_ping_fail	alert[0x2e]	11	1			T2	1		T232	1		T306	1
alert_ping_fail	alert[0x2f]	15	1			T9	1		T232	1		T197	1
alert_ping_fail	alert[0x30]	15	1			T5	2		T232	1		T218	2
alert_ping_fail	alert[0x31]	5	1			T4	1		T317	1		T318	1
alert_ping_fail	alert[0x32]	13	1			T272	1		T263	1		T301	2
alert_ping_fail	alert[0x33]	5	1			T303	2		T311	1		T312	1
alert_ping_fail	alert[0x34]	11	1			T4	1		T5	1		T306	1
alert_ping_fail	alert[0x35]	10	1			T117	1		T306	1		T300	1
alert_ping_fail	alert[0x36]	9	1			T4	1		T5	1		T306	1
alert_ping_fail	alert[0x37]	10	1			T272	1		T319	1		T309	1
alert_ping_fail	alert[0x38]	9	1			T5	1		T232	1		T306	1
alert_ping_fail	alert[0x39]	6	1			T9	1		T298	1		T272	1
alert_ping_fail	alert[0x3a]	9	1			T9	1		T197	1		T310	1
alert_ping_fail	alert[0x3b]	12	1			T73	1		T298	1		T301	1
alert_ping_fail	alert[0x3c]	10	1			T117	1		T320	1		T300	1
alert_ping_fail	alert[0x3d]	9	1			T4	1		T299	1		T321	1
alert_ping_fail	alert[0x3e]	10	1			T9	1		T272	1		T301	1
alert_ping_fail	alert[0x3f]	4	1			T301	1		T309	1		T303	1
alert_ping_fail	alert[0x40]	4	1			T9	1		T298	2		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	68461	1			T13	32		T20	5		T45	1
alert_integrity_fail	class_i[0x1]	100211	1			T20	4422		T27	16		T23	9
alert_integrity_fail	class_i[0x2]	98133	1			T8	10118		T20	3		T77	14
alert_integrity_fail	class_i[0x3]	76794	1			T13	10676		T20	1		T46	53
alert_ping_fail	class_i[0x0]	149	1			T4	14		T232	8		T73	1
alert_ping_fail	class_i[0x1]	185	1			T5	1		T9	12		T306	21
alert_ping_fail	class_i[0x2]	234	1			T2	2		T4	1		T5	18
alert_ping_fail	class_i[0x3]	118	1			T4	2		T9	3		T218	5