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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.72 100.00 100.00 100.00 99.38 99.60


Total test records in report: 839
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T137 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2653043909 Jul 06 05:31:00 PM PDT 24 Jul 06 05:33:24 PM PDT 24 23987553178 ps
T148 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2573170666 Jul 06 05:30:47 PM PDT 24 Jul 06 05:46:02 PM PDT 24 58222581773 ps
T168 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1936487090 Jul 06 05:30:25 PM PDT 24 Jul 06 05:32:00 PM PDT 24 4769627313 ps
T170 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1741487199 Jul 06 05:30:48 PM PDT 24 Jul 06 05:31:31 PM PDT 24 318082832 ps
T775 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3445290774 Jul 06 05:30:37 PM PDT 24 Jul 06 05:31:01 PM PDT 24 184949305 ps
T776 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4226019339 Jul 06 05:30:50 PM PDT 24 Jul 06 05:30:52 PM PDT 24 21177877 ps
T150 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2969615389 Jul 06 05:30:38 PM PDT 24 Jul 06 05:41:41 PM PDT 24 4835870349 ps
T173 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3854569611 Jul 06 05:30:38 PM PDT 24 Jul 06 05:32:08 PM PDT 24 14755600217 ps
T171 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4244867876 Jul 06 05:30:41 PM PDT 24 Jul 06 05:30:46 PM PDT 24 63187329 ps
T777 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.215133604 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:48 PM PDT 24 69974699 ps
T142 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3646012806 Jul 06 05:30:25 PM PDT 24 Jul 06 05:47:04 PM PDT 24 48354864553 ps
T175 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1126229906 Jul 06 05:30:51 PM PDT 24 Jul 06 05:32:04 PM PDT 24 4410938660 ps
T778 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.57930357 Jul 06 05:31:00 PM PDT 24 Jul 06 05:31:01 PM PDT 24 20162040 ps
T779 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2313400690 Jul 06 05:31:00 PM PDT 24 Jul 06 05:31:02 PM PDT 24 6513641 ps
T140 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3950316534 Jul 06 05:30:53 PM PDT 24 Jul 06 05:34:59 PM PDT 24 14785572293 ps
T156 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.140691435 Jul 06 05:30:40 PM PDT 24 Jul 06 05:32:58 PM PDT 24 1706871819 ps
T780 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1372325761 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:45 PM PDT 24 66990516 ps
T180 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1396011207 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:46 PM PDT 24 183393625 ps
T161 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1039082854 Jul 06 05:30:39 PM PDT 24 Jul 06 05:32:12 PM PDT 24 770197363 ps
T781 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.173345820 Jul 06 05:30:58 PM PDT 24 Jul 06 05:31:04 PM PDT 24 106978210 ps
T782 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.340238456 Jul 06 05:30:41 PM PDT 24 Jul 06 05:30:44 PM PDT 24 6333084 ps
T138 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.523025179 Jul 06 05:30:51 PM PDT 24 Jul 06 05:36:35 PM PDT 24 5951974276 ps
T783 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2661179273 Jul 06 05:30:42 PM PDT 24 Jul 06 05:30:45 PM PDT 24 11040141 ps
T784 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3247720240 Jul 06 05:30:42 PM PDT 24 Jul 06 05:30:52 PM PDT 24 181380444 ps
T785 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3950162191 Jul 06 05:31:07 PM PDT 24 Jul 06 05:31:15 PM PDT 24 183605289 ps
T786 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1911721857 Jul 06 05:30:43 PM PDT 24 Jul 06 05:31:33 PM PDT 24 1337532648 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4078593965 Jul 06 05:30:24 PM PDT 24 Jul 06 05:30:45 PM PDT 24 1043967626 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2329157668 Jul 06 05:30:30 PM PDT 24 Jul 06 05:31:18 PM PDT 24 4249666732 ps
T789 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3721476585 Jul 06 05:30:35 PM PDT 24 Jul 06 05:30:42 PM PDT 24 101310970 ps
T790 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1233905040 Jul 06 05:30:45 PM PDT 24 Jul 06 05:30:47 PM PDT 24 10461155 ps
T791 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2141167744 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:54 PM PDT 24 100820588 ps
T792 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1477576489 Jul 06 05:30:49 PM PDT 24 Jul 06 05:30:54 PM PDT 24 21264862 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.401846363 Jul 06 05:30:47 PM PDT 24 Jul 06 05:30:52 PM PDT 24 64512605 ps
T169 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2085681545 Jul 06 05:30:53 PM PDT 24 Jul 06 05:30:56 PM PDT 24 118488344 ps
T794 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3943385366 Jul 06 05:30:43 PM PDT 24 Jul 06 05:31:06 PM PDT 24 249476317 ps
T795 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1312275659 Jul 06 05:30:57 PM PDT 24 Jul 06 05:30:59 PM PDT 24 6358832 ps
T796 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.289690247 Jul 06 05:30:45 PM PDT 24 Jul 06 05:30:48 PM PDT 24 39024409 ps
T158 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1174800519 Jul 06 05:30:50 PM PDT 24 Jul 06 05:33:15 PM PDT 24 8616326517 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3679207326 Jul 06 05:30:24 PM PDT 24 Jul 06 05:30:35 PM PDT 24 184952086 ps
T798 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2869379894 Jul 06 05:30:51 PM PDT 24 Jul 06 05:30:58 PM PDT 24 36545813 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4163794144 Jul 06 05:30:44 PM PDT 24 Jul 06 05:30:47 PM PDT 24 7625194 ps
T800 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2520062316 Jul 06 05:30:54 PM PDT 24 Jul 06 05:30:56 PM PDT 24 10102349 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1451932819 Jul 06 05:30:34 PM PDT 24 Jul 06 05:39:44 PM PDT 24 34139073540 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2671299029 Jul 06 05:30:26 PM PDT 24 Jul 06 05:30:28 PM PDT 24 35937956 ps
T803 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4166637808 Jul 06 05:30:40 PM PDT 24 Jul 06 05:31:01 PM PDT 24 1205674743 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.294990806 Jul 06 05:30:39 PM PDT 24 Jul 06 05:30:49 PM PDT 24 135958900 ps
T805 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3525961540 Jul 06 05:30:37 PM PDT 24 Jul 06 05:30:42 PM PDT 24 180258660 ps
T806 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3276305612 Jul 06 05:30:52 PM PDT 24 Jul 06 05:31:00 PM PDT 24 17123982 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3316965155 Jul 06 05:30:24 PM PDT 24 Jul 06 05:30:29 PM PDT 24 40951246 ps
T808 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3555062280 Jul 06 05:30:54 PM PDT 24 Jul 06 05:31:20 PM PDT 24 368263436 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2677154516 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:52 PM PDT 24 128658116 ps
T810 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1779880783 Jul 06 05:30:50 PM PDT 24 Jul 06 05:30:52 PM PDT 24 10540615 ps
T811 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.27151344 Jul 06 05:31:01 PM PDT 24 Jul 06 05:31:03 PM PDT 24 33233220 ps
T812 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3270306232 Jul 06 05:30:42 PM PDT 24 Jul 06 05:32:51 PM PDT 24 24053480149 ps
T152 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1276032675 Jul 06 05:30:40 PM PDT 24 Jul 06 05:34:46 PM PDT 24 4382458673 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.437023265 Jul 06 05:30:33 PM PDT 24 Jul 06 05:30:35 PM PDT 24 8433011 ps
T814 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2131840547 Jul 06 05:30:50 PM PDT 24 Jul 06 05:30:52 PM PDT 24 7798294 ps
T155 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3645305763 Jul 06 05:30:43 PM PDT 24 Jul 06 05:41:58 PM PDT 24 19085036481 ps
T815 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4209939191 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:43 PM PDT 24 11235468 ps
T816 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2853387319 Jul 06 05:30:49 PM PDT 24 Jul 06 05:30:50 PM PDT 24 7369621 ps
T159 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.898089547 Jul 06 05:30:19 PM PDT 24 Jul 06 05:42:05 PM PDT 24 17210399415 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.978094666 Jul 06 05:30:22 PM PDT 24 Jul 06 05:32:48 PM PDT 24 2116697888 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1500058693 Jul 06 05:30:43 PM PDT 24 Jul 06 05:30:57 PM PDT 24 623206500 ps
T819 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3798115356 Jul 06 05:30:49 PM PDT 24 Jul 06 05:30:51 PM PDT 24 10024036 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3090645976 Jul 06 05:30:44 PM PDT 24 Jul 06 05:30:51 PM PDT 24 72349255 ps
T821 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3305535488 Jul 06 05:30:50 PM PDT 24 Jul 06 05:30:52 PM PDT 24 15581361 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1479719031 Jul 06 05:30:26 PM PDT 24 Jul 06 05:30:30 PM PDT 24 65360480 ps
T823 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2653024171 Jul 06 05:30:50 PM PDT 24 Jul 06 05:30:52 PM PDT 24 24896811 ps
T824 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.543590492 Jul 06 05:30:51 PM PDT 24 Jul 06 05:31:15 PM PDT 24 1495557061 ps
T154 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.207332833 Jul 06 05:30:42 PM PDT 24 Jul 06 05:33:39 PM PDT 24 2187206216 ps
T825 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2669871134 Jul 06 05:30:29 PM PDT 24 Jul 06 05:30:33 PM PDT 24 137169733 ps
T157 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3856542160 Jul 06 05:30:51 PM PDT 24 Jul 06 05:50:19 PM PDT 24 193848825623 ps
T172 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2767165109 Jul 06 05:30:40 PM PDT 24 Jul 06 05:31:18 PM PDT 24 470469911 ps
T826 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2144398087 Jul 06 05:30:51 PM PDT 24 Jul 06 05:31:28 PM PDT 24 6279361165 ps
T827 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3361507185 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:47 PM PDT 24 103846854 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3926400728 Jul 06 05:30:39 PM PDT 24 Jul 06 05:30:50 PM PDT 24 496038958 ps
T829 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3559672881 Jul 06 05:30:37 PM PDT 24 Jul 06 05:33:11 PM PDT 24 4494950162 ps
T830 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1410658537 Jul 06 05:30:59 PM PDT 24 Jul 06 05:31:05 PM PDT 24 258132036 ps
T160 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1068464496 Jul 06 05:30:42 PM PDT 24 Jul 06 05:36:49 PM PDT 24 46764069850 ps
T181 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.719521558 Jul 06 05:31:05 PM PDT 24 Jul 06 05:31:09 PM PDT 24 54497119 ps
T831 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3861511980 Jul 06 05:30:39 PM PDT 24 Jul 06 05:30:51 PM PDT 24 1266082445 ps
T832 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3603639088 Jul 06 05:30:54 PM PDT 24 Jul 06 05:30:56 PM PDT 24 8990030 ps
T833 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3819429363 Jul 06 05:30:42 PM PDT 24 Jul 06 05:30:51 PM PDT 24 150522721 ps
T834 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1837901581 Jul 06 05:30:23 PM PDT 24 Jul 06 05:30:29 PM PDT 24 45306112 ps
T835 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1146478064 Jul 06 05:30:54 PM PDT 24 Jul 06 05:30:56 PM PDT 24 10977419 ps
T836 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3183959713 Jul 06 05:30:26 PM PDT 24 Jul 06 05:34:44 PM PDT 24 2943363746 ps
T837 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1005394195 Jul 06 05:30:40 PM PDT 24 Jul 06 05:30:50 PM PDT 24 248349295 ps
T838 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2742288830 Jul 06 05:30:38 PM PDT 24 Jul 06 05:38:51 PM PDT 24 6799255009 ps
T839 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3604324517 Jul 06 05:30:38 PM PDT 24 Jul 06 05:30:43 PM PDT 24 36348999 ps

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.301168873
Short name T8
Test name
Test status
Simulation time 134430471628 ps
CPU time 6344.81 seconds
Started Jul 06 05:32:40 PM PDT 24
Finished Jul 06 07:18:26 PM PDT 24
Peak memory 395568 kb
Host smart-b6bef46a-317f-4b7e-ba03-2038f819ee37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301168873 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.301168873
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1155296681
Short name T10
Test name
Test status
Simulation time 1226946110 ps
CPU time 19.77 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:31:26 PM PDT 24
Peak memory 267472 kb
Host smart-05558126-b75c-40ea-85a7-3bca381529bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1155296681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1155296681
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3436449024
Short name T23
Test name
Test status
Simulation time 294388758782 ps
CPU time 4596.41 seconds
Started Jul 06 05:32:14 PM PDT 24
Finished Jul 06 06:48:51 PM PDT 24
Peak memory 306212 kb
Host smart-f31da162-e2b5-42ed-a8ed-248b22837629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436449024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3436449024
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2767093777
Short name T15
Test name
Test status
Simulation time 227891646 ps
CPU time 13.02 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:31:23 PM PDT 24
Peak memory 249216 kb
Host smart-ea415840-fd96-4e5b-a1d0-095e63c822dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2767093777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2767093777
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3204834425
Short name T163
Test name
Test status
Simulation time 2052328129 ps
CPU time 48.43 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:31:29 PM PDT 24
Peak memory 237572 kb
Host smart-bd82617a-5424-4ef5-89e8-e44c735e4439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3204834425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3204834425
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3047987323
Short name T188
Test name
Test status
Simulation time 48918430013 ps
CPU time 2978.52 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 06:20:55 PM PDT 24
Peak memory 306112 kb
Host smart-d17837bc-c8ff-485b-baa6-b60583632192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047987323 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3047987323
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2954018096
Short name T33
Test name
Test status
Simulation time 435533450539 ps
CPU time 4395.97 seconds
Started Jul 06 05:31:14 PM PDT 24
Finished Jul 06 06:44:31 PM PDT 24
Peak memory 355812 kb
Host smart-f8cecc5c-9da6-49ee-8b51-633554e6fd9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954018096 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2954018096
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.676567356
Short name T104
Test name
Test status
Simulation time 41889037006 ps
CPU time 2463.93 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 06:12:29 PM PDT 24
Peak memory 284284 kb
Host smart-0463c8f3-9a10-431b-8bb8-456bdc39f906
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676567356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.676567356
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2532279667
Short name T129
Test name
Test status
Simulation time 18281893860 ps
CPU time 1217.55 seconds
Started Jul 06 05:30:28 PM PDT 24
Finished Jul 06 05:50:46 PM PDT 24
Peak memory 265412 kb
Host smart-0aaba418-337b-4e73-9fe8-e8ececcc29c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532279667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2532279667
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3286410256
Short name T93
Test name
Test status
Simulation time 318369679068 ps
CPU time 4170.02 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 06:40:41 PM PDT 24
Peak memory 306088 kb
Host smart-5500ede2-c3f5-4dae-93e3-eb53c97cb5da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286410256 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3286410256
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1936516607
Short name T124
Test name
Test status
Simulation time 84828910528 ps
CPU time 2688.39 seconds
Started Jul 06 05:32:44 PM PDT 24
Finished Jul 06 06:17:33 PM PDT 24
Peak memory 290376 kb
Host smart-f07a028e-4008-4d47-b3ed-17f52408cef5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936516607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1936516607
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2247946749
Short name T62
Test name
Test status
Simulation time 34022447165 ps
CPU time 1979.97 seconds
Started Jul 06 05:33:06 PM PDT 24
Finished Jul 06 06:06:07 PM PDT 24
Peak memory 301952 kb
Host smart-c66d20cf-ed14-4ad6-b6cd-58e729c79245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247946749 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2247946749
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.523025179
Short name T138
Test name
Test status
Simulation time 5951974276 ps
CPU time 342.76 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:36:35 PM PDT 24
Peak memory 265356 kb
Host smart-a2936e52-36d9-41ec-b115-ab3464b46cbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=523025179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.523025179
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2897607106
Short name T24
Test name
Test status
Simulation time 41653633997 ps
CPU time 1055.48 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:48:24 PM PDT 24
Peak memory 290052 kb
Host smart-fb683a55-46cf-44ea-a350-7fc105216cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897607106 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2897607106
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2897702196
Short name T125
Test name
Test status
Simulation time 9826765038 ps
CPU time 310.87 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:35:49 PM PDT 24
Peak memory 265396 kb
Host smart-ef64f840-17e6-488a-9e70-8bd65301af79
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897702196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2897702196
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.243612492
Short name T218
Test name
Test status
Simulation time 103665190937 ps
CPU time 2774.04 seconds
Started Jul 06 05:31:52 PM PDT 24
Finished Jul 06 06:18:07 PM PDT 24
Peak memory 289300 kb
Host smart-a9c5feb8-f459-41dd-b566-8fcf6358df37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243612492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.243612492
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1643720076
Short name T139
Test name
Test status
Simulation time 5086051329 ps
CPU time 349.51 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:36:30 PM PDT 24
Peak memory 272684 kb
Host smart-57ea7a31-2e27-4f2a-b60c-8e0a1e818cd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1643720076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1643720076
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1775612285
Short name T5
Test name
Test status
Simulation time 46842018486 ps
CPU time 500.29 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 05:39:32 PM PDT 24
Peak memory 248204 kb
Host smart-f225c0b1-1f19-47d6-941a-ca9fbe9b2019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775612285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1775612285
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2969615389
Short name T150
Test name
Test status
Simulation time 4835870349 ps
CPU time 662.69 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:41:41 PM PDT 24
Peak memory 273100 kb
Host smart-c4ba4d25-ea2a-4bbf-b3bb-336c28148bb7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969615389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2969615389
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.725948028
Short name T231
Test name
Test status
Simulation time 18676417 ps
CPU time 1.51 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 236628 kb
Host smart-ec574d64-9962-4caf-b80e-d806e227e4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=725948028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.725948028
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.681114295
Short name T296
Test name
Test status
Simulation time 62216913106 ps
CPU time 3283.68 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 06:27:00 PM PDT 24
Peak memory 290252 kb
Host smart-73e7e68a-97ae-4ea1-8afc-3764c03f4749
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681114295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.681114295
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.547263806
Short name T221
Test name
Test status
Simulation time 45430822971 ps
CPU time 1417.35 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 05:55:11 PM PDT 24
Peak memory 273980 kb
Host smart-a5e20512-d677-400d-89d4-1c6ea6328baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547263806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.547263806
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.433841329
Short name T9
Test name
Test status
Simulation time 19082830200 ps
CPU time 399.98 seconds
Started Jul 06 05:31:17 PM PDT 24
Finished Jul 06 05:37:58 PM PDT 24
Peak memory 249420 kb
Host smart-d4c9f4ff-baf7-4131-a9fc-391ae4cb49ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433841329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.433841329
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3646012806
Short name T142
Test name
Test status
Simulation time 48354864553 ps
CPU time 999.11 seconds
Started Jul 06 05:30:25 PM PDT 24
Finished Jul 06 05:47:04 PM PDT 24
Peak memory 265456 kb
Host smart-2be04291-6fb7-4238-89ea-c27ff03accf3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646012806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3646012806
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2949994006
Short name T327
Test name
Test status
Simulation time 216551794412 ps
CPU time 2893.74 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 06:19:50 PM PDT 24
Peak memory 290340 kb
Host smart-d23475c4-a008-4c33-a5a6-d0e94eedc4c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949994006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2949994006
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1038839208
Short name T301
Test name
Test status
Simulation time 14882998567 ps
CPU time 588.41 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 05:41:31 PM PDT 24
Peak memory 249360 kb
Host smart-6f7ee5cf-0562-4085-8f10-b0599a650b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038839208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1038839208
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3090554959
Short name T20
Test name
Test status
Simulation time 114526423643 ps
CPU time 1597.93 seconds
Started Jul 06 05:31:14 PM PDT 24
Finished Jul 06 05:57:52 PM PDT 24
Peak memory 283644 kb
Host smart-ed43e558-5153-4bb9-b48b-de3505981864
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090554959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3090554959
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.703008322
Short name T130
Test name
Test status
Simulation time 62705122203 ps
CPU time 1079.43 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:48:38 PM PDT 24
Peak memory 265492 kb
Host smart-4b94f08b-ebb9-480c-8b82-3ddc1c59619a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703008322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.703008322
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.806721413
Short name T2
Test name
Test status
Simulation time 141135792144 ps
CPU time 1606.7 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:57:57 PM PDT 24
Peak memory 273340 kb
Host smart-118325c3-986a-489a-b5d5-74a4a0929400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806721413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.806721413
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2197794453
Short name T149
Test name
Test status
Simulation time 1969177430 ps
CPU time 102.63 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:32:24 PM PDT 24
Peak memory 265300 kb
Host smart-d8511020-f7c5-49b6-b545-5620cc021eb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2197794453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2197794453
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.123462882
Short name T4
Test name
Test status
Simulation time 50738135620 ps
CPU time 482.22 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:38:56 PM PDT 24
Peak memory 249400 kb
Host smart-6168066e-897f-4d3d-86c4-d59cfc22893f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123462882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.123462882
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1651191696
Short name T145
Test name
Test status
Simulation time 7306450140 ps
CPU time 635.7 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:41:16 PM PDT 24
Peak memory 265444 kb
Host smart-c7c81132-57da-4c14-96d6-50f17b3b1a76
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651191696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1651191696
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2735188281
Short name T313
Test name
Test status
Simulation time 31255489814 ps
CPU time 1719.06 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 06:00:03 PM PDT 24
Peak memory 273952 kb
Host smart-627b1f27-db66-4ec6-bf7d-06c0c2fe6b38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735188281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2735188281
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3936414252
Short name T143
Test name
Test status
Simulation time 12270588933 ps
CPU time 900.69 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:45:38 PM PDT 24
Peak memory 265612 kb
Host smart-642abfe6-3ab5-4e90-a456-0924167e491a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936414252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3936414252
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.363879399
Short name T166
Test name
Test status
Simulation time 20677424 ps
CPU time 1.45 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:30:41 PM PDT 24
Peak memory 237580 kb
Host smart-46ad6595-6e1a-4cf8-9709-183d624f01bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=363879399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.363879399
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.960853439
Short name T117
Test name
Test status
Simulation time 8393468501 ps
CPU time 318.6 seconds
Started Jul 06 05:31:29 PM PDT 24
Finished Jul 06 05:36:48 PM PDT 24
Peak memory 257024 kb
Host smart-657ce3e5-3f2e-430b-bdfd-1a7b8e470070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960853439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.960853439
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.237483096
Short name T109
Test name
Test status
Simulation time 92255879843 ps
CPU time 3125.35 seconds
Started Jul 06 05:32:12 PM PDT 24
Finished Jul 06 06:24:18 PM PDT 24
Peak memory 301680 kb
Host smart-c96010c8-6ccd-4284-8589-6898a34dad89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237483096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.237483096
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3671578264
Short name T51
Test name
Test status
Simulation time 1050576739 ps
CPU time 109.52 seconds
Started Jul 06 05:31:22 PM PDT 24
Finished Jul 06 05:33:12 PM PDT 24
Peak memory 257344 kb
Host smart-9aaba44e-2b6a-41d1-b994-3befbe714aca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671578264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3671578264
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2359020405
Short name T91
Test name
Test status
Simulation time 57849481259 ps
CPU time 1343.05 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:54:00 PM PDT 24
Peak memory 273908 kb
Host smart-6a82f576-b972-487f-9190-205fcd455660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359020405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2359020405
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3396753326
Short name T330
Test name
Test status
Simulation time 77770184316 ps
CPU time 2652.05 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 06:15:55 PM PDT 24
Peak memory 290292 kb
Host smart-9ec7283f-3c53-49bb-a436-61ab1dfad9a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396753326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3396753326
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1400928695
Short name T178
Test name
Test status
Simulation time 176066792 ps
CPU time 4.04 seconds
Started Jul 06 05:30:30 PM PDT 24
Finished Jul 06 05:30:34 PM PDT 24
Peak memory 237560 kb
Host smart-1bf4c5f1-13bc-46cf-bc1d-fee16eff377b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1400928695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1400928695
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1174800519
Short name T158
Test name
Test status
Simulation time 8616326517 ps
CPU time 144.7 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:33:15 PM PDT 24
Peak memory 265376 kb
Host smart-b4811a8e-ce59-461f-abe2-9bdb6dfb5603
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174800519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1174800519
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2888873636
Short name T94
Test name
Test status
Simulation time 21317313227 ps
CPU time 1088.27 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:49:46 PM PDT 24
Peak memory 289840 kb
Host smart-ac85138a-68f5-41d5-8650-018ea83d2500
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888873636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2888873636
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2298809242
Short name T63
Test name
Test status
Simulation time 6979705344 ps
CPU time 807.8 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 05:45:15 PM PDT 24
Peak memory 285740 kb
Host smart-74c6f301-5141-49ba-a6c6-017b7d58cee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298809242 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2298809242
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2955796080
Short name T565
Test name
Test status
Simulation time 42518557600 ps
CPU time 401.02 seconds
Started Jul 06 05:31:46 PM PDT 24
Finished Jul 06 05:38:28 PM PDT 24
Peak memory 249272 kb
Host smart-eae5f1b0-8019-4f51-811a-3175f2c84303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955796080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2955796080
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3401788558
Short name T262
Test name
Test status
Simulation time 46229708380 ps
CPU time 2698.73 seconds
Started Jul 06 05:32:35 PM PDT 24
Finished Jul 06 06:17:34 PM PDT 24
Peak memory 289700 kb
Host smart-eb07d4cf-dc2a-4e58-9e19-f718e26b7c45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401788558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3401788558
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3029951781
Short name T37
Test name
Test status
Simulation time 31269210498 ps
CPU time 1804.17 seconds
Started Jul 06 05:32:39 PM PDT 24
Finished Jul 06 06:02:44 PM PDT 24
Peak memory 273932 kb
Host smart-7809b400-b625-4f0f-a0b2-45c1ad7ad6b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029951781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3029951781
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3662903716
Short name T335
Test name
Test status
Simulation time 34118798591 ps
CPU time 2079.61 seconds
Started Jul 06 05:32:37 PM PDT 24
Finished Jul 06 06:07:17 PM PDT 24
Peak memory 282080 kb
Host smart-a1fdbe05-b10c-423d-b73b-d9ebce18bd45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662903716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3662903716
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2029285764
Short name T77
Test name
Test status
Simulation time 174258111708 ps
CPU time 2537 seconds
Started Jul 06 05:30:45 PM PDT 24
Finished Jul 06 06:13:03 PM PDT 24
Peak memory 290152 kb
Host smart-86928ebe-7f3b-43d6-8385-259fbd4750a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029285764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2029285764
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.717327324
Short name T205
Test name
Test status
Simulation time 12987924 ps
CPU time 2.63 seconds
Started Jul 06 05:31:02 PM PDT 24
Finished Jul 06 05:31:05 PM PDT 24
Peak memory 249548 kb
Host smart-33301f3e-6339-4afe-8b62-3668d897caa9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=717327324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.717327324
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1971352118
Short name T204
Test name
Test status
Simulation time 51399101 ps
CPU time 2.16 seconds
Started Jul 06 05:31:02 PM PDT 24
Finished Jul 06 05:31:04 PM PDT 24
Peak memory 249440 kb
Host smart-7c407fb0-0dea-4058-8d18-7d2b344cddce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1971352118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1971352118
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2090133351
Short name T210
Test name
Test status
Simulation time 32235829 ps
CPU time 2.49 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 05:31:13 PM PDT 24
Peak memory 249580 kb
Host smart-7cb757c3-8714-42b0-b750-61ee670a714e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2090133351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2090133351
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3266175511
Short name T208
Test name
Test status
Simulation time 616836240 ps
CPU time 3.47 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:31:38 PM PDT 24
Peak memory 249536 kb
Host smart-2b9d9096-199f-4887-8d87-b531570314aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3266175511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3266175511
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2821138224
Short name T132
Test name
Test status
Simulation time 2059109767 ps
CPU time 213.96 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:33:52 PM PDT 24
Peak memory 265388 kb
Host smart-410b9d34-4f9a-4850-bcb9-b53597b1683b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2821138224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2821138224
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1068464496
Short name T160
Test name
Test status
Simulation time 46764069850 ps
CPU time 364.87 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:36:49 PM PDT 24
Peak memory 265436 kb
Host smart-529a671a-c8dc-456a-b0db-2e0345a0e169
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1068464496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1068464496
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3934948768
Short name T267
Test name
Test status
Simulation time 126556365943 ps
CPU time 4121.19 seconds
Started Jul 06 05:31:25 PM PDT 24
Finished Jul 06 06:40:07 PM PDT 24
Peak memory 316768 kb
Host smart-d631cd43-a1a9-4909-a0cd-015ff052b43d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934948768 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3934948768
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.66710672
Short name T235
Test name
Test status
Simulation time 166051287260 ps
CPU time 5215.49 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 06:58:43 PM PDT 24
Peak memory 306580 kb
Host smart-98df778a-155d-4250-907c-72e30ba24d31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66710672 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.66710672
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1564330252
Short name T228
Test name
Test status
Simulation time 1144780677 ps
CPU time 29.29 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 05:33:30 PM PDT 24
Peak memory 248828 kb
Host smart-f222a5b1-0c87-455d-ac55-5773cd02f024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
30252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1564330252
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.311710725
Short name T288
Test name
Test status
Simulation time 4073352809 ps
CPU time 59.37 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:32:30 PM PDT 24
Peak memory 249760 kb
Host smart-ca0c55d2-4c4b-4f8e-b1ec-35c13093dfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31171
0725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.311710725
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3854569611
Short name T173
Test name
Test status
Simulation time 14755600217 ps
CPU time 88.93 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:32:08 PM PDT 24
Peak memory 240588 kb
Host smart-eea5df62-efbc-486d-8e52-26a499c49538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3854569611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3854569611
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2742288830
Short name T838
Test name
Test status
Simulation time 6799255009 ps
CPU time 492.77 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:38:51 PM PDT 24
Peak memory 268316 kb
Host smart-8e274536-1d51-4cb0-927b-0e3a5857daf8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742288830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2742288830
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.443753955
Short name T1
Test name
Test status
Simulation time 44968143127 ps
CPU time 839.5 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 05:45:19 PM PDT 24
Peak memory 265772 kb
Host smart-5b1dd1f7-1de1-4244-9f35-4bb59d732c8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443753955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.443753955
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1779810054
Short name T349
Test name
Test status
Simulation time 6625531 ps
CPU time 1.48 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 05:30:48 PM PDT 24
Peak memory 236612 kb
Host smart-4ac58ee2-5b2d-4ee5-84cd-baf3987c53a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1779810054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1779810054
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1396082027
Short name T307
Test name
Test status
Simulation time 5535252420 ps
CPU time 190.54 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:34:02 PM PDT 24
Peak memory 249652 kb
Host smart-8017aa09-95e2-4846-9daf-27b458c47ee3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396082027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1396082027
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3195737761
Short name T189
Test name
Test status
Simulation time 59051141572 ps
CPU time 6527.42 seconds
Started Jul 06 05:30:58 PM PDT 24
Finished Jul 06 07:19:46 PM PDT 24
Peak memory 371612 kb
Host smart-d686795c-ffe6-4f19-b8d6-cd41ec6ad8c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195737761 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3195737761
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3834871139
Short name T314
Test name
Test status
Simulation time 9463826887 ps
CPU time 391.16 seconds
Started Jul 06 05:31:08 PM PDT 24
Finished Jul 06 05:37:40 PM PDT 24
Peak memory 249352 kb
Host smart-0d48709d-7b75-4aa2-b178-d8e96f31f16a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834871139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3834871139
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2855727131
Short name T280
Test name
Test status
Simulation time 44615186330 ps
CPU time 2465.91 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 06:12:13 PM PDT 24
Peak memory 289368 kb
Host smart-2ff44f4c-ab42-4ede-9637-d42c06221c6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855727131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2855727131
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3761166004
Short name T278
Test name
Test status
Simulation time 1174184505 ps
CPU time 34.48 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:32:05 PM PDT 24
Peak memory 250320 kb
Host smart-df0c0b12-32e5-4543-8baa-9b3018ef8375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37611
66004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3761166004
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.125233449
Short name T553
Test name
Test status
Simulation time 5025000115 ps
CPU time 74.11 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 05:32:34 PM PDT 24
Peak memory 256736 kb
Host smart-d3328f77-0dfa-4d18-9ac1-edd3470a0461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
3449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.125233449
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2859407982
Short name T74
Test name
Test status
Simulation time 50969326262 ps
CPU time 1558.81 seconds
Started Jul 06 05:31:23 PM PDT 24
Finished Jul 06 05:57:22 PM PDT 24
Peak memory 290088 kb
Host smart-a3237000-5610-4d3d-aa6d-a6803dfa2443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859407982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2859407982
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.197808739
Short name T343
Test name
Test status
Simulation time 27447037933 ps
CPU time 1740.94 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 06:00:37 PM PDT 24
Peak memory 273188 kb
Host smart-ef9f576e-e595-46b7-b70b-2e267149f5e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197808739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.197808739
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1808391835
Short name T291
Test name
Test status
Simulation time 4905124095 ps
CPU time 71.66 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:32:51 PM PDT 24
Peak memory 250344 kb
Host smart-9362e487-d6da-4a36-bd3b-43a701feb178
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808391835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1808391835
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3212868746
Short name T275
Test name
Test status
Simulation time 21806153396 ps
CPU time 76.84 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 05:33:04 PM PDT 24
Peak memory 257576 kb
Host smart-576b24e0-ff96-4ea7-8b56-5f0e2f64e2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
68746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3212868746
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1083951100
Short name T328
Test name
Test status
Simulation time 21296190460 ps
CPU time 706.44 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 272056 kb
Host smart-a993de86-3381-42cf-87d3-ec7b4f43ab68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083951100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1083951100
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3070230678
Short name T65
Test name
Test status
Simulation time 247122179385 ps
CPU time 2890.02 seconds
Started Jul 06 05:32:08 PM PDT 24
Finished Jul 06 06:20:19 PM PDT 24
Peak memory 323132 kb
Host smart-63be1795-2077-48fb-bde6-73307ac75dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070230678 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3070230678
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2536250338
Short name T284
Test name
Test status
Simulation time 9621564380 ps
CPU time 66.44 seconds
Started Jul 06 05:32:13 PM PDT 24
Finished Jul 06 05:33:20 PM PDT 24
Peak memory 256480 kb
Host smart-457681d8-543c-4bba-b3b4-eee71e88e6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25362
50338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2536250338
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.700995580
Short name T196
Test name
Test status
Simulation time 5691802525 ps
CPU time 295.42 seconds
Started Jul 06 05:32:41 PM PDT 24
Finished Jul 06 05:37:37 PM PDT 24
Peak memory 257548 kb
Host smart-f9563b1c-57eb-4e18-a870-a2528bf4912e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70099
5580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.700995580
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3483649897
Short name T277
Test name
Test status
Simulation time 935616460 ps
CPU time 61.13 seconds
Started Jul 06 05:32:38 PM PDT 24
Finished Jul 06 05:33:40 PM PDT 24
Peak memory 249284 kb
Host smart-0151dd1c-398c-4501-9147-2b354cfd7037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
49897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3483649897
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3592664335
Short name T12
Test name
Test status
Simulation time 3790920742 ps
CPU time 20.44 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:31:09 PM PDT 24
Peak memory 271756 kb
Host smart-7369db62-5bf9-4749-a848-9f8f4f0baeeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3592664335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3592664335
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3030974149
Short name T84
Test name
Test status
Simulation time 1618163494 ps
CPU time 38.49 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:31:59 PM PDT 24
Peak memory 248920 kb
Host smart-e959edc3-53a2-46f3-8888-b346338fe399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30309
74149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3030974149
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.314522954
Short name T136
Test name
Test status
Simulation time 6786072148 ps
CPU time 223.45 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:34:37 PM PDT 24
Peak memory 265460 kb
Host smart-b93ae9cd-3084-44cc-95ee-66238a2ad067
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=314522954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.314522954
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1117929738
Short name T179
Test name
Test status
Simulation time 2414032384 ps
CPU time 84.83 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:32:10 PM PDT 24
Peak memory 240588 kb
Host smart-82724dd9-641d-4767-9237-5b0127166aec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1117929738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1117929738
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4216395163
Short name T177
Test name
Test status
Simulation time 114999182 ps
CPU time 4.26 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:30:53 PM PDT 24
Peak memory 237428 kb
Host smart-2ee97b90-fd55-4757-b95c-f8c37cc3047c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4216395163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4216395163
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1126229906
Short name T175
Test name
Test status
Simulation time 4410938660 ps
CPU time 72.15 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:32:04 PM PDT 24
Peak memory 240584 kb
Host smart-7d2cdffb-eb0d-468a-9698-1df96253e72c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1126229906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1126229906
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4244867876
Short name T171
Test name
Test status
Simulation time 63187329 ps
CPU time 3.26 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 237600 kb
Host smart-0b6d5419-d407-4924-976c-6aa1450a92b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4244867876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4244867876
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1776228268
Short name T162
Test name
Test status
Simulation time 42053636 ps
CPU time 3.48 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:30:48 PM PDT 24
Peak memory 237600 kb
Host smart-315d9b3d-b272-4e08-8f6a-bae77db211c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1776228268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1776228268
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.498356182
Short name T164
Test name
Test status
Simulation time 614773691 ps
CPU time 41.77 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:31:30 PM PDT 24
Peak memory 240524 kb
Host smart-98547719-e42b-4121-b822-f15703c10a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=498356182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.498356182
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2767165109
Short name T172
Test name
Test status
Simulation time 470469911 ps
CPU time 37.4 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:31:18 PM PDT 24
Peak memory 237624 kb
Host smart-1f5d7935-6acb-46b0-9e14-50511b165f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2767165109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2767165109
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.898089547
Short name T159
Test name
Test status
Simulation time 17210399415 ps
CPU time 705.36 seconds
Started Jul 06 05:30:19 PM PDT 24
Finished Jul 06 05:42:05 PM PDT 24
Peak memory 265468 kb
Host smart-f63d4d6c-6caf-4843-871c-8ab5e0652ef0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898089547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.898089547
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1542238608
Short name T176
Test name
Test status
Simulation time 43973270 ps
CPU time 2.72 seconds
Started Jul 06 05:30:22 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 237536 kb
Host smart-09c9ecb7-0076-40e9-91a1-82a8df7e390c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1542238608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1542238608
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.140649777
Short name T174
Test name
Test status
Simulation time 474437843 ps
CPU time 32.33 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:31:27 PM PDT 24
Peak memory 240472 kb
Host smart-c71d820f-0f75-4a7a-b06f-598e73546e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=140649777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.140649777
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1277504019
Short name T182
Test name
Test status
Simulation time 57638194 ps
CPU time 3.83 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 236424 kb
Host smart-122b4d74-c4e1-4e23-86fe-d2eb510958d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1277504019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1277504019
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1741487199
Short name T170
Test name
Test status
Simulation time 318082832 ps
CPU time 43.09 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:31:31 PM PDT 24
Peak memory 237588 kb
Host smart-9a46432a-809f-4675-b111-e60fd27d2bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1741487199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1741487199
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2085681545
Short name T169
Test name
Test status
Simulation time 118488344 ps
CPU time 2.78 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 237600 kb
Host smart-484d9c6f-cda2-4c97-be93-ac6f69c13ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2085681545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2085681545
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.719521558
Short name T181
Test name
Test status
Simulation time 54497119 ps
CPU time 3.8 seconds
Started Jul 06 05:31:05 PM PDT 24
Finished Jul 06 05:31:09 PM PDT 24
Peak memory 236632 kb
Host smart-256a4a51-a900-4d5d-b86f-987fe6b7c5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=719521558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.719521558
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1936487090
Short name T168
Test name
Test status
Simulation time 4769627313 ps
CPU time 93.86 seconds
Started Jul 06 05:30:25 PM PDT 24
Finished Jul 06 05:32:00 PM PDT 24
Peak memory 240580 kb
Host smart-c7add46d-123a-4021-aaa6-d4db22056983
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1936487090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1936487090
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2050445605
Short name T19
Test name
Test status
Simulation time 20171695883 ps
CPU time 1049.47 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:49:23 PM PDT 24
Peak memory 273052 kb
Host smart-6429f55a-a5fe-48ae-b2f9-69abbb6048f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050445605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2050445605
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.978094666
Short name T817
Test name
Test status
Simulation time 2116697888 ps
CPU time 145.64 seconds
Started Jul 06 05:30:22 PM PDT 24
Finished Jul 06 05:32:48 PM PDT 24
Peak memory 237544 kb
Host smart-6ef27f3c-4168-4c8f-b330-aabb2edd6033
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=978094666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.978094666
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1410569184
Short name T760
Test name
Test status
Simulation time 23312019640 ps
CPU time 206.03 seconds
Started Jul 06 05:30:20 PM PDT 24
Finished Jul 06 05:33:46 PM PDT 24
Peak memory 240604 kb
Host smart-96821e4f-cf72-4212-b7e7-4fa2f2569d34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1410569184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1410569184
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3316965155
Short name T807
Test name
Test status
Simulation time 40951246 ps
CPU time 4.5 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 240472 kb
Host smart-8542b560-73ad-450e-bbc3-b52706b94c37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3316965155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3316965155
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.294990806
Short name T804
Test name
Test status
Simulation time 135958900 ps
CPU time 9.62 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:30:49 PM PDT 24
Peak memory 240624 kb
Host smart-8fa488a7-eed2-4340-b3ba-5712dc134c28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294990806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.294990806
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1005394195
Short name T837
Test name
Test status
Simulation time 248349295 ps
CPU time 8.9 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:50 PM PDT 24
Peak memory 240548 kb
Host smart-806f5ecf-5c21-48c4-9d15-ebd110c0417c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1005394195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1005394195
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.437023265
Short name T813
Test name
Test status
Simulation time 8433011 ps
CPU time 1.59 seconds
Started Jul 06 05:30:33 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 236632 kb
Host smart-2a22a0ff-50e8-44d6-aba2-e6ed2e9e870d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=437023265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.437023265
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2329157668
Short name T788
Test name
Test status
Simulation time 4249666732 ps
CPU time 47.9 seconds
Started Jul 06 05:30:30 PM PDT 24
Finished Jul 06 05:31:18 PM PDT 24
Peak memory 248796 kb
Host smart-0795b272-e073-494b-b961-fe45ec1382a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2329157668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2329157668
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4207784903
Short name T758
Test name
Test status
Simulation time 305980024 ps
CPU time 20.52 seconds
Started Jul 06 05:30:34 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 248592 kb
Host smart-c68577ef-0752-4d6a-a13d-9f67f7ed9b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4207784903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4207784903
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3559672881
Short name T829
Test name
Test status
Simulation time 4494950162 ps
CPU time 153.39 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:33:11 PM PDT 24
Peak memory 237636 kb
Host smart-fc2d6701-df10-4c18-9bed-47d1d8b76787
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3559672881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3559672881
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1451932819
Short name T801
Test name
Test status
Simulation time 34139073540 ps
CPU time 549.29 seconds
Started Jul 06 05:30:34 PM PDT 24
Finished Jul 06 05:39:44 PM PDT 24
Peak memory 237640 kb
Host smart-f4d9d445-4f7c-4c31-a820-1e14111b599b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1451932819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1451932819
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3861511980
Short name T831
Test name
Test status
Simulation time 1266082445 ps
CPU time 10.84 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 249176 kb
Host smart-f393a360-6672-46f2-879c-9b08ff043117
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3861511980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3861511980
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1529532667
Short name T768
Test name
Test status
Simulation time 77804439 ps
CPU time 7.1 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:31 PM PDT 24
Peak memory 240548 kb
Host smart-2d993b65-5569-46bb-b5bd-4014cb222fbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529532667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1529532667
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3169212669
Short name T749
Test name
Test status
Simulation time 64355275 ps
CPU time 3.58 seconds
Started Jul 06 05:30:22 PM PDT 24
Finished Jul 06 05:30:26 PM PDT 24
Peak memory 237532 kb
Host smart-3bd5f722-894e-4694-8f38-82c3e2a55cce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3169212669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3169212669
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.49894892
Short name T165
Test name
Test status
Simulation time 11916400 ps
CPU time 1.26 seconds
Started Jul 06 05:30:33 PM PDT 24
Finished Jul 06 05:30:34 PM PDT 24
Peak memory 236644 kb
Host smart-c741aceb-25af-4005-8c15-b21c53dc77d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49894892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.49894892
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3498334911
Short name T192
Test name
Test status
Simulation time 619444598 ps
CPU time 21.63 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:31:01 PM PDT 24
Peak memory 245808 kb
Host smart-f676dc0e-7f7d-42c5-80ce-ae619786fa63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3498334911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3498334911
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2656603800
Short name T144
Test name
Test status
Simulation time 10318934269 ps
CPU time 150.1 seconds
Started Jul 06 05:30:22 PM PDT 24
Finished Jul 06 05:32:52 PM PDT 24
Peak memory 267820 kb
Host smart-04c0abc3-e801-4025-ac4e-bea4c74abcb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2656603800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2656603800
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1547659273
Short name T151
Test name
Test status
Simulation time 9304279590 ps
CPU time 354.46 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:36:35 PM PDT 24
Peak memory 265528 kb
Host smart-daf7b8df-3d0c-4a92-b0e3-82e0e5cf0929
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547659273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1547659273
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3074145907
Short name T762
Test name
Test status
Simulation time 153938177 ps
CPU time 12.79 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 248556 kb
Host smart-386ce86b-164a-47b7-bc81-5a054fa3fdce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3074145907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3074145907
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1450692746
Short name T736
Test name
Test status
Simulation time 78749017 ps
CPU time 10.55 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 256968 kb
Host smart-6c49639c-f08b-4aec-ab0f-9825b38d9311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450692746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1450692746
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.215133604
Short name T777
Test name
Test status
Simulation time 69974699 ps
CPU time 5.93 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:48 PM PDT 24
Peak memory 240552 kb
Host smart-6023b0f7-6081-4af0-a615-c60b40826bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=215133604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.215133604
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.574339010
Short name T765
Test name
Test status
Simulation time 11776821 ps
CPU time 1.69 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:39 PM PDT 24
Peak memory 236652 kb
Host smart-45677680-6919-4be9-8816-facbf8afcd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=574339010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.574339010
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4166637808
Short name T803
Test name
Test status
Simulation time 1205674743 ps
CPU time 18.65 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:31:01 PM PDT 24
Peak memory 244788 kb
Host smart-4f4525a8-3128-4de7-9424-9a451563e421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4166637808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4166637808
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1039082854
Short name T161
Test name
Test status
Simulation time 770197363 ps
CPU time 92.31 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:32:12 PM PDT 24
Peak memory 257168 kb
Host smart-b050b02f-66d6-40c6-be03-d73bec221561
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1039082854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1039082854
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.345556025
Short name T773
Test name
Test status
Simulation time 880773849 ps
CPU time 15.08 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:31:00 PM PDT 24
Peak memory 255160 kb
Host smart-f81e1fda-d33b-4989-829a-3b26d6b910c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=345556025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.345556025
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1385915362
Short name T721
Test name
Test status
Simulation time 126402231 ps
CPU time 5.61 seconds
Started Jul 06 05:30:35 PM PDT 24
Finished Jul 06 05:30:41 PM PDT 24
Peak memory 248760 kb
Host smart-3db0c569-6c6b-47d5-b07c-d64fe26f3a4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385915362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1385915362
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.601708677
Short name T190
Test name
Test status
Simulation time 50672670 ps
CPU time 4.95 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:30:47 PM PDT 24
Peak memory 236640 kb
Host smart-142ff20e-6c16-4b34-b739-5d0f2e9c47e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=601708677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.601708677
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2313400690
Short name T779
Test name
Test status
Simulation time 6513641 ps
CPU time 1.54 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 236584 kb
Host smart-81eb9295-a06a-4497-bab5-9cab5048bfcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2313400690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2313400690
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1387083075
Short name T191
Test name
Test status
Simulation time 1120202463 ps
CPU time 19.85 seconds
Started Jul 06 05:30:55 PM PDT 24
Finished Jul 06 05:31:16 PM PDT 24
Peak memory 245788 kb
Host smart-c138ff72-a95b-44a7-8c05-a1ba392558a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1387083075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1387083075
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3645305763
Short name T155
Test name
Test status
Simulation time 19085036481 ps
CPU time 673.44 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:41:58 PM PDT 24
Peak memory 273460 kb
Host smart-c744adb9-bd35-4dd6-be22-d29bce35bab1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645305763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3645305763
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1500058693
Short name T818
Test name
Test status
Simulation time 623206500 ps
CPU time 12.81 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 254760 kb
Host smart-c9dbef0e-8665-4496-b3a9-f4f86a9acfe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1500058693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1500058693
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.343927190
Short name T351
Test name
Test status
Simulation time 353960379 ps
CPU time 14.15 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 251896 kb
Host smart-b26650f6-c3c3-48e8-9305-ac6748a05b96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343927190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.343927190
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1239148792
Short name T763
Test name
Test status
Simulation time 64408806 ps
CPU time 3.18 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:45 PM PDT 24
Peak memory 236600 kb
Host smart-35600947-7b6e-4ba4-8250-1c3c83cbbe6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1239148792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1239148792
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.27151344
Short name T811
Test name
Test status
Simulation time 33233220 ps
CPU time 1.48 seconds
Started Jul 06 05:31:01 PM PDT 24
Finished Jul 06 05:31:03 PM PDT 24
Peak memory 236684 kb
Host smart-7be5e36a-ac75-49fb-8898-45c5561f1161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=27151344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.27151344
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3445290774
Short name T775
Test name
Test status
Simulation time 184949305 ps
CPU time 23.88 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:31:01 PM PDT 24
Peak memory 248648 kb
Host smart-dafa5c75-ee92-408e-8221-25516c77ebc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3445290774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3445290774
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2907011965
Short name T146
Test name
Test status
Simulation time 2325892153 ps
CPU time 302.42 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:35:41 PM PDT 24
Peak memory 265736 kb
Host smart-3d32e53b-16c8-4403-a1c7-1e100181ccc5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907011965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2907011965
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2141167744
Short name T791
Test name
Test status
Simulation time 100820588 ps
CPU time 12.3 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 249716 kb
Host smart-c8c8106a-9b03-4c29-b057-38827e9a8cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2141167744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2141167744
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3090645976
Short name T820
Test name
Test status
Simulation time 72349255 ps
CPU time 5.84 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 239000 kb
Host smart-9bed8f3b-6feb-44bc-ad86-59665db26349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090645976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3090645976
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2892928298
Short name T184
Test name
Test status
Simulation time 34904923 ps
CPU time 6.06 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:30:59 PM PDT 24
Peak memory 237572 kb
Host smart-b3b3da9c-bf2d-4925-bff8-178c0d6295d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2892928298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2892928298
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.4249097914
Short name T744
Test name
Test status
Simulation time 8858272 ps
CPU time 1.46 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 237612 kb
Host smart-38fef386-515f-4967-b49e-cccc361a78b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4249097914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4249097914
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.474775159
Short name T194
Test name
Test status
Simulation time 170921531 ps
CPU time 25.7 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:31:11 PM PDT 24
Peak memory 245812 kb
Host smart-5a9f6ffe-80ac-49ec-a776-24ca8a9f0db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=474775159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.474775159
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2633895496
Short name T153
Test name
Test status
Simulation time 8491015836 ps
CPU time 516.73 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:39:21 PM PDT 24
Peak memory 265284 kb
Host smart-4e5f6d99-5c83-42f8-80b7-c59373b3a42b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633895496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2633895496
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3555062280
Short name T808
Test name
Test status
Simulation time 368263436 ps
CPU time 25.13 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:31:20 PM PDT 24
Peak memory 248624 kb
Host smart-b9714751-7781-4357-8ee7-ae843025342f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3555062280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3555062280
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1106758401
Short name T735
Test name
Test status
Simulation time 298126102 ps
CPU time 5.77 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 240580 kb
Host smart-bcf178dc-991f-428f-9701-47bc269f41ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106758401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1106758401
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1477576489
Short name T792
Test name
Test status
Simulation time 21264862 ps
CPU time 3.39 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 236632 kb
Host smart-ab28a509-c8db-4c93-836f-3b06fdc3d222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1477576489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1477576489
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2661179273
Short name T783
Test name
Test status
Simulation time 11040141 ps
CPU time 1.41 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:30:45 PM PDT 24
Peak memory 236664 kb
Host smart-c581dc22-6e93-41b3-96d2-bae7d28dbd6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661179273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2661179273
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2134788806
Short name T728
Test name
Test status
Simulation time 649651835 ps
CPU time 23.99 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:31:07 PM PDT 24
Peak memory 248704 kb
Host smart-4a5f196b-32b5-4ea2-ae42-51192c0ad449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2134788806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2134788806
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3856542160
Short name T157
Test name
Test status
Simulation time 193848825623 ps
CPU time 1167.8 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:50:19 PM PDT 24
Peak memory 265588 kb
Host smart-b1230691-68db-4b21-afeb-6b53c63a1dc8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856542160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3856542160
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1400529497
Short name T727
Test name
Test status
Simulation time 176087090 ps
CPU time 6.47 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:30:58 PM PDT 24
Peak memory 248452 kb
Host smart-09d22544-83a3-4e1c-bdde-0511eadee262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1400529497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1400529497
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.348149232
Short name T353
Test name
Test status
Simulation time 102539395 ps
CPU time 8.22 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:53 PM PDT 24
Peak memory 240780 kb
Host smart-663fc63b-1390-4927-bfcd-5e1b05187c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348149232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.348149232
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2869379894
Short name T798
Test name
Test status
Simulation time 36545813 ps
CPU time 5.92 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:30:58 PM PDT 24
Peak memory 237560 kb
Host smart-1d71dac1-d5ac-4d39-9139-fd3ae627c915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2869379894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2869379894
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4209939191
Short name T815
Test name
Test status
Simulation time 11235468 ps
CPU time 1.4 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 237604 kb
Host smart-f6e470db-b121-4ba9-a9d5-719dc07dd385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209939191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4209939191
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.543590492
Short name T824
Test name
Test status
Simulation time 1495557061 ps
CPU time 23.1 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:31:15 PM PDT 24
Peak memory 248744 kb
Host smart-6ac48dbb-b19e-4739-af39-878237301de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=543590492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.543590492
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.325343213
Short name T141
Test name
Test status
Simulation time 2805688221 ps
CPU time 207.99 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:34:19 PM PDT 24
Peak memory 265448 kb
Host smart-97bfa830-c1c4-42a0-b157-8b79ccbaf091
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=325343213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.325343213
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3397608975
Short name T147
Test name
Test status
Simulation time 17825332356 ps
CPU time 1230.04 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:51:15 PM PDT 24
Peak memory 265428 kb
Host smart-c0b4d7ca-a6ce-446e-916c-8d8c43b35f15
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397608975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3397608975
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3098526049
Short name T757
Test name
Test status
Simulation time 58996037 ps
CPU time 6.65 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 248488 kb
Host smart-b0703188-aae5-4e67-b469-45fcfc5fc649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3098526049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3098526049
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1011401432
Short name T759
Test name
Test status
Simulation time 62391093 ps
CPU time 5.21 seconds
Started Jul 06 05:31:12 PM PDT 24
Finished Jul 06 05:31:17 PM PDT 24
Peak memory 238080 kb
Host smart-ef716fcc-2820-4301-b2e7-6d9c8d800dc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011401432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1011401432
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2491505511
Short name T718
Test name
Test status
Simulation time 132510176 ps
CPU time 9.24 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 237536 kb
Host smart-e440f3fd-e4c4-4e10-8b73-749c0b5c9f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2491505511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2491505511
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1911721857
Short name T786
Test name
Test status
Simulation time 1337532648 ps
CPU time 48.38 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 245676 kb
Host smart-1e3f03f2-167f-4d72-a041-4d1c43cdf9ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1911721857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1911721857
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2126467261
Short name T133
Test name
Test status
Simulation time 16712754422 ps
CPU time 200.75 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:34:06 PM PDT 24
Peak memory 267892 kb
Host smart-cafc60f1-2f34-43ed-886f-20dd37fff538
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2126467261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2126467261
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2323240509
Short name T134
Test name
Test status
Simulation time 12159822340 ps
CPU time 468.28 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:38:29 PM PDT 24
Peak memory 265404 kb
Host smart-54cfe25d-3790-414b-9e83-5b1e9551bae4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323240509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2323240509
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.928040898
Short name T724
Test name
Test status
Simulation time 329508418 ps
CPU time 22.38 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:31:06 PM PDT 24
Peak memory 248560 kb
Host smart-196107de-7cf2-45e5-bf36-847361035c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928040898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.928040898
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1042484073
Short name T734
Test name
Test status
Simulation time 86193325 ps
CPU time 6.89 seconds
Started Jul 06 05:30:55 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 240000 kb
Host smart-cb0450c9-a3b2-432d-8e7b-567b5bf3ff5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042484073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1042484073
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.4191746618
Short name T752
Test name
Test status
Simulation time 64372942 ps
CPU time 5.2 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 05:30:53 PM PDT 24
Peak memory 237428 kb
Host smart-e4141e07-6c42-44c5-80e9-a364471653f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4191746618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.4191746618
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4163794144
Short name T799
Test name
Test status
Simulation time 7625194 ps
CPU time 1.48 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:30:47 PM PDT 24
Peak memory 237624 kb
Host smart-6bb9d75b-1ca0-4eab-883b-3aee856998f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4163794144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4163794144
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4255044280
Short name T742
Test name
Test status
Simulation time 1413429894 ps
CPU time 27.47 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:31:10 PM PDT 24
Peak memory 248716 kb
Host smart-0aee15a2-fd19-48f2-835e-aa824adab9a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4255044280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4255044280
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.207332833
Short name T154
Test name
Test status
Simulation time 2187206216 ps
CPU time 175.1 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:33:39 PM PDT 24
Peak memory 265428 kb
Host smart-aae9e812-fe36-459b-83a2-a52d2dc686a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=207332833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.207332833
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3247720240
Short name T784
Test name
Test status
Simulation time 181380444 ps
CPU time 7.46 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 248808 kb
Host smart-ddd001f8-c99a-4f33-b3d2-50ab9acba4f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3247720240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3247720240
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3445133175
Short name T739
Test name
Test status
Simulation time 94984759 ps
CPU time 7.71 seconds
Started Jul 06 05:30:46 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 240588 kb
Host smart-5e7ecb57-c054-4413-93f8-e6f85b157ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445133175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3445133175
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4058600991
Short name T771
Test name
Test status
Simulation time 35454321 ps
CPU time 3.31 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 237428 kb
Host smart-81a03fcb-4e8e-4d06-a466-9c73e17414c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4058600991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4058600991
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3624425077
Short name T743
Test name
Test status
Simulation time 14838438 ps
CPU time 1.32 seconds
Started Jul 06 05:30:45 PM PDT 24
Finished Jul 06 05:30:47 PM PDT 24
Peak memory 237552 kb
Host smart-d62d449e-bbb0-460c-aac8-29cf49b3f8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3624425077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3624425077
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2144398087
Short name T826
Test name
Test status
Simulation time 6279361165 ps
CPU time 36.87 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:31:28 PM PDT 24
Peak memory 244756 kb
Host smart-52ccc137-9a2c-4fa1-b641-ed3f4c78e887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2144398087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2144398087
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2653043909
Short name T137
Test name
Test status
Simulation time 23987553178 ps
CPU time 143.1 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 05:33:24 PM PDT 24
Peak memory 265464 kb
Host smart-43bd81bf-493f-4ff2-ba37-9e82cd80e583
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2653043909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2653043909
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2573170666
Short name T148
Test name
Test status
Simulation time 58222581773 ps
CPU time 914.41 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 05:46:02 PM PDT 24
Peak memory 265416 kb
Host smart-5c7d4ef8-ef29-4315-a0dd-70b8460a83f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573170666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2573170666
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3679894401
Short name T770
Test name
Test status
Simulation time 159712523 ps
CPU time 10.96 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 248320 kb
Host smart-08c4610b-21da-4753-90c4-9cb553ac8731
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3679894401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3679894401
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1066653574
Short name T769
Test name
Test status
Simulation time 299411773 ps
CPU time 8.9 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:31:03 PM PDT 24
Peak memory 240140 kb
Host smart-dd8b570e-3a3e-48b3-9c88-c3130aa2997c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066653574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1066653574
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3950162191
Short name T785
Test name
Test status
Simulation time 183605289 ps
CPU time 7.86 seconds
Started Jul 06 05:31:07 PM PDT 24
Finished Jul 06 05:31:15 PM PDT 24
Peak memory 240564 kb
Host smart-a5edb7ad-a7a8-4529-9b06-a7a61d58784f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3950162191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3950162191
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.289690247
Short name T796
Test name
Test status
Simulation time 39024409 ps
CPU time 2.63 seconds
Started Jul 06 05:30:45 PM PDT 24
Finished Jul 06 05:30:48 PM PDT 24
Peak memory 236604 kb
Host smart-3f59bca0-6dae-46b6-9453-dfd87d1f9e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289690247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.289690247
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1317710927
Short name T766
Test name
Test status
Simulation time 2626287560 ps
CPU time 41.38 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 05:31:42 PM PDT 24
Peak memory 248800 kb
Host smart-a97a7106-b8b1-4e19-b5a5-bed9cdc17e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1317710927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1317710927
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3950316534
Short name T140
Test name
Test status
Simulation time 14785572293 ps
CPU time 245.78 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:34:59 PM PDT 24
Peak memory 265448 kb
Host smart-d48b52e2-7795-4ec3-82cc-eb37e76b9b6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3950316534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3950316534
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.381581568
Short name T127
Test name
Test status
Simulation time 31007861348 ps
CPU time 555.12 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:40:10 PM PDT 24
Peak memory 265440 kb
Host smart-ca2cde03-40d3-472f-bd22-1f4d1279872a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381581568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.381581568
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.755626491
Short name T755
Test name
Test status
Simulation time 294654324 ps
CPU time 12.68 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:31:05 PM PDT 24
Peak memory 248848 kb
Host smart-38d21888-844d-46f9-a462-9e363e90649e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=755626491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.755626491
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2704710413
Short name T772
Test name
Test status
Simulation time 1914642015 ps
CPU time 128.45 seconds
Started Jul 06 05:31:09 PM PDT 24
Finished Jul 06 05:33:17 PM PDT 24
Peak memory 237672 kb
Host smart-5a715fc0-de05-405b-97b3-3e5385320e97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2704710413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2704710413
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.503767616
Short name T726
Test name
Test status
Simulation time 10193918098 ps
CPU time 540.65 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:39:25 PM PDT 24
Peak memory 240540 kb
Host smart-4935df08-cf8b-4d47-a7c4-e0781c1f8896
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=503767616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.503767616
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3997189233
Short name T733
Test name
Test status
Simulation time 398072115 ps
CPU time 7.94 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 248548 kb
Host smart-6a26079a-df2f-4e13-82e1-284919e8d83c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3997189233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3997189233
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3926400728
Short name T828
Test name
Test status
Simulation time 496038958 ps
CPU time 10.1 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:30:50 PM PDT 24
Peak memory 251808 kb
Host smart-7e364329-8aa2-4708-955a-12c96d110d9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926400728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3926400728
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2669871134
Short name T825
Test name
Test status
Simulation time 137169733 ps
CPU time 4.22 seconds
Started Jul 06 05:30:29 PM PDT 24
Finished Jul 06 05:30:33 PM PDT 24
Peak memory 236608 kb
Host smart-7964cc0d-b8b0-425f-8e66-9a58901a5d8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2669871134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2669871134
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2518086619
Short name T714
Test name
Test status
Simulation time 11848287 ps
CPU time 1.33 seconds
Started Jul 06 05:30:25 PM PDT 24
Finished Jul 06 05:30:27 PM PDT 24
Peak memory 237584 kb
Host smart-c79be04f-add1-42ac-8f35-9fad3c252e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2518086619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2518086619
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3679207326
Short name T797
Test name
Test status
Simulation time 184952086 ps
CPU time 11.42 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 244856 kb
Host smart-54cdb0d3-76aa-4dea-b12e-448366763686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3679207326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3679207326
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3183959713
Short name T836
Test name
Test status
Simulation time 2943363746 ps
CPU time 257.64 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:34:44 PM PDT 24
Peak memory 273124 kb
Host smart-e58f1ae2-c3a7-44f3-9afc-c689f01b1842
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3183959713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3183959713
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3248355392
Short name T774
Test name
Test status
Simulation time 306783903 ps
CPU time 11.75 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 248768 kb
Host smart-2ccc4893-2c5c-4c2b-b1b0-1e9a0c5580d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248355392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3248355392
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1396011207
Short name T180
Test name
Test status
Simulation time 183393625 ps
CPU time 3.98 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 237584 kb
Host smart-7bc0bab4-c173-430c-8d80-a7006be21b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1396011207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1396011207
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1614936983
Short name T716
Test name
Test status
Simulation time 13281038 ps
CPU time 1.41 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:30:53 PM PDT 24
Peak memory 236644 kb
Host smart-a7320948-a816-47e4-a7ef-6a5ad3de06d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1614936983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1614936983
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3589928643
Short name T350
Test name
Test status
Simulation time 14485778 ps
CPU time 1.76 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 237564 kb
Host smart-caa0c0ba-effd-462f-8ae9-a6445d383d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3589928643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3589928643
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1146478064
Short name T835
Test name
Test status
Simulation time 10977419 ps
CPU time 1.33 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 236496 kb
Host smart-9eebf5d9-1dcb-4261-914e-e4b2a80b600b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1146478064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1146478064
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3305535488
Short name T821
Test name
Test status
Simulation time 15581361 ps
CPU time 1.41 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 235560 kb
Host smart-eb1dff8b-7d6c-48ad-99c1-831c1bcce853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3305535488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3305535488
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2853387319
Short name T816
Test name
Test status
Simulation time 7369621 ps
CPU time 1.47 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:50 PM PDT 24
Peak memory 237508 kb
Host smart-64e8494e-f4a2-44ef-bb67-bbbe35fbf35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2853387319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2853387319
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1312275659
Short name T795
Test name
Test status
Simulation time 6358832 ps
CPU time 1.47 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 05:30:59 PM PDT 24
Peak memory 237564 kb
Host smart-42d61c6f-0660-4899-9010-9e4c403b4d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1312275659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1312275659
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4093868442
Short name T345
Test name
Test status
Simulation time 24278326 ps
CPU time 1.5 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 236680 kb
Host smart-93a7c9b6-86d3-47e7-8e92-4c12bafc43be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093868442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4093868442
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3282979866
Short name T723
Test name
Test status
Simulation time 11381676 ps
CPU time 1.44 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 05:30:59 PM PDT 24
Peak memory 236640 kb
Host smart-20f740a4-e7dd-4152-8b0d-c66519a19b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3282979866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3282979866
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3603639088
Short name T832
Test name
Test status
Simulation time 8990030 ps
CPU time 1.56 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 236664 kb
Host smart-29430ff2-6f01-4593-a065-6204cc1fc5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3603639088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3603639088
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2465669458
Short name T754
Test name
Test status
Simulation time 8481322503 ps
CPU time 300.27 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:35:25 PM PDT 24
Peak memory 241468 kb
Host smart-7600247e-e3e2-4d2f-a1f2-0a337c921ae2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2465669458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2465669458
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1155232736
Short name T352
Test name
Test status
Simulation time 8906880388 ps
CPU time 479.67 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:38:37 PM PDT 24
Peak memory 237664 kb
Host smart-83dbc0f1-2bfc-4748-b58c-0738adcf6f3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1155232736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1155232736
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4166297226
Short name T230
Test name
Test status
Simulation time 226172414 ps
CPU time 4.92 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 248728 kb
Host smart-4d7df844-ed25-483c-80cd-89a38100689b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4166297226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4166297226
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2669582285
Short name T750
Test name
Test status
Simulation time 78132625 ps
CPU time 6.1 seconds
Started Jul 06 05:30:34 PM PDT 24
Finished Jul 06 05:30:41 PM PDT 24
Peak memory 240388 kb
Host smart-b7b95790-c8a3-4b68-9efa-ca2a34484e73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669582285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2669582285
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2677154516
Short name T809
Test name
Test status
Simulation time 128658116 ps
CPU time 9.97 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 240540 kb
Host smart-910e4e0c-23c3-44aa-8456-4b3ceff850d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2677154516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2677154516
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2671299029
Short name T802
Test name
Test status
Simulation time 35937956 ps
CPU time 1.51 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:30:28 PM PDT 24
Peak memory 237608 kb
Host smart-1e0887d4-bc28-415a-8990-e113b176e923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2671299029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2671299029
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4078593965
Short name T787
Test name
Test status
Simulation time 1043967626 ps
CPU time 20.23 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:45 PM PDT 24
Peak memory 240512 kb
Host smart-eb7ba430-bf61-4f4f-be1e-4911ad012be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4078593965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.4078593965
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1276032675
Short name T152
Test name
Test status
Simulation time 4382458673 ps
CPU time 244.74 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:34:46 PM PDT 24
Peak memory 267796 kb
Host smart-98533440-aee0-4c95-8d02-2f291badbe62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1276032675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1276032675
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1837901581
Short name T834
Test name
Test status
Simulation time 45306112 ps
CPU time 5.78 seconds
Started Jul 06 05:30:23 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 248852 kb
Host smart-ded09a00-e8cb-49e0-8014-84367b0685cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1837901581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1837901581
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2131840547
Short name T814
Test name
Test status
Simulation time 7798294 ps
CPU time 1.31 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 237816 kb
Host smart-00dd280b-aaba-4036-ab5e-6ca620fd2cd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2131840547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2131840547
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2520062316
Short name T800
Test name
Test status
Simulation time 10102349 ps
CPU time 1.55 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 237440 kb
Host smart-89b42507-10f4-47f1-9c6d-758068832122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2520062316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2520062316
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1302433193
Short name T725
Test name
Test status
Simulation time 8237515 ps
CPU time 1.49 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 237508 kb
Host smart-728bb348-b41c-4822-8855-ee29d2c3077b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1302433193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1302433193
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3808600430
Short name T347
Test name
Test status
Simulation time 16247579 ps
CPU time 1.36 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 235620 kb
Host smart-b3f1f311-3d45-462d-b1ee-64ce2443fb74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3808600430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3808600430
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.118528327
Short name T764
Test name
Test status
Simulation time 9279417 ps
CPU time 1.59 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 236560 kb
Host smart-a493f527-6c6a-42f4-b6bb-fba3a204b7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=118528327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.118528327
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4280122270
Short name T756
Test name
Test status
Simulation time 12281892 ps
CPU time 1.48 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 236700 kb
Host smart-08f5633c-bdf6-4c31-b2fb-b795b5b7a882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4280122270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4280122270
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2270160234
Short name T717
Test name
Test status
Simulation time 11669553 ps
CPU time 1.38 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 237608 kb
Host smart-d2207239-b2bb-4551-9ffc-9e467c1ecc51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2270160234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2270160234
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3276305612
Short name T806
Test name
Test status
Simulation time 17123982 ps
CPU time 1.91 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:31:00 PM PDT 24
Peak memory 236628 kb
Host smart-bb4b67bd-0557-44da-bc5d-e18ef318dbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3276305612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3276305612
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3817159193
Short name T348
Test name
Test status
Simulation time 16769392 ps
CPU time 1.56 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 237404 kb
Host smart-98362d84-f149-4355-9ce9-248b79491098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3817159193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3817159193
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4209554901
Short name T720
Test name
Test status
Simulation time 12130250 ps
CPU time 1.29 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 237608 kb
Host smart-9bd4cb7f-92a1-4db1-bc38-b4e76bdb30aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209554901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4209554901
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1666384517
Short name T193
Test name
Test status
Simulation time 4413919902 ps
CPU time 165.29 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:33:26 PM PDT 24
Peak memory 240416 kb
Host smart-5a7c04af-9824-49d6-8f82-cdf66edb657f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1666384517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1666384517
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2263937371
Short name T767
Test name
Test status
Simulation time 8795497969 ps
CPU time 523.07 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:39:27 PM PDT 24
Peak memory 240600 kb
Host smart-76fd3940-8cfe-478a-91d1-648c1585c2e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2263937371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2263937371
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.401846363
Short name T793
Test name
Test status
Simulation time 64512605 ps
CPU time 5.38 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 248548 kb
Host smart-f6bf842d-5fec-4eae-ab2c-3e2658cdd45a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=401846363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.401846363
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.103587484
Short name T185
Test name
Test status
Simulation time 404001168 ps
CPU time 7.54 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:32 PM PDT 24
Peak memory 248708 kb
Host smart-43abaf83-a0d7-4b17-8999-81c2a7c5788a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103587484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.103587484
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1479719031
Short name T822
Test name
Test status
Simulation time 65360480 ps
CPU time 3.71 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:30:30 PM PDT 24
Peak memory 237588 kb
Host smart-ee16b408-7dc3-46d5-91cb-6dd03d031678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1479719031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1479719031
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.340238456
Short name T782
Test name
Test status
Simulation time 6333084 ps
CPU time 1.34 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 237624 kb
Host smart-70a88b43-bdce-408b-99e1-3b14c239b1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=340238456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.340238456
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1430095021
Short name T732
Test name
Test status
Simulation time 509396595 ps
CPU time 34.2 seconds
Started Jul 06 05:30:28 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 244856 kb
Host smart-88d6c11e-f8a2-481b-99e2-6080667e3947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1430095021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1430095021
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3132453550
Short name T135
Test name
Test status
Simulation time 18642148065 ps
CPU time 325.72 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:36:10 PM PDT 24
Peak memory 265456 kb
Host smart-37a51f91-aab3-484f-a606-a4da5f4cb2a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3132453550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3132453550
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.546748282
Short name T719
Test name
Test status
Simulation time 249757758 ps
CPU time 3.5 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:30:42 PM PDT 24
Peak memory 248576 kb
Host smart-0659ced2-c4ba-4305-b375-56d596020ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=546748282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.546748282
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3798115356
Short name T819
Test name
Test status
Simulation time 10024036 ps
CPU time 1.24 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 236564 kb
Host smart-8ea5235b-85f6-47ea-8cbb-6b006c8ce7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3798115356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3798115356
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1233905040
Short name T790
Test name
Test status
Simulation time 10461155 ps
CPU time 1.23 seconds
Started Jul 06 05:30:45 PM PDT 24
Finished Jul 06 05:30:47 PM PDT 24
Peak memory 237816 kb
Host smart-10a42a6d-9efc-458e-b982-8d689169fa16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1233905040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1233905040
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.57930357
Short name T778
Test name
Test status
Simulation time 20162040 ps
CPU time 1.4 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 05:31:01 PM PDT 24
Peak memory 237608 kb
Host smart-fd9f929a-f236-4e17-9dd0-5695d0832872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57930357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.57930357
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2963189975
Short name T167
Test name
Test status
Simulation time 10319669 ps
CPU time 1.3 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 236564 kb
Host smart-e1d885ba-84c5-4baa-9df6-acb9964b6801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2963189975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2963189975
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3616527935
Short name T346
Test name
Test status
Simulation time 10655854 ps
CPU time 1.29 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 235664 kb
Host smart-ea4966b3-5172-4d73-af29-390fc99d2d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3616527935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3616527935
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.255242958
Short name T751
Test name
Test status
Simulation time 16940716 ps
CPU time 1.55 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 236560 kb
Host smart-5b04d07b-805d-4c2e-aa0d-dd103e1f1b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=255242958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.255242958
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.580265357
Short name T715
Test name
Test status
Simulation time 10217564 ps
CPU time 1.64 seconds
Started Jul 06 05:30:56 PM PDT 24
Finished Jul 06 05:30:58 PM PDT 24
Peak memory 237568 kb
Host smart-a998bfff-ece4-4302-a094-bf2b37ad9b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580265357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.580265357
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2653024171
Short name T823
Test name
Test status
Simulation time 24896811 ps
CPU time 1.42 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 237608 kb
Host smart-dee9ea01-03e5-48c8-908c-e7082235eae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2653024171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2653024171
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1779880783
Short name T810
Test name
Test status
Simulation time 10540615 ps
CPU time 1.63 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 237608 kb
Host smart-0b4634a3-b206-4cb7-ab54-d1b863b063b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1779880783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1779880783
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4272149140
Short name T730
Test name
Test status
Simulation time 30443282 ps
CPU time 1.43 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:30:50 PM PDT 24
Peak memory 236496 kb
Host smart-24e1adcd-1a1f-4d25-86c9-e7c11f7c25c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272149140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4272149140
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1061110467
Short name T747
Test name
Test status
Simulation time 874861485 ps
CPU time 4.94 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 240596 kb
Host smart-0f194436-ef27-4c73-b3b4-7be6a374de5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061110467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1061110467
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2307479038
Short name T183
Test name
Test status
Simulation time 95642672 ps
CPU time 7.98 seconds
Started Jul 06 05:30:30 PM PDT 24
Finished Jul 06 05:30:39 PM PDT 24
Peak memory 236608 kb
Host smart-1439e98c-b06a-45e5-8495-0434cd172685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2307479038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2307479038
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4226019339
Short name T776
Test name
Test status
Simulation time 21177877 ps
CPU time 1.43 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:30:52 PM PDT 24
Peak memory 237528 kb
Host smart-a83957d0-d2cd-4dda-a232-30a96a1e4d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4226019339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4226019339
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.817515097
Short name T195
Test name
Test status
Simulation time 517708825 ps
CPU time 40.91 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:31:51 PM PDT 24
Peak memory 248756 kb
Host smart-9f0f4798-2fb6-4750-bce0-9243787b5d6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=817515097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.817515097
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.664299238
Short name T128
Test name
Test status
Simulation time 21755509466 ps
CPU time 376.73 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:36:56 PM PDT 24
Peak memory 266516 kb
Host smart-bb628f0b-ed74-4cf8-ab6f-16cc54cdbdf8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=664299238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.664299238
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.717676242
Short name T740
Test name
Test status
Simulation time 261798090 ps
CPU time 16.86 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:59 PM PDT 24
Peak memory 253548 kb
Host smart-5f47eda5-a6b6-4c99-9182-0e5957f706e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=717676242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.717676242
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3361507185
Short name T827
Test name
Test status
Simulation time 103846854 ps
CPU time 4.69 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:47 PM PDT 24
Peak memory 240952 kb
Host smart-a8b0bb26-5ff7-4b46-80fa-04da51a56ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361507185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3361507185
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3819429363
Short name T833
Test name
Test status
Simulation time 150522721 ps
CPU time 7.71 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:30:51 PM PDT 24
Peak memory 240476 kb
Host smart-bd9e4a10-4686-402b-9424-e8b6e975a9fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3819429363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3819429363
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.799596072
Short name T753
Test name
Test status
Simulation time 10739281 ps
CPU time 1.45 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:30:41 PM PDT 24
Peak memory 237572 kb
Host smart-c7b6c819-7845-4f78-9044-b3b28b33517d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=799596072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.799596072
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3943385366
Short name T794
Test name
Test status
Simulation time 249476317 ps
CPU time 21.48 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:31:06 PM PDT 24
Peak memory 248740 kb
Host smart-510e9772-0081-4ef5-8df7-bdb0ce964994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3943385366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3943385366
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.140691435
Short name T156
Test name
Test status
Simulation time 1706871819 ps
CPU time 136.45 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:32:58 PM PDT 24
Peak memory 266392 kb
Host smart-90663e53-5484-48f4-a761-09b1c55e407d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=140691435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.140691435
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3604324517
Short name T839
Test name
Test status
Simulation time 36348999 ps
CPU time 4.47 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 248512 kb
Host smart-47077ef8-269f-4aa0-83fa-8577470b0204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3604324517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3604324517
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3721476585
Short name T789
Test name
Test status
Simulation time 101310970 ps
CPU time 7.3 seconds
Started Jul 06 05:30:35 PM PDT 24
Finished Jul 06 05:30:42 PM PDT 24
Peak memory 240620 kb
Host smart-5883fbde-faf1-4fad-b363-a4565b7d698e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721476585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3721476585
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3525961540
Short name T805
Test name
Test status
Simulation time 180258660 ps
CPU time 4.66 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:42 PM PDT 24
Peak memory 237596 kb
Host smart-effbcac6-7e1f-4560-a665-05cf3071f677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3525961540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3525961540
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2874542313
Short name T745
Test name
Test status
Simulation time 17278222 ps
CPU time 1.31 seconds
Started Jul 06 05:30:55 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 237592 kb
Host smart-f8142443-6893-472a-8c11-82a955caec2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2874542313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2874542313
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.505127731
Short name T722
Test name
Test status
Simulation time 358185376 ps
CPU time 25.25 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:31:04 PM PDT 24
Peak memory 248736 kb
Host smart-ae5a0ffa-d6a0-44a8-bf45-76120ad37f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505127731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.505127731
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3540062886
Short name T737
Test name
Test status
Simulation time 1280976465 ps
CPU time 11.13 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:49 PM PDT 24
Peak memory 254376 kb
Host smart-0244633c-dfe9-426f-a9ee-a3823086de4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3540062886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3540062886
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3050002847
Short name T731
Test name
Test status
Simulation time 1641982247 ps
CPU time 28.83 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:31:14 PM PDT 24
Peak memory 240348 kb
Host smart-510d6e3f-7f17-4783-a5c5-4440723d4a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3050002847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3050002847
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2426751583
Short name T729
Test name
Test status
Simulation time 126544125 ps
CPU time 5.86 seconds
Started Jul 06 05:30:38 PM PDT 24
Finished Jul 06 05:30:45 PM PDT 24
Peak memory 238652 kb
Host smart-eb0cdd51-074e-4da7-ae88-ea7fac9e3748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426751583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2426751583
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.173345820
Short name T781
Test name
Test status
Simulation time 106978210 ps
CPU time 5.67 seconds
Started Jul 06 05:30:58 PM PDT 24
Finished Jul 06 05:31:04 PM PDT 24
Peak memory 237792 kb
Host smart-c4557854-ee6f-47f5-98d5-11362332ccd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=173345820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.173345820
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.4122832467
Short name T746
Test name
Test status
Simulation time 12032016 ps
CPU time 1.61 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 236664 kb
Host smart-274a7893-8c35-441b-9203-23ccbb4a36cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4122832467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.4122832467
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1061234801
Short name T761
Test name
Test status
Simulation time 965610312 ps
CPU time 18.22 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:31:03 PM PDT 24
Peak memory 240540 kb
Host smart-c65670ac-8164-4eda-b509-843adce762e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1061234801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1061234801
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3896650069
Short name T126
Test name
Test status
Simulation time 7807064472 ps
CPU time 594.42 seconds
Started Jul 06 05:30:55 PM PDT 24
Finished Jul 06 05:40:50 PM PDT 24
Peak memory 265448 kb
Host smart-4a84594c-c558-4555-8b99-b267873e3468
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896650069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3896650069
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3655047747
Short name T713
Test name
Test status
Simulation time 174563417 ps
CPU time 5.47 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:48 PM PDT 24
Peak memory 248508 kb
Host smart-9ec7fb6d-7e17-4372-b38c-360da9571133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3655047747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3655047747
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3063169353
Short name T748
Test name
Test status
Simulation time 2725907633 ps
CPU time 47.86 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:31:30 PM PDT 24
Peak memory 248800 kb
Host smart-d107b77e-09e9-4b15-8e6d-db2ee1cb3cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3063169353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3063169353
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2035637035
Short name T738
Test name
Test status
Simulation time 159048723 ps
CPU time 13.02 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 252868 kb
Host smart-30e2fc03-226c-4a94-8873-48e0f921f949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035637035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2035637035
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1372325761
Short name T780
Test name
Test status
Simulation time 66990516 ps
CPU time 3.65 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:30:45 PM PDT 24
Peak memory 240512 kb
Host smart-22aa5dc4-9de5-4bcc-83fd-130d1d0a37b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1372325761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1372325761
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1031825981
Short name T741
Test name
Test status
Simulation time 312341508 ps
CPU time 14.32 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 245804 kb
Host smart-738a3f1d-f45d-432c-9f47-237e8cbab1af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1031825981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1031825981
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3270306232
Short name T812
Test name
Test status
Simulation time 24053480149 ps
CPU time 126.64 seconds
Started Jul 06 05:30:42 PM PDT 24
Finished Jul 06 05:32:51 PM PDT 24
Peak memory 265588 kb
Host smart-ac3ea7b3-2425-4f9d-94f7-854a8fddbccb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3270306232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3270306232
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3751480920
Short name T131
Test name
Test status
Simulation time 18652014944 ps
CPU time 690.95 seconds
Started Jul 06 05:30:40 PM PDT 24
Finished Jul 06 05:42:12 PM PDT 24
Peak memory 265436 kb
Host smart-c1f93ec5-367a-4f37-836f-2f74cf9cfd4e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751480920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3751480920
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1410658537
Short name T830
Test name
Test status
Simulation time 258132036 ps
CPU time 5.84 seconds
Started Jul 06 05:30:59 PM PDT 24
Finished Jul 06 05:31:05 PM PDT 24
Peak memory 254776 kb
Host smart-098df02d-14cb-49a8-9fda-4b5bc79e7458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1410658537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1410658537
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.235081716
Short name T546
Test name
Test status
Simulation time 57323027624 ps
CPU time 1681.22 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:58:52 PM PDT 24
Peak memory 290496 kb
Host smart-47abab3c-3f9a-45e2-8ce0-9125d3f9ac7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235081716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.235081716
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1806944643
Short name T700
Test name
Test status
Simulation time 550434339 ps
CPU time 8.59 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 249172 kb
Host smart-f197f533-ce33-4823-955e-5e48b5a3eadc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1806944643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1806944643
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2391851569
Short name T67
Test name
Test status
Simulation time 4922972935 ps
CPU time 112.31 seconds
Started Jul 06 05:30:46 PM PDT 24
Finished Jul 06 05:32:39 PM PDT 24
Peak memory 256848 kb
Host smart-80faf1fc-ca81-4207-a4b4-1f0f27eebca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
51569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2391851569
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.242709190
Short name T384
Test name
Test status
Simulation time 1930971158 ps
CPU time 23.59 seconds
Started Jul 06 05:30:46 PM PDT 24
Finished Jul 06 05:31:10 PM PDT 24
Peak memory 249584 kb
Host smart-86613d36-1732-4bd2-8211-83149058667c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24270
9190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.242709190
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1661668544
Short name T326
Test name
Test status
Simulation time 56501355219 ps
CPU time 3111.1 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 06:22:40 PM PDT 24
Peak memory 289688 kb
Host smart-6d63d8db-4f61-452c-91e6-4e723ed7f589
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661668544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1661668544
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1389028663
Short name T71
Test name
Test status
Simulation time 35564794760 ps
CPU time 775.6 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 273764 kb
Host smart-a1bb6b99-d335-4cf2-9de0-542153575119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389028663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1389028663
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1375215651
Short name T240
Test name
Test status
Simulation time 1250498053 ps
CPU time 42.83 seconds
Started Jul 06 05:31:01 PM PDT 24
Finished Jul 06 05:31:44 PM PDT 24
Peak memory 256812 kb
Host smart-38eadbb9-dd48-41a6-a493-208de1726cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
15651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1375215651
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.745543050
Short name T542
Test name
Test status
Simulation time 1291202413 ps
CPU time 35.33 seconds
Started Jul 06 05:30:45 PM PDT 24
Finished Jul 06 05:31:21 PM PDT 24
Peak memory 248628 kb
Host smart-4c9a304d-c576-4681-be3e-9df8328083da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74554
3050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.745543050
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3648669219
Short name T616
Test name
Test status
Simulation time 510974765 ps
CPU time 10.7 seconds
Started Jul 06 05:31:09 PM PDT 24
Finished Jul 06 05:31:21 PM PDT 24
Peak memory 249252 kb
Host smart-985ce043-ec91-4599-a1f7-3af74da3b8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36486
69219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3648669219
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1193537634
Short name T401
Test name
Test status
Simulation time 1678491164 ps
CPU time 51.47 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:31:45 PM PDT 24
Peak memory 256848 kb
Host smart-08f2f4fe-236b-4e0b-94db-50bb8989fd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11935
37634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1193537634
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.75205250
Short name T646
Test name
Test status
Simulation time 8029957375 ps
CPU time 1024.06 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:48:11 PM PDT 24
Peak memory 282144 kb
Host smart-c566a2e5-07d7-44d8-8b27-a0c95e8f0743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75205250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.75205250
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.344457833
Short name T440
Test name
Test status
Simulation time 423371046 ps
CPU time 20.48 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:31:13 PM PDT 24
Peak memory 249184 kb
Host smart-a639b1a3-af5f-4201-bd42-ba3c21ee1c72
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=344457833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.344457833
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1711345156
Short name T685
Test name
Test status
Simulation time 67820965267 ps
CPU time 280.51 seconds
Started Jul 06 05:30:46 PM PDT 24
Finished Jul 06 05:35:26 PM PDT 24
Peak memory 257556 kb
Host smart-cf1e5d91-8a65-4d0e-90d1-5ff5f64ba9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17113
45156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1711345156
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1474003639
Short name T691
Test name
Test status
Simulation time 54931059 ps
CPU time 2.54 seconds
Started Jul 06 05:31:03 PM PDT 24
Finished Jul 06 05:31:06 PM PDT 24
Peak memory 240344 kb
Host smart-ccb4dce9-59fc-4fc5-a722-826ac867e0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
03639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1474003639
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.672604581
Short name T334
Test name
Test status
Simulation time 40170675459 ps
CPU time 1021.54 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 05:47:59 PM PDT 24
Peak memory 273816 kb
Host smart-bfd33714-e720-43c8-ab78-e2ddbfac4226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672604581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.672604581
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4209744908
Short name T261
Test name
Test status
Simulation time 49529539844 ps
CPU time 2680.24 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 06:15:28 PM PDT 24
Peak memory 289384 kb
Host smart-7aad80da-ae7f-41d0-b216-024a4dd8a8eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209744908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4209744908
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1611124684
Short name T354
Test name
Test status
Simulation time 1178659540 ps
CPU time 18.75 seconds
Started Jul 06 05:30:55 PM PDT 24
Finished Jul 06 05:31:14 PM PDT 24
Peak memory 255904 kb
Host smart-1341b1c4-f993-4e7a-8a76-451aca9f6916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16111
24684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1611124684
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3785968266
Short name T364
Test name
Test status
Simulation time 212783563 ps
CPU time 7.62 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 254356 kb
Host smart-a38850c3-6728-4271-916c-3bfd4714d207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37859
68266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3785968266
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4040436889
Short name T11
Test name
Test status
Simulation time 1613796393 ps
CPU time 24.73 seconds
Started Jul 06 05:30:59 PM PDT 24
Finished Jul 06 05:31:24 PM PDT 24
Peak memory 271480 kb
Host smart-8c0a551c-3602-417b-abeb-1b92ae14e80f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4040436889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4040436889
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3133677775
Short name T430
Test name
Test status
Simulation time 753784226 ps
CPU time 16.07 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 05:31:32 PM PDT 24
Peak memory 248832 kb
Host smart-3d5a782d-fc02-4c88-991b-2860eadf0249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31336
77775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3133677775
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3740123324
Short name T652
Test name
Test status
Simulation time 1602642479 ps
CPU time 25.24 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:31:19 PM PDT 24
Peak memory 256784 kb
Host smart-af5ff66e-9089-4813-9a43-a481fd1eb1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37401
23324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3740123324
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3529606625
Short name T670
Test name
Test status
Simulation time 73051316831 ps
CPU time 2321.64 seconds
Started Jul 06 05:31:21 PM PDT 24
Finished Jul 06 06:10:04 PM PDT 24
Peak memory 290352 kb
Host smart-794b12e3-a859-4ce3-b0f6-c6abadc6b4bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529606625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3529606625
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1749403939
Short name T651
Test name
Test status
Simulation time 660891770 ps
CPU time 27.86 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:31:58 PM PDT 24
Peak memory 249260 kb
Host smart-dfde122c-b011-4b3c-908d-4277c032de27
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1749403939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1749403939
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2145744970
Short name T511
Test name
Test status
Simulation time 1063679552 ps
CPU time 94.85 seconds
Started Jul 06 05:31:14 PM PDT 24
Finished Jul 06 05:32:49 PM PDT 24
Peak memory 256972 kb
Host smart-a44fcf38-2e3f-4bd7-a834-cd8eed63362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
44970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2145744970
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1420773336
Short name T555
Test name
Test status
Simulation time 650158157 ps
CPU time 45.28 seconds
Started Jul 06 05:31:22 PM PDT 24
Finished Jul 06 05:32:08 PM PDT 24
Peak memory 249292 kb
Host smart-9caa9a09-6833-47e6-99ed-77ace2aeddc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14207
73336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1420773336
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4141451820
Short name T585
Test name
Test status
Simulation time 316957991927 ps
CPU time 1438.72 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 05:55:18 PM PDT 24
Peak memory 273432 kb
Host smart-827c8978-832a-4978-bc5b-338d93bc41b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141451820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4141451820
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2726855487
Short name T481
Test name
Test status
Simulation time 25947857989 ps
CPU time 532.83 seconds
Started Jul 06 05:31:21 PM PDT 24
Finished Jul 06 05:40:15 PM PDT 24
Peak memory 249388 kb
Host smart-762b53ff-95c8-4b56-8761-974617b432a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726855487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2726855487
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2695329129
Short name T536
Test name
Test status
Simulation time 1696464692 ps
CPU time 23.57 seconds
Started Jul 06 05:31:09 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 256796 kb
Host smart-c121fa99-5303-490a-9c4c-cb4418dbc4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26953
29129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2695329129
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.38591443
Short name T474
Test name
Test status
Simulation time 312740384 ps
CPU time 10.22 seconds
Started Jul 06 05:31:27 PM PDT 24
Finished Jul 06 05:31:37 PM PDT 24
Peak memory 256908 kb
Host smart-7c626b9f-b003-4321-853a-8a495bfe2fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38591
443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.38591443
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.607759080
Short name T396
Test name
Test status
Simulation time 2375318836 ps
CPU time 44.05 seconds
Started Jul 06 05:31:08 PM PDT 24
Finished Jul 06 05:31:52 PM PDT 24
Peak memory 257168 kb
Host smart-4ce9245e-d9ee-453d-88ee-c589b48b8b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60775
9080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.607759080
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1822227745
Short name T356
Test name
Test status
Simulation time 1589464873 ps
CPU time 25.17 seconds
Started Jul 06 05:31:17 PM PDT 24
Finished Jul 06 05:31:42 PM PDT 24
Peak memory 257260 kb
Host smart-902198ac-e772-4e6b-b68f-7f44ec088f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18222
27745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1822227745
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1216014537
Short name T484
Test name
Test status
Simulation time 1190150213 ps
CPU time 44.08 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:32:08 PM PDT 24
Peak memory 257472 kb
Host smart-8bf7f414-39c9-47c1-9ec8-8439fe30b3e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216014537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1216014537
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3605662884
Short name T677
Test name
Test status
Simulation time 607920208502 ps
CPU time 4892.14 seconds
Started Jul 06 05:31:18 PM PDT 24
Finished Jul 06 06:52:51 PM PDT 24
Peak memory 306828 kb
Host smart-d66f459e-f8d4-4179-903f-d1907b19d69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605662884 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3605662884
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.937086022
Short name T214
Test name
Test status
Simulation time 76906967 ps
CPU time 3.64 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 05:31:37 PM PDT 24
Peak memory 249620 kb
Host smart-26cab00a-885c-4ec4-89db-487249978e4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=937086022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.937086022
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.455409389
Short name T105
Test name
Test status
Simulation time 10621311897 ps
CPU time 1002.73 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:48:03 PM PDT 24
Peak memory 285064 kb
Host smart-c092f2a2-5a26-4b94-8c85-5f3a333cea47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455409389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.455409389
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.575403578
Short name T523
Test name
Test status
Simulation time 235032389 ps
CPU time 8.05 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 05:31:42 PM PDT 24
Peak memory 249192 kb
Host smart-4f2598ce-1e1a-4a21-ad5d-941d27ee13ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=575403578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.575403578
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1292763473
Short name T492
Test name
Test status
Simulation time 2988276996 ps
CPU time 171.66 seconds
Started Jul 06 05:31:27 PM PDT 24
Finished Jul 06 05:34:19 PM PDT 24
Peak memory 257060 kb
Host smart-a39cfba6-5e14-4137-9a92-339bce265597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
63473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1292763473
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1182863063
Short name T381
Test name
Test status
Simulation time 1114042420 ps
CPU time 12.52 seconds
Started Jul 06 05:31:13 PM PDT 24
Finished Jul 06 05:31:26 PM PDT 24
Peak memory 249232 kb
Host smart-00d680a8-a79e-425e-89e3-4a9a2d29f107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828
63063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1182863063
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2529419209
Short name T344
Test name
Test status
Simulation time 74603751749 ps
CPU time 2066.74 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 06:05:46 PM PDT 24
Peak memory 273664 kb
Host smart-06b13334-b352-4717-acad-ce006125fef4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529419209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2529419209
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.155247285
Short name T529
Test name
Test status
Simulation time 50586161622 ps
CPU time 1553.2 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:57:18 PM PDT 24
Peak memory 273928 kb
Host smart-10e7f404-378d-4b33-8cbd-2518de8a791f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155247285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.155247285
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2480874745
Short name T315
Test name
Test status
Simulation time 10044807261 ps
CPU time 407.64 seconds
Started Jul 06 05:31:15 PM PDT 24
Finished Jul 06 05:38:04 PM PDT 24
Peak memory 249400 kb
Host smart-24eaa7f9-eb38-4446-82f0-4944daa9d2e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480874745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2480874745
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.854992169
Short name T388
Test name
Test status
Simulation time 406723348 ps
CPU time 44.79 seconds
Started Jul 06 05:31:26 PM PDT 24
Finished Jul 06 05:32:11 PM PDT 24
Peak memory 257372 kb
Host smart-e0cb4d4f-0f9e-4b8a-bd0d-5126683b55e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85499
2169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.854992169
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2495771813
Short name T667
Test name
Test status
Simulation time 1315341611 ps
CPU time 17.66 seconds
Started Jul 06 05:31:18 PM PDT 24
Finished Jul 06 05:31:36 PM PDT 24
Peak memory 249220 kb
Host smart-debb9e9f-2920-4573-a0fd-32194307749d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24957
71813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2495771813
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.4185406943
Short name T95
Test name
Test status
Simulation time 239780327 ps
CPU time 30.01 seconds
Started Jul 06 05:31:21 PM PDT 24
Finished Jul 06 05:31:51 PM PDT 24
Peak memory 248840 kb
Host smart-3b6d79f8-0534-4513-8824-b150a3616dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41854
06943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4185406943
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1989718269
Short name T697
Test name
Test status
Simulation time 933954416 ps
CPU time 51.93 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:32:02 PM PDT 24
Peak memory 257360 kb
Host smart-f243bafe-52f7-4891-b299-868d0b1c5de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
18269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1989718269
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1632492345
Short name T437
Test name
Test status
Simulation time 7140082872 ps
CPU time 172.3 seconds
Started Jul 06 05:31:14 PM PDT 24
Finished Jul 06 05:34:07 PM PDT 24
Peak memory 257468 kb
Host smart-3b56b14c-d4c4-420e-9911-8b5f476a860b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632492345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1632492345
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2337274457
Short name T254
Test name
Test status
Simulation time 215293538443 ps
CPU time 2676.68 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 06:16:13 PM PDT 24
Peak memory 306232 kb
Host smart-9dcfca89-bee7-4f74-aaa9-2c73db8c334d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337274457 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2337274457
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1578194820
Short name T203
Test name
Test status
Simulation time 66810899 ps
CPU time 2.59 seconds
Started Jul 06 05:31:21 PM PDT 24
Finished Jul 06 05:31:24 PM PDT 24
Peak memory 249580 kb
Host smart-c844733e-7e24-4740-af97-5412e76a9282
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1578194820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1578194820
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.808109032
Short name T567
Test name
Test status
Simulation time 32147055409 ps
CPU time 1803.74 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 06:01:42 PM PDT 24
Peak memory 290172 kb
Host smart-b9f41b8e-fd1c-42b9-9624-27e92103695c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808109032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.808109032
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.308183917
Short name T455
Test name
Test status
Simulation time 474893972 ps
CPU time 8.47 seconds
Started Jul 06 05:31:25 PM PDT 24
Finished Jul 06 05:31:34 PM PDT 24
Peak memory 249268 kb
Host smart-914e2fc3-6b81-4b8c-a775-397489fd18b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=308183917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.308183917
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2373790059
Short name T429
Test name
Test status
Simulation time 1237705985 ps
CPU time 103.34 seconds
Started Jul 06 05:31:14 PM PDT 24
Finished Jul 06 05:32:58 PM PDT 24
Peak memory 257012 kb
Host smart-398a4c8c-7ba4-4f1f-bbac-b53414735e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23737
90059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2373790059
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2724516088
Short name T575
Test name
Test status
Simulation time 704674479 ps
CPU time 26.07 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:31:56 PM PDT 24
Peak memory 249300 kb
Host smart-150c225a-6c38-4c22-9f38-2078483359a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
16088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2724516088
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1690397463
Short name T506
Test name
Test status
Simulation time 31071885213 ps
CPU time 1256.23 seconds
Started Jul 06 05:31:26 PM PDT 24
Finished Jul 06 05:52:23 PM PDT 24
Peak memory 289496 kb
Host smart-644f3ad2-3522-4f15-b6c4-0f7bbbdc20b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690397463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1690397463
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2890610929
Short name T525
Test name
Test status
Simulation time 13698428099 ps
CPU time 544.82 seconds
Started Jul 06 05:31:15 PM PDT 24
Finished Jul 06 05:40:20 PM PDT 24
Peak memory 249360 kb
Host smart-56f55aca-abe1-402c-a775-892985536ac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890610929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2890610929
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3616120844
Short name T621
Test name
Test status
Simulation time 827636259 ps
CPU time 24.82 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:31:45 PM PDT 24
Peak memory 257348 kb
Host smart-77fe62b1-40d1-4231-871e-91e349655d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161
20844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3616120844
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3000824474
Short name T368
Test name
Test status
Simulation time 619128523 ps
CPU time 37.22 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 05:32:09 PM PDT 24
Peak memory 248556 kb
Host smart-3e05642c-2d4a-4a4e-b3a8-ca4d26bad8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
24474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3000824474
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3159200577
Short name T260
Test name
Test status
Simulation time 1578015592 ps
CPU time 23.25 seconds
Started Jul 06 05:31:18 PM PDT 24
Finished Jul 06 05:31:41 PM PDT 24
Peak memory 249288 kb
Host smart-6326da68-d6ef-4dce-a695-139bf7fc8aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31592
00577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3159200577
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3382216746
Short name T234
Test name
Test status
Simulation time 115104333810 ps
CPU time 3648.05 seconds
Started Jul 06 05:31:25 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 298300 kb
Host smart-faff3710-cf87-40ca-968c-e88ee2c64dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382216746 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3382216746
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3353910687
Short name T58
Test name
Test status
Simulation time 18675240842 ps
CPU time 1151.5 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:50:36 PM PDT 24
Peak memory 273544 kb
Host smart-a7e48ad9-c4d3-45c1-9eee-f85a9f5c8cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353910687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3353910687
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1873680417
Short name T416
Test name
Test status
Simulation time 629487204 ps
CPU time 28.14 seconds
Started Jul 06 05:31:29 PM PDT 24
Finished Jul 06 05:31:57 PM PDT 24
Peak memory 249240 kb
Host smart-a8611dd2-8523-4d47-a43b-ced27ea733ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1873680417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1873680417
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.182682302
Short name T295
Test name
Test status
Simulation time 5212478611 ps
CPU time 117.61 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:33:22 PM PDT 24
Peak memory 257112 kb
Host smart-f24de046-753f-4445-8b2d-3a72a4df6c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18268
2302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.182682302
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1528474321
Short name T583
Test name
Test status
Simulation time 1670173430 ps
CPU time 29 seconds
Started Jul 06 05:31:25 PM PDT 24
Finished Jul 06 05:31:55 PM PDT 24
Peak memory 257488 kb
Host smart-b36cf66d-cb88-441b-88e4-cb1d4e97ffad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15284
74321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1528474321
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2775172809
Short name T341
Test name
Test status
Simulation time 40925930295 ps
CPU time 2195.29 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 06:07:56 PM PDT 24
Peak memory 271944 kb
Host smart-5df4575f-f0c8-4f30-9136-1da8495fd3d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775172809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2775172809
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2277099437
Short name T633
Test name
Test status
Simulation time 38960631501 ps
CPU time 957.38 seconds
Started Jul 06 05:31:28 PM PDT 24
Finished Jul 06 05:47:26 PM PDT 24
Peak memory 289372 kb
Host smart-687540aa-5c0b-448c-9b87-61aa93312a99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277099437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2277099437
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2845730898
Short name T432
Test name
Test status
Simulation time 161749619 ps
CPU time 20.07 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:31:55 PM PDT 24
Peak memory 248680 kb
Host smart-062f04db-20f7-48c3-9211-9850762d880f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457
30898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2845730898
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4275566132
Short name T371
Test name
Test status
Simulation time 118833244 ps
CPU time 5.54 seconds
Started Jul 06 05:31:27 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 251360 kb
Host smart-2b4f530e-3666-4cfc-a955-981f085a36c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755
66132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4275566132
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1082893115
Short name T618
Test name
Test status
Simulation time 1135811985 ps
CPU time 92.87 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:32:58 PM PDT 24
Peak memory 257348 kb
Host smart-6904c48c-2e14-4211-a4aa-d010aabbdd44
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082893115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1082893115
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2306662577
Short name T209
Test name
Test status
Simulation time 43365819 ps
CPU time 3.41 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:31:28 PM PDT 24
Peak memory 249540 kb
Host smart-dc431c46-080b-4a21-b625-fa96c7bc2eb5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2306662577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2306662577
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.863777543
Short name T36
Test name
Test status
Simulation time 149786175558 ps
CPU time 2324.1 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 06:10:16 PM PDT 24
Peak memory 290156 kb
Host smart-7bbbd5d6-da02-44c6-b8e6-52f8bdbd7303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863777543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.863777543
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.975967868
Short name T359
Test name
Test status
Simulation time 372813190 ps
CPU time 7.43 seconds
Started Jul 06 05:31:28 PM PDT 24
Finished Jul 06 05:31:36 PM PDT 24
Peak memory 249184 kb
Host smart-d807696e-512f-4aaf-8079-dd28033e7100
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=975967868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.975967868
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.579325416
Short name T537
Test name
Test status
Simulation time 4595420086 ps
CPU time 243.64 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:35:38 PM PDT 24
Peak memory 257588 kb
Host smart-fa49060f-458d-412d-af69-090d6197ab67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57932
5416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.579325416
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3649470114
Short name T539
Test name
Test status
Simulation time 217774531 ps
CPU time 7.8 seconds
Started Jul 06 05:31:22 PM PDT 24
Finished Jul 06 05:31:30 PM PDT 24
Peak memory 252040 kb
Host smart-7f61c5c5-7ea4-4e0c-bb40-7216954a251b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36494
70114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3649470114
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1783881995
Short name T342
Test name
Test status
Simulation time 60642632070 ps
CPU time 1538.93 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:57:15 PM PDT 24
Peak memory 289412 kb
Host smart-19a1e680-4f02-4473-a730-39e76cf36367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783881995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1783881995
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1292005456
Short name T298
Test name
Test status
Simulation time 64592932249 ps
CPU time 570.15 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 05:41:04 PM PDT 24
Peak memory 257540 kb
Host smart-c1f38b36-b7e7-426d-a9e5-3f117b301878
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292005456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1292005456
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2817179875
Short name T399
Test name
Test status
Simulation time 20722598 ps
CPU time 3.27 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 241008 kb
Host smart-69193954-8d07-4304-88df-177fbae27fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
79875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2817179875
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.392088528
Short name T108
Test name
Test status
Simulation time 1123717631 ps
CPU time 60.82 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:32:21 PM PDT 24
Peak memory 256324 kb
Host smart-bde61e69-811c-416f-b39e-2b26fce2489a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
8528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.392088528
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1385957854
Short name T479
Test name
Test status
Simulation time 246068620 ps
CPU time 30.03 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:32:01 PM PDT 24
Peak memory 248772 kb
Host smart-a54efe6b-014d-4f38-ac64-1f78ccfd7d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859
57854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1385957854
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2056103628
Short name T476
Test name
Test status
Simulation time 1812681532 ps
CPU time 19.23 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:31:40 PM PDT 24
Peak memory 256388 kb
Host smart-00416bc3-e960-4819-9f7e-72847eeaa7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561
03628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2056103628
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1874570414
Short name T52
Test name
Test status
Simulation time 9768050391 ps
CPU time 554.82 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 05:40:47 PM PDT 24
Peak memory 257644 kb
Host smart-5a2f990b-2658-439b-9d96-22041a5c3a71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874570414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1874570414
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.839977720
Short name T187
Test name
Test status
Simulation time 116138952748 ps
CPU time 861.31 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:45:46 PM PDT 24
Peak memory 283876 kb
Host smart-50bc9059-4711-4017-b9c2-97733da8a4d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839977720 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.839977720
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2521710940
Short name T207
Test name
Test status
Simulation time 35255891 ps
CPU time 3.52 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 05:31:35 PM PDT 24
Peak memory 249516 kb
Host smart-ae7392de-b995-4505-a188-497e347720cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2521710940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2521710940
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1207721755
Short name T545
Test name
Test status
Simulation time 36512181559 ps
CPU time 2057.73 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 06:05:50 PM PDT 24
Peak memory 273900 kb
Host smart-ce6c1a20-0aa3-47ca-bd10-0be3d2495a91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207721755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1207721755
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1625587026
Short name T521
Test name
Test status
Simulation time 380342399 ps
CPU time 18 seconds
Started Jul 06 05:31:21 PM PDT 24
Finished Jul 06 05:31:39 PM PDT 24
Peak memory 249272 kb
Host smart-2061c3d7-5581-45c2-bb69-f50b6ec245b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1625587026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1625587026
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1853991820
Short name T392
Test name
Test status
Simulation time 3539832795 ps
CPU time 143.83 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:34:07 PM PDT 24
Peak memory 257056 kb
Host smart-341e8446-4954-47ad-a31a-24dc7ec10138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18539
91820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1853991820
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1435508611
Short name T245
Test name
Test status
Simulation time 319913562 ps
CPU time 30.41 seconds
Started Jul 06 05:31:28 PM PDT 24
Finished Jul 06 05:31:59 PM PDT 24
Peak memory 248820 kb
Host smart-be54e771-a54b-4599-9187-3b7fa0aa8be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14355
08611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1435508611
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2154703268
Short name T324
Test name
Test status
Simulation time 13100776339 ps
CPU time 1084.58 seconds
Started Jul 06 05:31:27 PM PDT 24
Finished Jul 06 05:49:32 PM PDT 24
Peak memory 285368 kb
Host smart-bcce98e8-86e2-4b1b-8201-98b6fc7e81b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154703268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2154703268
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4012457291
Short name T563
Test name
Test status
Simulation time 105795683258 ps
CPU time 1784.75 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 06:01:18 PM PDT 24
Peak memory 288932 kb
Host smart-0725bedd-1edb-40d6-94b0-aa675eb707f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012457291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4012457291
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.911853887
Short name T306
Test name
Test status
Simulation time 54561726565 ps
CPU time 566.76 seconds
Started Jul 06 05:31:23 PM PDT 24
Finished Jul 06 05:40:50 PM PDT 24
Peak memory 249364 kb
Host smart-0cff60a2-cf60-4b15-95a3-b182dc4df9cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911853887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.911853887
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1091829713
Short name T423
Test name
Test status
Simulation time 599183848 ps
CPU time 41.1 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:32:18 PM PDT 24
Peak memory 256784 kb
Host smart-3b6710bf-b170-429a-9d1f-866dac308458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918
29713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1091829713
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2011567189
Short name T602
Test name
Test status
Simulation time 2459416236 ps
CPU time 34.94 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:13 PM PDT 24
Peak memory 257472 kb
Host smart-7e9f4f01-5bfe-41db-8f0a-f5a323e35293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20115
67189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2011567189
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.867851488
Short name T487
Test name
Test status
Simulation time 859335967 ps
CPU time 30.71 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 257456 kb
Host smart-c786f26d-2f4c-43ad-8b5e-09832c157179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86785
1488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.867851488
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1521865310
Short name T217
Test name
Test status
Simulation time 28944635 ps
CPU time 2.72 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:31:41 PM PDT 24
Peak memory 249536 kb
Host smart-cc366a37-64fc-4108-a4c4-8f647762448e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1521865310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1521865310
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1760318175
Short name T43
Test name
Test status
Simulation time 67042182763 ps
CPU time 2240.73 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 06:08:53 PM PDT 24
Peak memory 288384 kb
Host smart-6e62e6de-a57a-4ad3-8772-657d33c51aa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760318175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1760318175
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1555523097
Short name T14
Test name
Test status
Simulation time 984897558 ps
CPU time 15.47 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:31:51 PM PDT 24
Peak memory 249280 kb
Host smart-5afb91f3-034a-4e1c-b2a9-f9e5574457e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1555523097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1555523097
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.415455963
Short name T496
Test name
Test status
Simulation time 2864669963 ps
CPU time 73.13 seconds
Started Jul 06 05:31:26 PM PDT 24
Finished Jul 06 05:32:39 PM PDT 24
Peak memory 257024 kb
Host smart-4a6e8b1d-512b-4172-a4f0-8036d07ccd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41545
5963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.415455963
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1166012973
Short name T559
Test name
Test status
Simulation time 2067821671 ps
CPU time 33.84 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:32:05 PM PDT 24
Peak memory 249212 kb
Host smart-7ed94cad-d502-45ea-9587-248194f5567a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
12973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1166012973
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2115951312
Short name T198
Test name
Test status
Simulation time 46326769526 ps
CPU time 1330.29 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:53:50 PM PDT 24
Peak memory 273896 kb
Host smart-d5b25ce0-461b-4608-a92e-5f38f70089c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115951312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2115951312
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1241360394
Short name T30
Test name
Test status
Simulation time 31380759686 ps
CPU time 1311.76 seconds
Started Jul 06 05:31:29 PM PDT 24
Finished Jul 06 05:53:22 PM PDT 24
Peak memory 265816 kb
Host smart-c21228b2-a4aa-4bf5-aa26-5c2dd6ffb70f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241360394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1241360394
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1052609024
Short name T73
Test name
Test status
Simulation time 16414701369 ps
CPU time 183.11 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:34:41 PM PDT 24
Peak memory 249352 kb
Host smart-4f33eb6c-de44-4089-bba8-5c9cc63c5ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052609024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1052609024
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3739110674
Short name T501
Test name
Test status
Simulation time 501366034 ps
CPU time 23.67 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:01 PM PDT 24
Peak memory 249284 kb
Host smart-8713ad5b-7bdb-41eb-a728-1dcdca9e5f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37391
10674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3739110674
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4050789439
Short name T223
Test name
Test status
Simulation time 913318545 ps
CPU time 25.02 seconds
Started Jul 06 05:31:25 PM PDT 24
Finished Jul 06 05:31:51 PM PDT 24
Peak memory 249272 kb
Host smart-36837eb2-8bda-4a74-83c7-bce1fd1b7091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40507
89439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4050789439
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1600682870
Short name T579
Test name
Test status
Simulation time 1383757618 ps
CPU time 18.14 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:31:55 PM PDT 24
Peak memory 248532 kb
Host smart-04b06a1d-1571-4910-bd40-50ef38cd16e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16006
82870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1600682870
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3317904048
Short name T373
Test name
Test status
Simulation time 859381461 ps
CPU time 15.42 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 05:31:49 PM PDT 24
Peak memory 255412 kb
Host smart-62adee18-9ff4-4b25-b337-554b53ee8241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33179
04048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3317904048
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.95008001
Short name T561
Test name
Test status
Simulation time 10854299767 ps
CPU time 195.52 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:34:51 PM PDT 24
Peak memory 257628 kb
Host smart-1cf357e6-a7c9-4311-9021-f0ba98e0bec0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95008001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_hand
ler_stress_all.95008001
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2274932755
Short name T199
Test name
Test status
Simulation time 153495196738 ps
CPU time 3580.76 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 06:31:13 PM PDT 24
Peak memory 355012 kb
Host smart-e6fe116c-eaea-4601-9674-7a346dbf227a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274932755 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2274932755
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3334191069
Short name T200
Test name
Test status
Simulation time 67850423 ps
CPU time 3.86 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:31:40 PM PDT 24
Peak memory 249572 kb
Host smart-e83b8734-9b32-42a3-9805-33f6453e2690
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3334191069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3334191069
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.944352764
Short name T497
Test name
Test status
Simulation time 30840235171 ps
CPU time 752.4 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:44:12 PM PDT 24
Peak memory 268832 kb
Host smart-94408deb-fe25-4ad9-936a-925ca85920bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944352764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.944352764
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.84264317
Short name T571
Test name
Test status
Simulation time 943597704 ps
CPU time 11.01 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:31:54 PM PDT 24
Peak memory 249244 kb
Host smart-8da7908a-93ab-44b4-bd89-8ddf24cd38bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=84264317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.84264317
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4004394968
Short name T503
Test name
Test status
Simulation time 4963809111 ps
CPU time 81.3 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:32:58 PM PDT 24
Peak memory 257012 kb
Host smart-c9440551-8259-4006-9e07-900d30d7695b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
94968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4004394968
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1523101014
Short name T549
Test name
Test status
Simulation time 4691881164 ps
CPU time 44.34 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:22 PM PDT 24
Peak memory 249388 kb
Host smart-074f26a9-0e93-4e9d-b82f-e5c0935fde09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15231
01014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1523101014
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1928445210
Short name T435
Test name
Test status
Simulation time 30350507843 ps
CPU time 1335.59 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 05:53:48 PM PDT 24
Peak memory 273212 kb
Host smart-8335e8b5-48a7-41e7-a229-4bfb521219f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928445210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1928445210
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3966023860
Short name T442
Test name
Test status
Simulation time 38292595 ps
CPU time 3.08 seconds
Started Jul 06 05:31:41 PM PDT 24
Finished Jul 06 05:31:44 PM PDT 24
Peak memory 249240 kb
Host smart-b59e41e7-badd-4927-9c55-ced8da946c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39660
23860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3966023860
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1151738018
Short name T404
Test name
Test status
Simulation time 82430407 ps
CPU time 3.14 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 05:31:34 PM PDT 24
Peak memory 240604 kb
Host smart-4d9b9180-07c2-4ba3-b023-23594c1cff64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11517
38018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1151738018
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.967329481
Short name T706
Test name
Test status
Simulation time 159751897 ps
CPU time 10.93 seconds
Started Jul 06 05:31:37 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 249236 kb
Host smart-972398b0-e48a-4de0-bb06-78157449105e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96732
9481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.967329481
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3727132779
Short name T466
Test name
Test status
Simulation time 829240055 ps
CPU time 22.56 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:31:58 PM PDT 24
Peak memory 256944 kb
Host smart-207b4738-3762-4ce8-85ca-50ab1fe9319e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37271
32779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3727132779
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3570991016
Short name T57
Test name
Test status
Simulation time 23494977241 ps
CPU time 2026.65 seconds
Started Jul 06 05:31:28 PM PDT 24
Finished Jul 06 06:05:16 PM PDT 24
Peak memory 298368 kb
Host smart-6a8d691f-8ae1-445d-8917-5369f658bde5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570991016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3570991016
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3687731369
Short name T89
Test name
Test status
Simulation time 31883584831 ps
CPU time 1998.17 seconds
Started Jul 06 05:31:41 PM PDT 24
Finished Jul 06 06:05:00 PM PDT 24
Peak memory 286988 kb
Host smart-71b85742-7ca1-49d0-99a3-b0b14c129dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687731369 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3687731369
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.565965745
Short name T201
Test name
Test status
Simulation time 103001669 ps
CPU time 3.44 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 05:31:36 PM PDT 24
Peak memory 249456 kb
Host smart-055b4297-fe60-4fe2-894b-202001fb6617
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=565965745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.565965745
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.634685210
Short name T514
Test name
Test status
Simulation time 18075953834 ps
CPU time 949.57 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 05:47:21 PM PDT 24
Peak memory 273596 kb
Host smart-034f5b4a-7c07-4dab-b9b5-bcce61cb36da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634685210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.634685210
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1561150386
Short name T372
Test name
Test status
Simulation time 684182438 ps
CPU time 10.97 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 249180 kb
Host smart-bb5350c9-98f6-4aa1-af26-f7a9084e881a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1561150386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1561150386
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2288555936
Short name T374
Test name
Test status
Simulation time 1346065861 ps
CPU time 90.54 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:33:08 PM PDT 24
Peak memory 256964 kb
Host smart-66e27668-f94d-4b17-bcb0-94188cf0e9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22885
55936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2288555936
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1425234579
Short name T410
Test name
Test status
Simulation time 5323131644 ps
CPU time 40.44 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:18 PM PDT 24
Peak memory 257244 kb
Host smart-5ce014f2-bebc-4b32-9697-4079f3ceecdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14252
34579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1425234579
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2751274103
Short name T408
Test name
Test status
Simulation time 147491735037 ps
CPU time 2030.14 seconds
Started Jul 06 05:31:31 PM PDT 24
Finished Jul 06 06:05:22 PM PDT 24
Peak memory 286368 kb
Host smart-3ed33fb7-3ee0-4a5f-a19c-1804a977da53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751274103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2751274103
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1925353474
Short name T613
Test name
Test status
Simulation time 11217863353 ps
CPU time 469.8 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:39:29 PM PDT 24
Peak memory 248220 kb
Host smart-3389467d-795b-4346-8b60-c3aade60df43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925353474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1925353474
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2730511041
Short name T620
Test name
Test status
Simulation time 2498881297 ps
CPU time 38.43 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:32:22 PM PDT 24
Peak memory 256932 kb
Host smart-f7fef7a7-aa80-4944-97a1-5b0e2ae6dd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
11041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2730511041
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.460190796
Short name T485
Test name
Test status
Simulation time 2163811399 ps
CPU time 32.75 seconds
Started Jul 06 05:31:29 PM PDT 24
Finished Jul 06 05:32:02 PM PDT 24
Peak memory 256464 kb
Host smart-c97c1840-b24d-49c2-b35b-fd675b3ce11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46019
0796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.460190796
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1123468381
Short name T453
Test name
Test status
Simulation time 783487184 ps
CPU time 55.61 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:33 PM PDT 24
Peak memory 256864 kb
Host smart-ddb1fb55-bb6a-425f-95b2-b21a742d80b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11234
68381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1123468381
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2474589549
Short name T570
Test name
Test status
Simulation time 1583825800 ps
CPU time 37.73 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:32:17 PM PDT 24
Peak memory 249256 kb
Host smart-aade27dc-6cee-45cf-8175-27d03165b681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
89549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2474589549
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2020374901
Short name T252
Test name
Test status
Simulation time 46262043884 ps
CPU time 2605.33 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 06:15:05 PM PDT 24
Peak memory 289396 kb
Host smart-12a008d3-cee9-405e-9da0-b1d5e0aaf993
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020374901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2020374901
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2330601103
Short name T215
Test name
Test status
Simulation time 19153323 ps
CPU time 2.83 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 05:31:45 PM PDT 24
Peak memory 249516 kb
Host smart-e85dfb4a-fd7d-47f1-ac5e-285a5bebecf4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2330601103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2330601103
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.733856740
Short name T515
Test name
Test status
Simulation time 88221109610 ps
CPU time 1212.05 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:51:49 PM PDT 24
Peak memory 273580 kb
Host smart-76211fe9-47c9-44e5-b203-44d531f3c159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733856740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.733856740
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1524658313
Short name T70
Test name
Test status
Simulation time 628497921 ps
CPU time 30.01 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:08 PM PDT 24
Peak memory 249264 kb
Host smart-dfad8259-e40c-43e6-be79-50e8922bb024
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1524658313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1524658313
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2132330054
Short name T459
Test name
Test status
Simulation time 747425151 ps
CPU time 20.22 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 05:31:54 PM PDT 24
Peak memory 257344 kb
Host smart-58c2c44e-17cb-425b-a950-7a94c4bec066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
30054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2132330054
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.959895135
Short name T556
Test name
Test status
Simulation time 38592726 ps
CPU time 4.69 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:31:42 PM PDT 24
Peak memory 249196 kb
Host smart-6921394e-1235-4710-a813-9d289b470642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95989
5135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.959895135
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3893078175
Short name T701
Test name
Test status
Simulation time 160908863285 ps
CPU time 2510.85 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 06:13:28 PM PDT 24
Peak memory 286196 kb
Host smart-3e9709be-f4e5-4d1f-a714-e999c5c1bd03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893078175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3893078175
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2505003266
Short name T708
Test name
Test status
Simulation time 1471671406 ps
CPU time 44.91 seconds
Started Jul 06 05:31:29 PM PDT 24
Finished Jul 06 05:32:15 PM PDT 24
Peak memory 257428 kb
Host smart-5726b964-215b-433c-a0fc-317196445b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
03266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2505003266
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.464038914
Short name T80
Test name
Test status
Simulation time 1756737455 ps
CPU time 17.81 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:31:55 PM PDT 24
Peak memory 257284 kb
Host smart-5b81a75c-3003-4ba3-aa3d-4db36aee9128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46403
8914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.464038914
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.17745
Short name T419
Test name
Test status
Simulation time 89947690 ps
CPU time 7.41 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:31:46 PM PDT 24
Peak memory 248616 kb
Host smart-8a201326-03a4-4156-86a4-edf37dd4a8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
-assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.17745
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4266649747
Short name T428
Test name
Test status
Simulation time 265208361 ps
CPU time 20.09 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 05:31:54 PM PDT 24
Peak memory 257088 kb
Host smart-75763602-bbbb-4577-8348-7fc45f439c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
49747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4266649747
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4126106109
Short name T709
Test name
Test status
Simulation time 205864499516 ps
CPU time 2959.92 seconds
Started Jul 06 05:31:37 PM PDT 24
Finished Jul 06 06:20:59 PM PDT 24
Peak memory 289532 kb
Host smart-7e86e6e7-ad50-4f17-b688-c5029fa5bf83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126106109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4126106109
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2479600317
Short name T212
Test name
Test status
Simulation time 34647641 ps
CPU time 3.47 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 249584 kb
Host smart-fd5b58e2-9919-4686-b044-d73249e2a32d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2479600317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2479600317
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.767594817
Short name T692
Test name
Test status
Simulation time 20435889757 ps
CPU time 1152.88 seconds
Started Jul 06 05:31:02 PM PDT 24
Finished Jul 06 05:50:16 PM PDT 24
Peak memory 266732 kb
Host smart-fc23ef54-b2e6-4840-8a7e-7a63341d694f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767594817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.767594817
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.4130638580
Short name T469
Test name
Test status
Simulation time 1400911448 ps
CPU time 18.23 seconds
Started Jul 06 05:30:46 PM PDT 24
Finished Jul 06 05:31:05 PM PDT 24
Peak memory 249296 kb
Host smart-b4cd1a82-5c60-4637-ba58-b0083a80b8f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4130638580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.4130638580
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3111848063
Short name T498
Test name
Test status
Simulation time 14551016626 ps
CPU time 213.89 seconds
Started Jul 06 05:30:47 PM PDT 24
Finished Jul 06 05:34:21 PM PDT 24
Peak memory 257444 kb
Host smart-8d18a2b2-310c-4670-a990-5d622013040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31118
48063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3111848063
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3711019505
Short name T595
Test name
Test status
Simulation time 292773667 ps
CPU time 16.8 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:31:05 PM PDT 24
Peak memory 249228 kb
Host smart-3e403ce6-e7d0-4b07-b02e-fc85d077147e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110
19505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3711019505
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.566243330
Short name T323
Test name
Test status
Simulation time 72700810701 ps
CPU time 2284.89 seconds
Started Jul 06 05:31:05 PM PDT 24
Finished Jul 06 06:09:11 PM PDT 24
Peak memory 290224 kb
Host smart-5e64fe24-8a6f-4ff1-a43d-a3fecc7e5b66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566243330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.566243330
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2037169607
Short name T363
Test name
Test status
Simulation time 196842757822 ps
CPU time 2980.15 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 06:20:35 PM PDT 24
Peak memory 282132 kb
Host smart-6288b497-46f2-4021-885b-55976a72789a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037169607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2037169607
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2578236793
Short name T478
Test name
Test status
Simulation time 237585099 ps
CPU time 13.87 seconds
Started Jul 06 05:31:07 PM PDT 24
Finished Jul 06 05:31:21 PM PDT 24
Peak memory 249216 kb
Host smart-4db87c2b-d4e9-4592-9d95-545b0d474afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
36793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2578236793
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3937447115
Short name T56
Test name
Test status
Simulation time 610431454 ps
CPU time 38.73 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:31:32 PM PDT 24
Peak memory 256748 kb
Host smart-764f55f7-7352-46ea-a01d-74a5ca262ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
47115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3937447115
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.604792318
Short name T46
Test name
Test status
Simulation time 246282736 ps
CPU time 29.51 seconds
Started Jul 06 05:31:13 PM PDT 24
Finished Jul 06 05:31:43 PM PDT 24
Peak memory 249296 kb
Host smart-c4aa435b-6b8b-41a9-9307-71cf4de46357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60479
2318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.604792318
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2509444521
Short name T460
Test name
Test status
Simulation time 1951040659 ps
CPU time 30.38 seconds
Started Jul 06 05:31:15 PM PDT 24
Finished Jul 06 05:31:46 PM PDT 24
Peak memory 249260 kb
Host smart-d842fdc6-4715-4e82-967c-321f0ea90c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25094
44521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2509444521
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.290545815
Short name T389
Test name
Test status
Simulation time 7755383965 ps
CPU time 178.49 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:33:43 PM PDT 24
Peak memory 257600 kb
Host smart-15ce6ee0-8c5f-46a7-854a-1cf0a93dc9ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290545815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.290545815
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3978547915
Short name T25
Test name
Test status
Simulation time 266516007828 ps
CPU time 2039.23 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 06:04:53 PM PDT 24
Peak memory 306704 kb
Host smart-0e45c891-cf1f-42a5-8ca4-4647a6c3cd60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978547915 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3978547915
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1791077276
Short name T92
Test name
Test status
Simulation time 145812010159 ps
CPU time 2309.85 seconds
Started Jul 06 05:31:33 PM PDT 24
Finished Jul 06 06:10:04 PM PDT 24
Peak memory 289432 kb
Host smart-6bd3ded9-4ba9-4bf9-bbda-ac79c0b0821d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791077276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1791077276
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1892157442
Short name T266
Test name
Test status
Simulation time 410820943 ps
CPU time 49.72 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:32:26 PM PDT 24
Peak memory 250336 kb
Host smart-979aa546-dba2-4a77-8782-71093ef83098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18921
57442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1892157442
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2997308296
Short name T456
Test name
Test status
Simulation time 1968074998 ps
CPU time 33.3 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:32:10 PM PDT 24
Peak memory 248672 kb
Host smart-e0f4c271-4202-42f5-b503-d51829bdd3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29973
08296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2997308296
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2279311434
Short name T433
Test name
Test status
Simulation time 297182716440 ps
CPU time 2147.89 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 06:07:26 PM PDT 24
Peak memory 290376 kb
Host smart-9209ae1e-c53c-4f62-9632-a098b1b99910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279311434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2279311434
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3771393780
Short name T311
Test name
Test status
Simulation time 9136787774 ps
CPU time 293.21 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:36:37 PM PDT 24
Peak memory 248204 kb
Host smart-1086e191-078a-472e-a7e2-9346c6f94f5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771393780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3771393780
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3153402235
Short name T457
Test name
Test status
Simulation time 364940421 ps
CPU time 31.81 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:32:16 PM PDT 24
Peak memory 249192 kb
Host smart-c7f17e8e-e057-41da-bb20-2c3446bfd2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31534
02235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3153402235
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3677820451
Short name T22
Test name
Test status
Simulation time 500537035 ps
CPU time 28.29 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:32:06 PM PDT 24
Peak memory 249280 kb
Host smart-a6f8ce4a-3be4-418d-af20-c21f5bf56dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
20451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3677820451
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3295305330
Short name T282
Test name
Test status
Simulation time 89348829 ps
CPU time 11.89 seconds
Started Jul 06 05:31:37 PM PDT 24
Finished Jul 06 05:31:51 PM PDT 24
Peak memory 256796 kb
Host smart-269387e6-0104-472b-ac3a-f87122651dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
05330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3295305330
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1112620631
Short name T369
Test name
Test status
Simulation time 4032416164 ps
CPU time 29.86 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:32:05 PM PDT 24
Peak memory 256608 kb
Host smart-9c8cd7b0-208b-4709-8901-2b3175d0d1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11126
20631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1112620631
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3722542866
Short name T292
Test name
Test status
Simulation time 48491291032 ps
CPU time 2901.42 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 06:20:01 PM PDT 24
Peak memory 305608 kb
Host smart-53c58b78-4156-4cbe-be08-3eaf0e3fa0a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722542866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3722542866
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.237818756
Short name T110
Test name
Test status
Simulation time 42072626852 ps
CPU time 3930.62 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 06:37:10 PM PDT 24
Peak memory 339476 kb
Host smart-17cf0777-0e16-422b-b25e-dc9b9c5c7acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237818756 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.237818756
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4061012303
Short name T531
Test name
Test status
Simulation time 6516506242 ps
CPU time 694.62 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:43:14 PM PDT 24
Peak memory 266776 kb
Host smart-20c35b19-5d36-4500-927e-37f8cf5e3236
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061012303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4061012303
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.258544544
Short name T66
Test name
Test status
Simulation time 1425410558 ps
CPU time 112.69 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:33:27 PM PDT 24
Peak memory 257504 kb
Host smart-d113b025-c694-490e-a008-0adcc5fcecbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
4544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.258544544
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3141747761
Short name T662
Test name
Test status
Simulation time 220432643 ps
CPU time 5.5 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 249816 kb
Host smart-cd23eeec-f546-4351-ba3c-c8e12224a441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417
47761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3141747761
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.379906640
Short name T294
Test name
Test status
Simulation time 12710086632 ps
CPU time 1180 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:51:18 PM PDT 24
Peak memory 287972 kb
Host smart-d3aa12f2-5e79-42c6-84d3-d8a099cafd83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379906640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.379906640
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1255329286
Short name T580
Test name
Test status
Simulation time 37137815141 ps
CPU time 963.72 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:47:48 PM PDT 24
Peak memory 274180 kb
Host smart-bac114c9-7d2c-48cd-8234-a3838b1ae601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255329286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1255329286
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2061693041
Short name T304
Test name
Test status
Simulation time 41153886678 ps
CPU time 215.17 seconds
Started Jul 06 05:31:29 PM PDT 24
Finished Jul 06 05:35:04 PM PDT 24
Peak memory 255908 kb
Host smart-8b7e4202-c9ef-4dc2-b860-a7747bb4486a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061693041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2061693041
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3944893358
Short name T383
Test name
Test status
Simulation time 792866509 ps
CPU time 17.37 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:31:54 PM PDT 24
Peak memory 256476 kb
Host smart-f89c3ac8-a234-4762-89d1-04d1e077f2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
93358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3944893358
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1198393445
Short name T75
Test name
Test status
Simulation time 765048102 ps
CPU time 16.71 seconds
Started Jul 06 05:31:37 PM PDT 24
Finished Jul 06 05:31:55 PM PDT 24
Peak memory 249076 kb
Host smart-02348717-373f-49a9-b00c-c7509de8edea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11983
93445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1198393445
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2777218244
Short name T699
Test name
Test status
Simulation time 1517619702 ps
CPU time 32.04 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:32:07 PM PDT 24
Peak memory 257000 kb
Host smart-32cd1c4e-cdc1-4a20-bb1f-1ea2bbdc5ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27772
18244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2777218244
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2408301484
Short name T653
Test name
Test status
Simulation time 890386109 ps
CPU time 51.05 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:32:28 PM PDT 24
Peak memory 256596 kb
Host smart-fca85118-bd5b-404d-af94-d2e5f2e6e2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
01484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2408301484
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4285705568
Short name T551
Test name
Test status
Simulation time 32286556679 ps
CPU time 2259.74 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 06:09:16 PM PDT 24
Peak memory 289636 kb
Host smart-b3154c0f-a8e5-4e22-b075-068d849e610c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285705568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4285705568
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2702225087
Short name T578
Test name
Test status
Simulation time 21183238650 ps
CPU time 290.46 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:36:28 PM PDT 24
Peak memory 257504 kb
Host smart-faec336c-02c3-4dd7-94e6-81c9008895ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27022
25087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2702225087
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3654400292
Short name T607
Test name
Test status
Simulation time 1324754684 ps
CPU time 41.41 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:32:21 PM PDT 24
Peak memory 248972 kb
Host smart-da4deaa1-8901-40ab-a5dc-ad6dd02e48e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
00292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3654400292
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3998523977
Short name T640
Test name
Test status
Simulation time 61726306913 ps
CPU time 3056.35 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 06:22:34 PM PDT 24
Peak memory 289568 kb
Host smart-029b4d36-044f-43c0-9f26-762d823ce26a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998523977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3998523977
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3959640674
Short name T598
Test name
Test status
Simulation time 3795411150 ps
CPU time 131.4 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:33:48 PM PDT 24
Peak memory 249296 kb
Host smart-68902a2f-2f13-496e-ad1e-efc9c1593abc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959640674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3959640674
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2393945224
Short name T644
Test name
Test status
Simulation time 809027201 ps
CPU time 47.95 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:32:32 PM PDT 24
Peak memory 256872 kb
Host smart-6c583cf5-a9de-4b85-99ed-f00445e6e54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23939
45224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2393945224
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1801527396
Short name T78
Test name
Test status
Simulation time 1522818144 ps
CPU time 31.87 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:32:09 PM PDT 24
Peak memory 249116 kb
Host smart-69ee7c29-6ffa-4670-a530-6fa7e36139db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18015
27396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1801527396
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1444087772
Short name T287
Test name
Test status
Simulation time 2136421924 ps
CPU time 38.85 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 05:32:22 PM PDT 24
Peak memory 249316 kb
Host smart-df9d490a-05c9-4e0b-ab54-1b717142039a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
87772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1444087772
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1057412049
Short name T367
Test name
Test status
Simulation time 566672194 ps
CPU time 9.75 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:31:49 PM PDT 24
Peak memory 254336 kb
Host smart-61ce1b2d-fe3a-4854-a51e-046d0879a794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574
12049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1057412049
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2309193720
Short name T236
Test name
Test status
Simulation time 55364874886 ps
CPU time 1210.5 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:51:50 PM PDT 24
Peak memory 284792 kb
Host smart-cef7d18e-950e-43be-9223-538612590181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309193720 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2309193720
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3154222616
Short name T427
Test name
Test status
Simulation time 379358727290 ps
CPU time 1438.28 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:55:42 PM PDT 24
Peak memory 282772 kb
Host smart-6f77ce28-28d3-4211-90fd-f39399a77bf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154222616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3154222616
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.699664667
Short name T495
Test name
Test status
Simulation time 4379587856 ps
CPU time 257.62 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:35:56 PM PDT 24
Peak memory 257596 kb
Host smart-1655f212-9fe4-4c8c-a470-a39a37f21bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69966
4667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.699664667
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.715281840
Short name T18
Test name
Test status
Simulation time 663049749 ps
CPU time 5.78 seconds
Started Jul 06 05:31:39 PM PDT 24
Finished Jul 06 05:31:46 PM PDT 24
Peak memory 240664 kb
Host smart-d71de9a6-c589-4f54-a1c9-de2178b51681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71528
1840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.715281840
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2786396603
Short name T502
Test name
Test status
Simulation time 31941803669 ps
CPU time 1745.43 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 06:00:42 PM PDT 24
Peak memory 287088 kb
Host smart-6771ec88-c714-4fd7-ad87-d5d9b7067129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786396603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2786396603
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1612699435
Short name T660
Test name
Test status
Simulation time 7678715481 ps
CPU time 272.84 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:36:12 PM PDT 24
Peak memory 249252 kb
Host smart-4f568f39-e5d4-409b-8604-cda9c9fe0b3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612699435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1612699435
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2037966750
Short name T3
Test name
Test status
Simulation time 589066200 ps
CPU time 35.17 seconds
Started Jul 06 05:31:39 PM PDT 24
Finished Jul 06 05:32:15 PM PDT 24
Peak memory 256808 kb
Host smart-aebab233-19d5-4c40-b053-64d129892a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20379
66750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2037966750
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.792781041
Short name T69
Test name
Test status
Simulation time 1322421143 ps
CPU time 25.96 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:32:01 PM PDT 24
Peak memory 248776 kb
Host smart-881d9688-a93d-49c7-aafb-c6951af99d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79278
1041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.792781041
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1817815215
Short name T45
Test name
Test status
Simulation time 501908696 ps
CPU time 14.29 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:31:51 PM PDT 24
Peak memory 248780 kb
Host smart-2d425368-4ee4-4993-b342-e2cb429b32ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18178
15215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1817815215
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.848287358
Short name T219
Test name
Test status
Simulation time 6539213001 ps
CPU time 34.5 seconds
Started Jul 06 05:31:39 PM PDT 24
Finished Jul 06 05:32:14 PM PDT 24
Peak memory 257576 kb
Host smart-feb108ef-7c72-4713-bbba-ad731c46c942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84828
7358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.848287358
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3572701206
Short name T32
Test name
Test status
Simulation time 37618036044 ps
CPU time 2540.77 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 06:14:03 PM PDT 24
Peak memory 289792 kb
Host smart-ab211637-f732-4790-aa3c-1300be75ef23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572701206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3572701206
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1084004221
Short name T237
Test name
Test status
Simulation time 56976185108 ps
CPU time 724.29 seconds
Started Jul 06 05:31:39 PM PDT 24
Finished Jul 06 05:43:44 PM PDT 24
Peak memory 272092 kb
Host smart-2efe2821-042b-463e-801a-4a7fe6062d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084004221 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1084004221
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1939673545
Short name T101
Test name
Test status
Simulation time 65443779599 ps
CPU time 964.62 seconds
Started Jul 06 05:31:40 PM PDT 24
Finished Jul 06 05:47:45 PM PDT 24
Peak memory 286264 kb
Host smart-4caead25-3fcd-4b93-8369-3bfcc722ebd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939673545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1939673545
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1898911037
Short name T530
Test name
Test status
Simulation time 2032152073 ps
CPU time 137.36 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:33:53 PM PDT 24
Peak memory 256928 kb
Host smart-5d7af115-639e-434b-8bd0-fab3c2e350c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18989
11037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1898911037
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2434374918
Short name T527
Test name
Test status
Simulation time 2318248335 ps
CPU time 15.42 seconds
Started Jul 06 05:31:37 PM PDT 24
Finished Jul 06 05:31:54 PM PDT 24
Peak memory 257256 kb
Host smart-8577417a-6c97-48f4-b146-fbd346f1e2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
74918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2434374918
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1747689674
Short name T329
Test name
Test status
Simulation time 119384989500 ps
CPU time 1545.8 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:57:23 PM PDT 24
Peak memory 273500 kb
Host smart-b7c64705-a6e4-479a-91cc-534dac91f2f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747689674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1747689674
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2958749135
Short name T547
Test name
Test status
Simulation time 154919507030 ps
CPU time 2436.43 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 06:12:20 PM PDT 24
Peak memory 282908 kb
Host smart-54aeaebb-2eb8-4bc6-a37f-81a8d3d4cdd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958749135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2958749135
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1729641440
Short name T635
Test name
Test status
Simulation time 202979308578 ps
CPU time 544.94 seconds
Started Jul 06 05:31:35 PM PDT 24
Finished Jul 06 05:40:41 PM PDT 24
Peak memory 256476 kb
Host smart-b2c35298-4a0b-4b96-8163-16b2489f2b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729641440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1729641440
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1058162791
Short name T669
Test name
Test status
Simulation time 2307025503 ps
CPU time 41.99 seconds
Started Jul 06 05:31:37 PM PDT 24
Finished Jul 06 05:32:21 PM PDT 24
Peak memory 256764 kb
Host smart-89d37e6b-574d-4c13-8813-0a41146ba16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581
62791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1058162791
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2352437854
Short name T473
Test name
Test status
Simulation time 231955700 ps
CPU time 16.67 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:31:55 PM PDT 24
Peak memory 257256 kb
Host smart-c4b0f168-ca0b-4cd6-9f3d-8538382a9cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23524
37854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2352437854
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4184701082
Short name T61
Test name
Test status
Simulation time 1529548275 ps
CPU time 56.89 seconds
Started Jul 06 05:31:32 PM PDT 24
Finished Jul 06 05:32:30 PM PDT 24
Peak memory 256544 kb
Host smart-a24527f2-d060-42e1-8e8d-c8247665ceb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
01082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4184701082
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3046106789
Short name T360
Test name
Test status
Simulation time 2388810948 ps
CPU time 18.24 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 05:31:53 PM PDT 24
Peak memory 257484 kb
Host smart-b3153bb6-935a-4786-b516-502c3a82fa21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30461
06789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3046106789
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1392645254
Short name T122
Test name
Test status
Simulation time 39390461578 ps
CPU time 2396.41 seconds
Started Jul 06 05:31:34 PM PDT 24
Finished Jul 06 06:11:33 PM PDT 24
Peak memory 290216 kb
Host smart-808d203d-22a6-4adb-81d8-fd3d204e16d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392645254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1392645254
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1460162936
Short name T281
Test name
Test status
Simulation time 15381178592 ps
CPU time 1090.07 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 05:49:53 PM PDT 24
Peak memory 273524 kb
Host smart-e56c2f83-b4f5-4777-9fe3-486a0b097eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460162936 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1460162936
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.348060688
Short name T38
Test name
Test status
Simulation time 112088015387 ps
CPU time 1507.53 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:56:52 PM PDT 24
Peak memory 267788 kb
Host smart-87a2a7c3-10d4-435f-91b5-48e2bbd22729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348060688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.348060688
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1099240684
Short name T574
Test name
Test status
Simulation time 1827498140 ps
CPU time 57.18 seconds
Started Jul 06 05:31:45 PM PDT 24
Finished Jul 06 05:32:43 PM PDT 24
Peak memory 256760 kb
Host smart-4af9c807-0b02-467b-9400-3fb4296e174d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10992
40684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1099240684
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2992266063
Short name T76
Test name
Test status
Simulation time 563155436 ps
CPU time 17.67 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:32:02 PM PDT 24
Peak memory 249224 kb
Host smart-48846f05-cc87-4ccc-9c0b-1a6bfb84598d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29922
66063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2992266063
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.386639096
Short name T114
Test name
Test status
Simulation time 14608033962 ps
CPU time 1242.95 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:52:28 PM PDT 24
Peak memory 282376 kb
Host smart-fcf2ba7e-5e8b-47eb-b411-ec68ebbe1c74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386639096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.386639096
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3237606124
Short name T712
Test name
Test status
Simulation time 134045246365 ps
CPU time 1402.24 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 05:55:10 PM PDT 24
Peak memory 265812 kb
Host smart-51db71e0-479b-4ada-ab80-dc18ce238cc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237606124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3237606124
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3162395641
Short name T299
Test name
Test status
Simulation time 27384461297 ps
CPU time 343.36 seconds
Started Jul 06 05:31:45 PM PDT 24
Finished Jul 06 05:37:28 PM PDT 24
Peak memory 249400 kb
Host smart-d39d3dca-6095-4688-a12f-48c77435bb6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162395641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3162395641
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3336922787
Short name T226
Test name
Test status
Simulation time 324246786 ps
CPU time 28.17 seconds
Started Jul 06 05:31:39 PM PDT 24
Finished Jul 06 05:32:08 PM PDT 24
Peak memory 249284 kb
Host smart-40561244-cc83-490e-bca6-d544d02808dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33369
22787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3336922787
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.676403956
Short name T601
Test name
Test status
Simulation time 771756677 ps
CPU time 38.56 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 05:32:21 PM PDT 24
Peak memory 256944 kb
Host smart-6f51b0da-d5a3-4248-8cf1-7624a1f462d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67640
3956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.676403956
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3195419780
Short name T436
Test name
Test status
Simulation time 1568774682 ps
CPU time 31.79 seconds
Started Jul 06 05:31:45 PM PDT 24
Finished Jul 06 05:32:17 PM PDT 24
Peak memory 257172 kb
Host smart-d372c806-1bc0-460d-946d-4180618fcc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31954
19780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3195419780
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3537919942
Short name T86
Test name
Test status
Simulation time 34120696644 ps
CPU time 2105.18 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 06:06:50 PM PDT 24
Peak memory 290120 kb
Host smart-3a876df6-d810-4535-80ad-676d2c739f4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537919942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3537919942
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2530334848
Short name T577
Test name
Test status
Simulation time 80865505506 ps
CPU time 1431.62 seconds
Started Jul 06 05:31:36 PM PDT 24
Finished Jul 06 05:55:30 PM PDT 24
Peak memory 289664 kb
Host smart-0a5db890-eb20-4bbd-9518-a4913df3b0ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530334848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2530334848
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3444815356
Short name T464
Test name
Test status
Simulation time 3198896766 ps
CPU time 87.02 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:33:12 PM PDT 24
Peak memory 257612 kb
Host smart-5db11277-f260-4d10-983a-771cc6fc4e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34448
15356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3444815356
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.70127983
Short name T88
Test name
Test status
Simulation time 86601547 ps
CPU time 5.01 seconds
Started Jul 06 05:31:38 PM PDT 24
Finished Jul 06 05:31:44 PM PDT 24
Peak memory 240584 kb
Host smart-78cf1cc8-04d7-4478-aecd-2be5443ae92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70127
983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.70127983
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.172325257
Short name T445
Test name
Test status
Simulation time 30327768961 ps
CPU time 1719.61 seconds
Started Jul 06 05:31:40 PM PDT 24
Finished Jul 06 06:00:20 PM PDT 24
Peak memory 273876 kb
Host smart-748f6836-0908-4cdb-91f4-e8c13c0d7343
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172325257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.172325257
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3519799504
Short name T541
Test name
Test status
Simulation time 111174658563 ps
CPU time 349.46 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:37:34 PM PDT 24
Peak memory 249196 kb
Host smart-2e7d2004-9f08-4c99-8cf3-bb01d882ea30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519799504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3519799504
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2379035602
Short name T375
Test name
Test status
Simulation time 324172108 ps
CPU time 7.21 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 249288 kb
Host smart-003f1e1a-0671-46d9-921d-739d0ab9f005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
35602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2379035602
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2618065845
Short name T518
Test name
Test status
Simulation time 464082865 ps
CPU time 16.42 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:32:00 PM PDT 24
Peak memory 256972 kb
Host smart-05c3f4c8-b84b-4fec-9282-35b9894545df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26180
65845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2618065845
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3855101518
Short name T558
Test name
Test status
Simulation time 2972340756 ps
CPU time 45.64 seconds
Started Jul 06 05:31:41 PM PDT 24
Finished Jul 06 05:32:27 PM PDT 24
Peak memory 256660 kb
Host smart-810de6f9-5043-4a89-87d1-2cdee099e3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
01518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3855101518
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1959425766
Short name T44
Test name
Test status
Simulation time 5948200840 ps
CPU time 56.18 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:32:41 PM PDT 24
Peak memory 256576 kb
Host smart-adfa9528-92f1-43a0-8142-8df961913be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
25766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1959425766
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1713698704
Short name T562
Test name
Test status
Simulation time 66113620208 ps
CPU time 2370.86 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 06:11:15 PM PDT 24
Peak memory 289700 kb
Host smart-a404d5b0-fd42-4b45-9931-aaeb0327d3ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713698704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1713698704
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1964762262
Short name T629
Test name
Test status
Simulation time 198430110720 ps
CPU time 3162.34 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 06:24:30 PM PDT 24
Peak memory 290124 kb
Host smart-3e59509d-d2e2-4994-94bc-900c86d61bb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964762262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1964762262
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1387592837
Short name T386
Test name
Test status
Simulation time 7614346700 ps
CPU time 135.56 seconds
Started Jul 06 05:31:48 PM PDT 24
Finished Jul 06 05:34:04 PM PDT 24
Peak memory 257596 kb
Host smart-8e80de3d-6e69-4e12-b83f-7a6e8ee2c72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13875
92837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1387592837
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3570987238
Short name T573
Test name
Test status
Simulation time 925532031 ps
CPU time 29.97 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:32:13 PM PDT 24
Peak memory 249208 kb
Host smart-017772ff-17f3-45a9-840e-c9615256b9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35709
87238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3570987238
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3846213630
Short name T636
Test name
Test status
Simulation time 456659344843 ps
CPU time 2121.89 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 06:07:09 PM PDT 24
Peak memory 273912 kb
Host smart-b649deca-e09e-4da7-b001-52fc8b9c91a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846213630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3846213630
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1982965719
Short name T589
Test name
Test status
Simulation time 10793416281 ps
CPU time 649.41 seconds
Started Jul 06 05:31:41 PM PDT 24
Finished Jul 06 05:42:31 PM PDT 24
Peak memory 273772 kb
Host smart-289eedad-81e9-4549-99b1-b00df173d546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982965719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1982965719
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1980281621
Short name T707
Test name
Test status
Simulation time 7250458847 ps
CPU time 287.76 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 05:36:35 PM PDT 24
Peak memory 256668 kb
Host smart-e35631a2-c15b-4dbc-9d11-fa0ef257ed73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980281621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1980281621
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.18287464
Short name T606
Test name
Test status
Simulation time 691767253 ps
CPU time 42.94 seconds
Started Jul 06 05:31:46 PM PDT 24
Finished Jul 06 05:32:29 PM PDT 24
Peak memory 256472 kb
Host smart-60bb0622-4192-4fa7-b00d-fb2418b757e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18287
464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.18287464
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3230098857
Short name T394
Test name
Test status
Simulation time 223753829 ps
CPU time 15.77 seconds
Started Jul 06 05:31:42 PM PDT 24
Finished Jul 06 05:31:58 PM PDT 24
Peak memory 255368 kb
Host smart-672f7743-a2c2-4996-b199-9c091eed6108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
98857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3230098857
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.586147475
Short name T480
Test name
Test status
Simulation time 334470847 ps
CPU time 9.93 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 05:31:57 PM PDT 24
Peak memory 249580 kb
Host smart-379b02c1-cb89-4105-9278-6a3116909cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58614
7475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.586147475
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1128466506
Short name T605
Test name
Test status
Simulation time 1300163198 ps
CPU time 69.39 seconds
Started Jul 06 05:31:39 PM PDT 24
Finished Jul 06 05:32:49 PM PDT 24
Peak memory 257368 kb
Host smart-a5b8c1f8-5569-4109-95e2-8cd449eaad8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11284
66506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1128466506
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3133543986
Short name T259
Test name
Test status
Simulation time 9038403284 ps
CPU time 122.59 seconds
Started Jul 06 05:31:46 PM PDT 24
Finished Jul 06 05:33:49 PM PDT 24
Peak memory 257560 kb
Host smart-02644d16-5d9d-458e-aae5-66cf95fc56c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133543986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3133543986
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2544024477
Short name T242
Test name
Test status
Simulation time 209902525349 ps
CPU time 2009.95 seconds
Started Jul 06 05:31:41 PM PDT 24
Finished Jul 06 06:05:11 PM PDT 24
Peak memory 273276 kb
Host smart-9cf19606-0773-428d-8717-6871480c45e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544024477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2544024477
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4056321725
Short name T47
Test name
Test status
Simulation time 8681851567 ps
CPU time 225.86 seconds
Started Jul 06 05:31:44 PM PDT 24
Finished Jul 06 05:35:31 PM PDT 24
Peak memory 256680 kb
Host smart-a7cf92ef-3467-4005-89cd-c56567113a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40563
21725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4056321725
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1646228102
Short name T286
Test name
Test status
Simulation time 1262940668 ps
CPU time 14.07 seconds
Started Jul 06 05:31:45 PM PDT 24
Finished Jul 06 05:31:59 PM PDT 24
Peak memory 249220 kb
Host smart-bd261a70-911e-42c7-91a1-31628aed21bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16462
28102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1646228102
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1639625853
Short name T465
Test name
Test status
Simulation time 249687678646 ps
CPU time 2587.32 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 06:14:55 PM PDT 24
Peak memory 286236 kb
Host smart-faa454bd-3a12-437f-9f41-a5d12d004955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639625853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1639625853
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1884682853
Short name T119
Test name
Test status
Simulation time 21080063 ps
CPU time 3.08 seconds
Started Jul 06 05:31:47 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 249268 kb
Host smart-62ad512e-f487-4693-a4d8-15c3406b7300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18846
82853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1884682853
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2731570287
Short name T572
Test name
Test status
Simulation time 338569493 ps
CPU time 33.6 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:32:18 PM PDT 24
Peak memory 249228 kb
Host smart-2d940216-4d58-4af6-a298-cf327e7e5008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
70287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2731570287
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2677832184
Short name T489
Test name
Test status
Simulation time 322278829 ps
CPU time 25.56 seconds
Started Jul 06 05:31:43 PM PDT 24
Finished Jul 06 05:32:09 PM PDT 24
Peak memory 256312 kb
Host smart-75b52dd5-17b0-464d-997e-85fe8b40a61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778
32184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2677832184
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1204465718
Short name T568
Test name
Test status
Simulation time 777471974 ps
CPU time 17.51 seconds
Started Jul 06 05:31:40 PM PDT 24
Finished Jul 06 05:31:58 PM PDT 24
Peak memory 256400 kb
Host smart-7c2f87c3-7b70-43f9-b928-ce71785362a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12044
65718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1204465718
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2075494288
Short name T377
Test name
Test status
Simulation time 47324760659 ps
CPU time 1455.01 seconds
Started Jul 06 05:31:50 PM PDT 24
Finished Jul 06 05:56:06 PM PDT 24
Peak memory 273020 kb
Host smart-b01806a4-53ea-464e-8021-94656b43af8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075494288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2075494288
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1197982771
Short name T615
Test name
Test status
Simulation time 5845913986 ps
CPU time 607.44 seconds
Started Jul 06 05:31:58 PM PDT 24
Finished Jul 06 05:42:06 PM PDT 24
Peak memory 265768 kb
Host smart-0f2263fc-359f-4055-b785-f8f1f06875e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197982771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1197982771
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1030483557
Short name T403
Test name
Test status
Simulation time 1446864481 ps
CPU time 85.61 seconds
Started Jul 06 05:31:49 PM PDT 24
Finished Jul 06 05:33:15 PM PDT 24
Peak memory 256852 kb
Host smart-799e0aaf-513e-4239-9623-ad2d77f044be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10304
83557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1030483557
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2428492584
Short name T519
Test name
Test status
Simulation time 938730834 ps
CPU time 58.55 seconds
Started Jul 06 05:31:45 PM PDT 24
Finished Jul 06 05:32:44 PM PDT 24
Peak memory 257364 kb
Host smart-805487d6-0f95-442c-9969-50f87d948f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24284
92584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2428492584
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1020729442
Short name T676
Test name
Test status
Simulation time 21219359377 ps
CPU time 956.06 seconds
Started Jul 06 05:31:52 PM PDT 24
Finished Jul 06 05:47:49 PM PDT 24
Peak memory 273872 kb
Host smart-b49a81af-d862-470e-890b-8f754b0584c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020729442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1020729442
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3437574999
Short name T107
Test name
Test status
Simulation time 8614376547 ps
CPU time 902.98 seconds
Started Jul 06 05:31:59 PM PDT 24
Finished Jul 06 05:47:03 PM PDT 24
Peak memory 273992 kb
Host smart-f49e8b82-43df-4297-883b-2a7de9d61960
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437574999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3437574999
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3135708591
Short name T253
Test name
Test status
Simulation time 62798250239 ps
CPU time 602.17 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:41:56 PM PDT 24
Peak memory 249152 kb
Host smart-9e1b538f-a010-4b4c-b957-310204bf73c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135708591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3135708591
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1309296594
Short name T447
Test name
Test status
Simulation time 355105784 ps
CPU time 19.23 seconds
Started Jul 06 05:31:46 PM PDT 24
Finished Jul 06 05:32:05 PM PDT 24
Peak memory 256768 kb
Host smart-5f0345e6-0f13-4f72-861e-a5868821e7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13092
96594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1309296594
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.416769347
Short name T53
Test name
Test status
Simulation time 6332194265 ps
CPU time 34.35 seconds
Started Jul 06 05:31:50 PM PDT 24
Finished Jul 06 05:32:25 PM PDT 24
Peak memory 256468 kb
Host smart-c81dfe34-36df-4ff6-8163-a813b852c7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41676
9347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.416769347
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1122713511
Short name T650
Test name
Test status
Simulation time 1967916452 ps
CPU time 55.29 seconds
Started Jul 06 05:31:45 PM PDT 24
Finished Jul 06 05:32:41 PM PDT 24
Peak memory 256944 kb
Host smart-490fa9ec-474e-4c20-a1da-d0b6210a0f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
13511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1122713511
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1855558668
Short name T370
Test name
Test status
Simulation time 1211989043 ps
CPU time 72.94 seconds
Started Jul 06 05:31:46 PM PDT 24
Finished Jul 06 05:32:59 PM PDT 24
Peak memory 249272 kb
Host smart-5fdbfddf-4b92-41b9-ab01-fcd70b3731e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555
58668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1855558668
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2727077387
Short name T206
Test name
Test status
Simulation time 20763203 ps
CPU time 2.76 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 05:31:00 PM PDT 24
Peak memory 249540 kb
Host smart-fea10cf3-c01b-4f49-9a34-712b4dc691b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2727077387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2727077387
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.838961105
Short name T500
Test name
Test status
Simulation time 40825741988 ps
CPU time 1077.3 seconds
Started Jul 06 05:31:02 PM PDT 24
Finished Jul 06 05:49:00 PM PDT 24
Peak memory 288056 kb
Host smart-fe1741e3-7bcf-48b0-aaeb-97207a54f7ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838961105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.838961105
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3954561867
Short name T672
Test name
Test status
Simulation time 578986905 ps
CPU time 15.89 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:31:04 PM PDT 24
Peak memory 249284 kb
Host smart-28031d7d-7b73-498c-a6d8-0aa9685aa7fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3954561867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3954561867
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1430645358
Short name T507
Test name
Test status
Simulation time 8775168930 ps
CPU time 251.25 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:35:22 PM PDT 24
Peak memory 257104 kb
Host smart-41cb4cb9-f856-4a82-bd7e-3aa6873645e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14306
45358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1430645358
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3278775698
Short name T696
Test name
Test status
Simulation time 803016852 ps
CPU time 15.52 seconds
Started Jul 06 05:31:09 PM PDT 24
Finished Jul 06 05:31:25 PM PDT 24
Peak memory 249740 kb
Host smart-5f54720f-b0b1-46c3-b259-31a14ceb9b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32787
75698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3278775698
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3409685470
Short name T659
Test name
Test status
Simulation time 64530112641 ps
CPU time 929.32 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:46:19 PM PDT 24
Peak memory 282500 kb
Host smart-1be13b2c-9be5-4d14-a3cc-7a24b6cf908d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409685470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3409685470
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.501575717
Short name T7
Test name
Test status
Simulation time 71238743935 ps
CPU time 1667.26 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:58:39 PM PDT 24
Peak memory 290204 kb
Host smart-7aa3bf61-c20d-4cf4-a580-f64c955eacef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501575717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.501575717
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3256247239
Short name T657
Test name
Test status
Simulation time 125557801556 ps
CPU time 571.97 seconds
Started Jul 06 05:31:08 PM PDT 24
Finished Jul 06 05:40:41 PM PDT 24
Peak memory 255936 kb
Host smart-0bca5476-2cb8-4355-bcbe-0cdf13b2bbf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256247239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3256247239
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3481343854
Short name T402
Test name
Test status
Simulation time 772882029 ps
CPU time 42.23 seconds
Started Jul 06 05:31:02 PM PDT 24
Finished Jul 06 05:31:44 PM PDT 24
Peak memory 257028 kb
Host smart-69edad3c-71e2-40bf-ac45-0b7913dfc525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34813
43854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3481343854
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.804512375
Short name T385
Test name
Test status
Simulation time 2518507078 ps
CPU time 51.42 seconds
Started Jul 06 05:30:59 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 257140 kb
Host smart-f51770a0-8d40-4c1e-8b10-3462663577bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80451
2375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.804512375
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3534707963
Short name T35
Test name
Test status
Simulation time 1855540407 ps
CPU time 26.86 seconds
Started Jul 06 05:31:04 PM PDT 24
Finished Jul 06 05:31:31 PM PDT 24
Peak memory 270584 kb
Host smart-ab001195-e8ee-4d01-8730-9189fcaa47cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3534707963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3534707963
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.411005212
Short name T406
Test name
Test status
Simulation time 2412394993 ps
CPU time 30.88 seconds
Started Jul 06 05:30:56 PM PDT 24
Finished Jul 06 05:31:27 PM PDT 24
Peak memory 249912 kb
Host smart-887f5b10-9c50-4d2d-85ba-7befb5fa951e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41100
5212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.411005212
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2286436074
Short name T550
Test name
Test status
Simulation time 1153938948 ps
CPU time 66.43 seconds
Started Jul 06 05:30:51 PM PDT 24
Finished Jul 06 05:31:58 PM PDT 24
Peak memory 257408 kb
Host smart-30644614-fd47-4181-b630-b3b63366404f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22864
36074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2286436074
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4118780425
Short name T382
Test name
Test status
Simulation time 1293297028 ps
CPU time 98.99 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:32:29 PM PDT 24
Peak memory 257480 kb
Host smart-345e48cb-7081-44d7-aadc-75be67fac06a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118780425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4118780425
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1154913710
Short name T444
Test name
Test status
Simulation time 76357364189 ps
CPU time 1704.26 seconds
Started Jul 06 05:31:52 PM PDT 24
Finished Jul 06 06:00:17 PM PDT 24
Peak memory 273952 kb
Host smart-a0804355-07e4-4161-a58f-9034a990e36c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154913710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1154913710
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2186228187
Short name T247
Test name
Test status
Simulation time 11107383356 ps
CPU time 87.41 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:33:21 PM PDT 24
Peak memory 256772 kb
Host smart-4e4461fe-712b-454a-963d-d29fec1fa3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21862
28187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2186228187
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3448811844
Short name T239
Test name
Test status
Simulation time 1748639225 ps
CPU time 36.12 seconds
Started Jul 06 05:31:54 PM PDT 24
Finished Jul 06 05:32:30 PM PDT 24
Peak memory 256392 kb
Host smart-3236b094-d4e6-4b82-a5bd-0836efbde6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
11844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3448811844
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.60679462
Short name T123
Test name
Test status
Simulation time 164658614022 ps
CPU time 1361.12 seconds
Started Jul 06 05:31:54 PM PDT 24
Finished Jul 06 05:54:35 PM PDT 24
Peak memory 290320 kb
Host smart-a44f3422-a1ca-433c-856c-8f6874cf1b1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60679462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.60679462
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4246992823
Short name T471
Test name
Test status
Simulation time 80144735498 ps
CPU time 1476.67 seconds
Started Jul 06 05:31:57 PM PDT 24
Finished Jul 06 05:56:34 PM PDT 24
Peak memory 289388 kb
Host smart-f2e48ffb-c7aa-47a2-b282-91bbc9f881be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246992823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4246992823
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3525769087
Short name T510
Test name
Test status
Simulation time 34487303189 ps
CPU time 278.35 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:36:32 PM PDT 24
Peak memory 256072 kb
Host smart-ad4d6be1-4164-48d1-addd-5bfa621e2fb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525769087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3525769087
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1829320474
Short name T656
Test name
Test status
Simulation time 502795075 ps
CPU time 21.01 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:32:15 PM PDT 24
Peak memory 256760 kb
Host smart-970933bd-4261-4ec5-a6ad-0a98ed0b091d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18293
20474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1829320474
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2581780434
Short name T581
Test name
Test status
Simulation time 1156247672 ps
CPU time 70.48 seconds
Started Jul 06 05:31:54 PM PDT 24
Finished Jul 06 05:33:05 PM PDT 24
Peak memory 249268 kb
Host smart-08b1e573-af67-4cee-889d-8608612f506a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25817
80434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2581780434
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2433314910
Short name T414
Test name
Test status
Simulation time 4274439823 ps
CPU time 27.58 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:32:21 PM PDT 24
Peak memory 249448 kb
Host smart-acbee860-a6fb-4b2f-8fc4-73629c360538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24333
14910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2433314910
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3842338031
Short name T505
Test name
Test status
Simulation time 3054525929 ps
CPU time 54.68 seconds
Started Jul 06 05:31:53 PM PDT 24
Finished Jul 06 05:32:48 PM PDT 24
Peak memory 256704 kb
Host smart-d997e400-23aa-4f43-88a2-1fefff6c8686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38423
38031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3842338031
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2991412859
Short name T508
Test name
Test status
Simulation time 55973707342 ps
CPU time 1449.83 seconds
Started Jul 06 05:31:56 PM PDT 24
Finished Jul 06 05:56:06 PM PDT 24
Peak memory 290220 kb
Host smart-b165a262-1585-4a9b-a9e0-5effe656335c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991412859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2991412859
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2280918809
Short name T31
Test name
Test status
Simulation time 229021006972 ps
CPU time 4925.03 seconds
Started Jul 06 05:31:56 PM PDT 24
Finished Jul 06 06:54:02 PM PDT 24
Peak memory 304464 kb
Host smart-1d529ea2-d774-4010-a7d8-64ecc90d3b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280918809 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2280918809
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.124743597
Short name T98
Test name
Test status
Simulation time 113817991052 ps
CPU time 1808.37 seconds
Started Jul 06 05:31:56 PM PDT 24
Finished Jul 06 06:02:05 PM PDT 24
Peak memory 273968 kb
Host smart-b0519d44-fe97-4ff3-a481-96d0ce780266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124743597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.124743597
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3087585266
Short name T113
Test name
Test status
Simulation time 1446194300 ps
CPU time 25.08 seconds
Started Jul 06 05:32:00 PM PDT 24
Finished Jul 06 05:32:25 PM PDT 24
Peak memory 257024 kb
Host smart-7fc6ee60-b26f-4b3a-b861-35f7b565a478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30875
85266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3087585266
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.230259764
Short name T407
Test name
Test status
Simulation time 1193808749 ps
CPU time 26.41 seconds
Started Jul 06 05:32:00 PM PDT 24
Finished Jul 06 05:32:26 PM PDT 24
Peak memory 249136 kb
Host smart-d4f717a3-c29c-49ba-8354-a6d2dd406ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
9764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.230259764
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3769792039
Short name T336
Test name
Test status
Simulation time 41362049124 ps
CPU time 835.01 seconds
Started Jul 06 05:31:57 PM PDT 24
Finished Jul 06 05:45:52 PM PDT 24
Peak memory 273616 kb
Host smart-1d6d29ff-d71d-4169-8519-e05216022897
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769792039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3769792039
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.4221497957
Short name T520
Test name
Test status
Simulation time 309284039753 ps
CPU time 2496.72 seconds
Started Jul 06 05:31:58 PM PDT 24
Finished Jul 06 06:13:35 PM PDT 24
Peak memory 273320 kb
Host smart-c0852b6d-2700-4313-8775-fd532669fa28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221497957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.4221497957
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2857304410
Short name T666
Test name
Test status
Simulation time 4719956095 ps
CPU time 188.67 seconds
Started Jul 06 05:31:57 PM PDT 24
Finished Jul 06 05:35:06 PM PDT 24
Peak memory 249232 kb
Host smart-0a06dd86-ee60-4a39-8257-a7f63d14687a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857304410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2857304410
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1449914996
Short name T576
Test name
Test status
Simulation time 493371217 ps
CPU time 31.8 seconds
Started Jul 06 05:32:00 PM PDT 24
Finished Jul 06 05:32:32 PM PDT 24
Peak memory 256608 kb
Host smart-714de635-54c3-476c-a55f-c1d817cf57cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14499
14996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1449914996
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2652747345
Short name T695
Test name
Test status
Simulation time 398735461 ps
CPU time 16.23 seconds
Started Jul 06 05:31:57 PM PDT 24
Finished Jul 06 05:32:14 PM PDT 24
Peak memory 256008 kb
Host smart-fbea3050-1b56-4348-b35c-a1d8f2912ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26527
47345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2652747345
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1337633453
Short name T643
Test name
Test status
Simulation time 130584631 ps
CPU time 10.15 seconds
Started Jul 06 05:31:55 PM PDT 24
Finished Jul 06 05:32:06 PM PDT 24
Peak memory 248804 kb
Host smart-56287c0f-6b9e-4b3b-a2ee-4fd487ad58cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
33453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1337633453
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.912045213
Short name T594
Test name
Test status
Simulation time 1823981684 ps
CPU time 30.91 seconds
Started Jul 06 05:31:56 PM PDT 24
Finished Jul 06 05:32:28 PM PDT 24
Peak memory 257456 kb
Host smart-d585b75e-dc1f-4178-b36f-74fae063efae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91204
5213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.912045213
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2337798502
Short name T488
Test name
Test status
Simulation time 299314762608 ps
CPU time 1752.8 seconds
Started Jul 06 05:31:56 PM PDT 24
Finished Jul 06 06:01:09 PM PDT 24
Peak memory 306208 kb
Host smart-68bd1a26-4467-44cf-b2e2-d42f7b35c9f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337798502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2337798502
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1898499614
Short name T255
Test name
Test status
Simulation time 224897234676 ps
CPU time 5019.74 seconds
Started Jul 06 05:32:01 PM PDT 24
Finished Jul 06 06:55:42 PM PDT 24
Peak memory 347656 kb
Host smart-e7d911b7-1e52-48d8-891c-912756bc221f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898499614 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1898499614
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.51907724
Short name T225
Test name
Test status
Simulation time 56533993643 ps
CPU time 3017.9 seconds
Started Jul 06 05:32:03 PM PDT 24
Finished Jul 06 06:22:21 PM PDT 24
Peak memory 290244 kb
Host smart-a43d1bd4-7151-4af4-96b0-1bca564c304c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51907724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.51907724
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4143788515
Short name T398
Test name
Test status
Simulation time 6154215675 ps
CPU time 114.5 seconds
Started Jul 06 05:32:00 PM PDT 24
Finished Jul 06 05:33:55 PM PDT 24
Peak memory 257148 kb
Host smart-bc0c7c80-37b6-4bce-ba04-96390127015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41437
88515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4143788515
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2780475785
Short name T680
Test name
Test status
Simulation time 1460104406 ps
CPU time 19.32 seconds
Started Jul 06 05:32:02 PM PDT 24
Finished Jul 06 05:32:21 PM PDT 24
Peak memory 248640 kb
Host smart-cbef40bf-254e-4abf-a605-0e0d4c7d02f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27804
75785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2780475785
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2309266604
Short name T293
Test name
Test status
Simulation time 23029256652 ps
CPU time 1258.88 seconds
Started Jul 06 05:32:00 PM PDT 24
Finished Jul 06 05:52:59 PM PDT 24
Peak memory 273224 kb
Host smart-86214eaf-9626-4120-971b-cff253d8009d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309266604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2309266604
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3383707305
Short name T627
Test name
Test status
Simulation time 32843393864 ps
CPU time 647.34 seconds
Started Jul 06 05:32:02 PM PDT 24
Finished Jul 06 05:42:50 PM PDT 24
Peak memory 273972 kb
Host smart-cfdb64f4-017b-4ff7-8c2a-7ea30299014e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383707305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3383707305
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1508791754
Short name T300
Test name
Test status
Simulation time 10842952115 ps
CPU time 248.7 seconds
Started Jul 06 05:32:00 PM PDT 24
Finished Jul 06 05:36:09 PM PDT 24
Peak memory 249396 kb
Host smart-facf809d-3b2b-47af-8d6b-a5e8ddfbc030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508791754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1508791754
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3400914341
Short name T241
Test name
Test status
Simulation time 3651630427 ps
CPU time 38.49 seconds
Started Jul 06 05:32:02 PM PDT 24
Finished Jul 06 05:32:41 PM PDT 24
Peak memory 257324 kb
Host smart-f035db92-cf73-4e09-a328-45261270a6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
14341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3400914341
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.580057753
Short name T395
Test name
Test status
Simulation time 892524693 ps
CPU time 30.22 seconds
Started Jul 06 05:32:02 PM PDT 24
Finished Jul 06 05:32:32 PM PDT 24
Peak memory 256448 kb
Host smart-cb3995b7-4e58-44c3-9061-0f4eb27f2f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58005
7753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.580057753
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2110819666
Short name T97
Test name
Test status
Simulation time 809095616 ps
CPU time 23.36 seconds
Started Jul 06 05:32:01 PM PDT 24
Finished Jul 06 05:32:25 PM PDT 24
Peak memory 248420 kb
Host smart-19db3cdb-b93f-4950-a28a-aa75c75c05a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
19666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2110819666
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1261865248
Short name T524
Test name
Test status
Simulation time 274811900 ps
CPU time 15.43 seconds
Started Jul 06 05:32:01 PM PDT 24
Finished Jul 06 05:32:16 PM PDT 24
Peak memory 249480 kb
Host smart-ac2d6351-fbc2-4548-8cfd-c5c9d36ff890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12618
65248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1261865248
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3748916781
Short name T100
Test name
Test status
Simulation time 29875330542 ps
CPU time 430.89 seconds
Started Jul 06 05:32:08 PM PDT 24
Finished Jul 06 05:39:19 PM PDT 24
Peak memory 257516 kb
Host smart-b763dde6-e9bd-4db9-9141-e1e79dacc430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748916781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3748916781
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3842915066
Short name T103
Test name
Test status
Simulation time 138844802128 ps
CPU time 1233 seconds
Started Jul 06 05:32:08 PM PDT 24
Finished Jul 06 05:52:42 PM PDT 24
Peak memory 288640 kb
Host smart-9ee16a2f-3103-4834-8886-0a1bf8d8e17b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842915066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3842915066
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1367860077
Short name T271
Test name
Test status
Simulation time 3011376226 ps
CPU time 161.1 seconds
Started Jul 06 05:32:10 PM PDT 24
Finished Jul 06 05:34:51 PM PDT 24
Peak memory 257588 kb
Host smart-53a02428-923b-4f65-8ecb-a66b56ed0660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
60077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1367860077
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1107028508
Short name T422
Test name
Test status
Simulation time 887030146 ps
CPU time 4.72 seconds
Started Jul 06 05:32:05 PM PDT 24
Finished Jul 06 05:32:10 PM PDT 24
Peak memory 241040 kb
Host smart-768328ef-9f1f-40de-8e95-0d8155d908cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11070
28508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1107028508
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3719431437
Short name T340
Test name
Test status
Simulation time 10408060202 ps
CPU time 1063.74 seconds
Started Jul 06 05:32:10 PM PDT 24
Finished Jul 06 05:49:54 PM PDT 24
Peak memory 282204 kb
Host smart-c03c0afe-8906-4e7e-8a15-19afa62250ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719431437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3719431437
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1187075818
Short name T362
Test name
Test status
Simulation time 22090953524 ps
CPU time 1386.34 seconds
Started Jul 06 05:32:04 PM PDT 24
Finished Jul 06 05:55:11 PM PDT 24
Peak memory 273700 kb
Host smart-2cdc9bee-e192-489f-ae31-b96e715ecb1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187075818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1187075818
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2561538168
Short name T319
Test name
Test status
Simulation time 5395805487 ps
CPU time 114.63 seconds
Started Jul 06 05:32:04 PM PDT 24
Finished Jul 06 05:33:59 PM PDT 24
Peak memory 249416 kb
Host smart-73c12a8d-c770-4053-b3d8-7a45768e522d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561538168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2561538168
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3398809043
Short name T687
Test name
Test status
Simulation time 618189605 ps
CPU time 19.48 seconds
Started Jul 06 05:32:06 PM PDT 24
Finished Jul 06 05:32:25 PM PDT 24
Peak memory 257348 kb
Host smart-878bc856-f0b7-4004-a458-a3419d9a2d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33988
09043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3398809043
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.504243592
Short name T639
Test name
Test status
Simulation time 846952691 ps
CPU time 19.54 seconds
Started Jul 06 05:32:06 PM PDT 24
Finished Jul 06 05:32:25 PM PDT 24
Peak memory 248428 kb
Host smart-13413cbd-b2cf-45a9-9020-9da14ae764fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50424
3592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.504243592
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1112832233
Short name T283
Test name
Test status
Simulation time 3145849368 ps
CPU time 27.61 seconds
Started Jul 06 05:32:08 PM PDT 24
Finished Jul 06 05:32:36 PM PDT 24
Peak memory 257248 kb
Host smart-0efe7826-278f-4db6-ae05-44af50943aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128
32233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1112832233
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1540620627
Short name T355
Test name
Test status
Simulation time 432752111 ps
CPU time 20.3 seconds
Started Jul 06 05:32:07 PM PDT 24
Finished Jul 06 05:32:28 PM PDT 24
Peak memory 256628 kb
Host smart-3eed300d-b633-4b37-9c79-75316653c156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15406
20627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1540620627
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3388121322
Short name T535
Test name
Test status
Simulation time 32018144561 ps
CPU time 1798.86 seconds
Started Jul 06 05:32:07 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 290140 kb
Host smart-6a2060e8-fe32-49ec-896d-0629541008a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388121322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3388121322
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1829138347
Short name T661
Test name
Test status
Simulation time 52615022999 ps
CPU time 3167.16 seconds
Started Jul 06 05:32:13 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 290320 kb
Host smart-ca50ca25-3550-4936-ba0b-0207c82b81c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829138347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1829138347
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3929328442
Short name T246
Test name
Test status
Simulation time 1069407701 ps
CPU time 89.41 seconds
Started Jul 06 05:32:09 PM PDT 24
Finished Jul 06 05:33:39 PM PDT 24
Peak memory 256992 kb
Host smart-2433f235-9e95-46bf-a80c-bb9e65bec673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39293
28442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3929328442
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2020619953
Short name T16
Test name
Test status
Simulation time 518390245 ps
CPU time 14.94 seconds
Started Jul 06 05:32:08 PM PDT 24
Finished Jul 06 05:32:24 PM PDT 24
Peak memory 248764 kb
Host smart-4c37402b-8f59-46c4-bc91-1dd1e404e57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
19953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2020619953
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1634759704
Short name T322
Test name
Test status
Simulation time 48112468921 ps
CPU time 1283.29 seconds
Started Jul 06 05:32:12 PM PDT 24
Finished Jul 06 05:53:35 PM PDT 24
Peak memory 283216 kb
Host smart-d4751f91-f0eb-4779-a106-b2f166a01994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634759704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1634759704
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4137481826
Short name T243
Test name
Test status
Simulation time 8654535801 ps
CPU time 691.28 seconds
Started Jul 06 05:32:13 PM PDT 24
Finished Jul 06 05:43:45 PM PDT 24
Peak memory 272248 kb
Host smart-6408fbff-586e-4843-bd66-d60f13653a31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137481826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4137481826
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.202730658
Short name T263
Test name
Test status
Simulation time 20895893248 ps
CPU time 225.12 seconds
Started Jul 06 05:32:11 PM PDT 24
Finished Jul 06 05:35:57 PM PDT 24
Peak memory 249396 kb
Host smart-b5819c99-c5a9-4046-aac3-427a31633970
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202730658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.202730658
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2850957119
Short name T365
Test name
Test status
Simulation time 1881921834 ps
CPU time 59.34 seconds
Started Jul 06 05:32:06 PM PDT 24
Finished Jul 06 05:33:06 PM PDT 24
Peak memory 257184 kb
Host smart-10d2cb8d-0541-4ed9-8c81-6c8fbfb1c990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28509
57119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2850957119
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1786672443
Short name T490
Test name
Test status
Simulation time 3408838568 ps
CPU time 49.74 seconds
Started Jul 06 05:32:10 PM PDT 24
Finished Jul 06 05:33:00 PM PDT 24
Peak memory 249216 kb
Host smart-21fe1ddc-b428-4973-b0be-b780213139ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866
72443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1786672443
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2068353538
Short name T264
Test name
Test status
Simulation time 407452145 ps
CPU time 12.21 seconds
Started Jul 06 05:32:13 PM PDT 24
Finished Jul 06 05:32:25 PM PDT 24
Peak memory 256372 kb
Host smart-0370b1ca-1d9e-4bc3-8693-6747bc181af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20683
53538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2068353538
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3346144966
Short name T686
Test name
Test status
Simulation time 3894502361 ps
CPU time 63.72 seconds
Started Jul 06 05:32:04 PM PDT 24
Finished Jul 06 05:33:08 PM PDT 24
Peak memory 257568 kb
Host smart-be71d795-f2d1-4d51-bdf4-e9c9e0ba450f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
44966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3346144966
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.253338189
Short name T679
Test name
Test status
Simulation time 204815735071 ps
CPU time 6220.59 seconds
Started Jul 06 05:32:12 PM PDT 24
Finished Jul 06 07:15:54 PM PDT 24
Peak memory 363520 kb
Host smart-b242c2be-9e3e-4e37-b0ed-0ae5de1d277b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253338189 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.253338189
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.701312608
Short name T534
Test name
Test status
Simulation time 41506385394 ps
CPU time 2391.29 seconds
Started Jul 06 05:32:13 PM PDT 24
Finished Jul 06 06:12:05 PM PDT 24
Peak memory 290124 kb
Host smart-c8e2a2cf-1cd1-403d-bd29-6a50f317b82c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701312608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.701312608
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1984912735
Short name T50
Test name
Test status
Simulation time 16377091896 ps
CPU time 208.61 seconds
Started Jul 06 05:32:10 PM PDT 24
Finished Jul 06 05:35:39 PM PDT 24
Peak memory 257488 kb
Host smart-6fdcf833-61c3-46c5-81d7-f3d2769c3629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19849
12735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1984912735
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2180216350
Short name T472
Test name
Test status
Simulation time 828818600 ps
CPU time 29.1 seconds
Started Jul 06 05:32:14 PM PDT 24
Finished Jul 06 05:32:43 PM PDT 24
Peak memory 257040 kb
Host smart-ce7e391d-3406-4598-bde1-6eecef21afae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21802
16350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2180216350
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.567665979
Short name T705
Test name
Test status
Simulation time 91135074253 ps
CPU time 1631.26 seconds
Started Jul 06 05:32:10 PM PDT 24
Finished Jul 06 05:59:21 PM PDT 24
Peak memory 289404 kb
Host smart-164c517c-a42d-4c57-bc19-918cf8a7327d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567665979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.567665979
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2123651708
Short name T463
Test name
Test status
Simulation time 19941887828 ps
CPU time 1128.08 seconds
Started Jul 06 05:32:11 PM PDT 24
Finished Jul 06 05:50:59 PM PDT 24
Peak memory 273488 kb
Host smart-d8fad9e6-3fe9-40fd-bd24-56542a9bdb70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123651708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2123651708
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.284390012
Short name T318
Test name
Test status
Simulation time 40731070552 ps
CPU time 292.95 seconds
Started Jul 06 05:32:13 PM PDT 24
Finished Jul 06 05:37:06 PM PDT 24
Peak memory 256308 kb
Host smart-203d0217-8011-48df-ae1d-54c849cf2bfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284390012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.284390012
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.257612655
Short name T596
Test name
Test status
Simulation time 116669041 ps
CPU time 8.1 seconds
Started Jul 06 05:32:11 PM PDT 24
Finished Jul 06 05:32:19 PM PDT 24
Peak memory 249276 kb
Host smart-a8a35657-793b-48f7-9c25-3899547a6f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25761
2655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.257612655
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3438709491
Short name T486
Test name
Test status
Simulation time 460181867 ps
CPU time 25.06 seconds
Started Jul 06 05:32:11 PM PDT 24
Finished Jul 06 05:32:36 PM PDT 24
Peak memory 248740 kb
Host smart-037b1a6a-23f4-4fe5-b0c4-7cc1ad35bfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34387
09491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3438709491
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.924039122
Short name T493
Test name
Test status
Simulation time 384473280 ps
CPU time 7.53 seconds
Started Jul 06 05:32:11 PM PDT 24
Finished Jul 06 05:32:18 PM PDT 24
Peak memory 252268 kb
Host smart-e71f1eec-8e2f-4964-b663-8db49da0258f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92403
9122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.924039122
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.345135782
Short name T626
Test name
Test status
Simulation time 93629302478 ps
CPU time 2886.1 seconds
Started Jul 06 05:32:12 PM PDT 24
Finished Jul 06 06:20:19 PM PDT 24
Peak memory 290260 kb
Host smart-30c49bbe-bd6a-4732-b81a-bb4b4f7f8b17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345135782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.345135782
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1364549090
Short name T560
Test name
Test status
Simulation time 62429577338 ps
CPU time 5977.43 seconds
Started Jul 06 05:32:14 PM PDT 24
Finished Jul 06 07:11:52 PM PDT 24
Peak memory 355184 kb
Host smart-b8070cc1-b671-4c42-bf06-2d67ab440730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364549090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1364549090
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2490073194
Short name T710
Test name
Test status
Simulation time 11211462969 ps
CPU time 154.36 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:34:49 PM PDT 24
Peak memory 257120 kb
Host smart-935a8acc-d878-4a71-b126-292e3ba489ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900
73194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2490073194
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.225087092
Short name T694
Test name
Test status
Simulation time 2226013259 ps
CPU time 41.59 seconds
Started Jul 06 05:32:17 PM PDT 24
Finished Jul 06 05:32:59 PM PDT 24
Peak memory 255840 kb
Host smart-3e206744-4b5d-49ad-b701-b948547fdcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508
7092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.225087092
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2380752675
Short name T331
Test name
Test status
Simulation time 37066033714 ps
CPU time 2291.73 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 06:10:28 PM PDT 24
Peak memory 288780 kb
Host smart-5a5dc565-d7ab-4f41-b577-1cacb4273671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380752675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2380752675
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2401599133
Short name T675
Test name
Test status
Simulation time 44475454024 ps
CPU time 1188.35 seconds
Started Jul 06 05:32:18 PM PDT 24
Finished Jul 06 05:52:07 PM PDT 24
Peak memory 272720 kb
Host smart-b9b03488-6743-4008-9a9d-a5d23447eaaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401599133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2401599133
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2510583284
Short name T540
Test name
Test status
Simulation time 18848526397 ps
CPU time 383 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:38:39 PM PDT 24
Peak memory 255872 kb
Host smart-c0f9ba42-5c3e-41ce-aa74-71b50c9d7bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510583284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2510583284
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1100563898
Short name T426
Test name
Test status
Simulation time 2761771740 ps
CPU time 50.34 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:33:06 PM PDT 24
Peak memory 256972 kb
Host smart-677257c7-5cb9-438b-8af6-36407815b9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11005
63898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1100563898
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3556520902
Short name T265
Test name
Test status
Simulation time 435446834 ps
CPU time 43.71 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:32:59 PM PDT 24
Peak memory 250112 kb
Host smart-c88cb399-ad4f-42c6-930a-a60cf62ca070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35565
20902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3556520902
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4286577758
Short name T379
Test name
Test status
Simulation time 42785386 ps
CPU time 4.3 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:32:19 PM PDT 24
Peak memory 240628 kb
Host smart-07662798-1898-407e-babf-79d529d8f60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42865
77758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4286577758
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4194258859
Short name T689
Test name
Test status
Simulation time 129955674 ps
CPU time 8.46 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:32:24 PM PDT 24
Peak memory 252472 kb
Host smart-5c859b8a-c904-4edc-a68a-c3602341e6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41942
58859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4194258859
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4007685023
Short name T668
Test name
Test status
Simulation time 16348378008 ps
CPU time 295.97 seconds
Started Jul 06 05:32:18 PM PDT 24
Finished Jul 06 05:37:14 PM PDT 24
Peak memory 257492 kb
Host smart-33bc0920-3c41-47e0-acf9-b1f7330e732c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007685023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4007685023
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.838188282
Short name T13
Test name
Test status
Simulation time 15815196177 ps
CPU time 1111.78 seconds
Started Jul 06 05:32:24 PM PDT 24
Finished Jul 06 05:50:56 PM PDT 24
Peak memory 290248 kb
Host smart-c8d6477b-276f-4681-ba2f-de8a11981ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838188282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.838188282
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3071726485
Short name T588
Test name
Test status
Simulation time 3711928147 ps
CPU time 51.11 seconds
Started Jul 06 05:32:20 PM PDT 24
Finished Jul 06 05:33:11 PM PDT 24
Peak memory 257036 kb
Host smart-313db6aa-b1e0-4dc4-b3ab-f127b246053c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717
26485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3071726485
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1560552537
Short name T21
Test name
Test status
Simulation time 2976264292 ps
CPU time 48.37 seconds
Started Jul 06 05:32:19 PM PDT 24
Finished Jul 06 05:33:08 PM PDT 24
Peak memory 249240 kb
Host smart-ce975f25-14ad-42d8-ac19-6a89bc11e2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15605
52537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1560552537
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1447763006
Short name T590
Test name
Test status
Simulation time 37279423472 ps
CPU time 1998.77 seconds
Started Jul 06 05:32:24 PM PDT 24
Finished Jul 06 06:05:43 PM PDT 24
Peak memory 273744 kb
Host smart-5327bdde-f07f-4b37-a9e0-935195f8fd91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447763006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1447763006
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1870581096
Short name T425
Test name
Test status
Simulation time 146637960111 ps
CPU time 1797.75 seconds
Started Jul 06 05:32:19 PM PDT 24
Finished Jul 06 06:02:17 PM PDT 24
Peak memory 289280 kb
Host smart-4673877b-30ac-4404-8a4a-d1ee2084f9a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870581096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1870581096
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2264261067
Short name T312
Test name
Test status
Simulation time 7755645305 ps
CPU time 310.94 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:37:38 PM PDT 24
Peak memory 249388 kb
Host smart-9ead94a8-4db4-47b6-a434-1cc09dcc861b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264261067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2264261067
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.182711637
Short name T462
Test name
Test status
Simulation time 81482313 ps
CPU time 11.73 seconds
Started Jul 06 05:32:21 PM PDT 24
Finished Jul 06 05:32:33 PM PDT 24
Peak memory 249236 kb
Host smart-e30b1886-e80d-4b93-b71c-e4e48629b387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18271
1637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.182711637
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1408396429
Short name T461
Test name
Test status
Simulation time 1592975382 ps
CPU time 29.34 seconds
Started Jul 06 05:32:15 PM PDT 24
Finished Jul 06 05:32:45 PM PDT 24
Peak memory 248708 kb
Host smart-90225097-42f3-47ee-b4a3-88b7f5417281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14083
96429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1408396429
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1287015767
Short name T513
Test name
Test status
Simulation time 126628260 ps
CPU time 8.85 seconds
Started Jul 06 05:32:22 PM PDT 24
Finished Jul 06 05:32:31 PM PDT 24
Peak memory 255264 kb
Host smart-14bfc72d-827a-4da3-a7fe-69c8d0cf1771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
15767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1287015767
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2043053198
Short name T470
Test name
Test status
Simulation time 324967377 ps
CPU time 34.98 seconds
Started Jul 06 05:32:19 PM PDT 24
Finished Jul 06 05:32:54 PM PDT 24
Peak memory 257396 kb
Host smart-b9b704ff-1828-4fcb-8891-5b37442d7cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20430
53198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2043053198
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.386672306
Short name T248
Test name
Test status
Simulation time 1552524346 ps
CPU time 94.64 seconds
Started Jul 06 05:32:20 PM PDT 24
Finished Jul 06 05:33:54 PM PDT 24
Peak memory 257496 kb
Host smart-8096f18c-3eca-4ef8-823e-887b0e5d5df0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386672306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.386672306
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2775585793
Short name T102
Test name
Test status
Simulation time 515494742486 ps
CPU time 3931.12 seconds
Started Jul 06 05:32:21 PM PDT 24
Finished Jul 06 06:37:53 PM PDT 24
Peak memory 305772 kb
Host smart-67494d8e-2f23-403c-b72f-aa718224ff93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775585793 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2775585793
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.55947563
Short name T227
Test name
Test status
Simulation time 89161671289 ps
CPU time 1372.21 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 05:55:19 PM PDT 24
Peak memory 272640 kb
Host smart-7c9c7677-8299-4575-bfe2-f497d035a681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55947563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.55947563
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3458546053
Short name T48
Test name
Test status
Simulation time 5908622119 ps
CPU time 335.47 seconds
Started Jul 06 05:32:20 PM PDT 24
Finished Jul 06 05:37:56 PM PDT 24
Peak memory 257432 kb
Host smart-82a8abee-db5a-421d-87a2-6048330d7623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
46053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3458546053
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2337262447
Short name T238
Test name
Test status
Simulation time 1608797605 ps
CPU time 54.14 seconds
Started Jul 06 05:32:20 PM PDT 24
Finished Jul 06 05:33:15 PM PDT 24
Peak memory 256888 kb
Host smart-f7594baa-6dad-458a-84a5-ae750f935d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23372
62447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2337262447
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.781150123
Short name T603
Test name
Test status
Simulation time 59348632804 ps
CPU time 1941.13 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 06:04:48 PM PDT 24
Peak memory 282108 kb
Host smart-b97bf190-6d27-4663-afbd-6e5df59da724
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781150123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.781150123
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1179145605
Short name T376
Test name
Test status
Simulation time 204696715030 ps
CPU time 2926.09 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 06:21:14 PM PDT 24
Peak memory 289784 kb
Host smart-18cdc285-d026-427f-af58-6e9f4dd08c5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179145605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1179145605
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3150315966
Short name T320
Test name
Test status
Simulation time 24035736179 ps
CPU time 156.24 seconds
Started Jul 06 05:32:28 PM PDT 24
Finished Jul 06 05:35:04 PM PDT 24
Peak memory 248308 kb
Host smart-87e32224-5ddd-4ef3-bb0f-bd009dd39d0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150315966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3150315966
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1822125988
Short name T522
Test name
Test status
Simulation time 13905824010 ps
CPU time 66 seconds
Started Jul 06 05:32:24 PM PDT 24
Finished Jul 06 05:33:31 PM PDT 24
Peak memory 257044 kb
Host smart-faff555f-ab49-4390-887f-71cf5ea5d2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18221
25988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1822125988
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.885825483
Short name T658
Test name
Test status
Simulation time 772829896 ps
CPU time 48.23 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:33:15 PM PDT 24
Peak memory 248952 kb
Host smart-347894b6-6ae9-42fb-b61e-19e1b23d7570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88582
5483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.885825483
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.574370730
Short name T454
Test name
Test status
Simulation time 671267895 ps
CPU time 13.61 seconds
Started Jul 06 05:32:21 PM PDT 24
Finished Jul 06 05:32:35 PM PDT 24
Peak memory 249156 kb
Host smart-1ad91a45-91b5-44cf-9dd7-bed629d6b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57437
0730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.574370730
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2603209289
Short name T438
Test name
Test status
Simulation time 231172552 ps
CPU time 5.14 seconds
Started Jul 06 05:32:21 PM PDT 24
Finished Jul 06 05:32:26 PM PDT 24
Peak memory 251516 kb
Host smart-af17feaf-8863-4bd8-9cb5-985c6d32c4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
09289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2603209289
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3260820317
Short name T441
Test name
Test status
Simulation time 22549533862 ps
CPU time 1332.59 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:54:39 PM PDT 24
Peak memory 288944 kb
Host smart-b5c49605-6633-411e-8c6d-c3721bc4bdb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260820317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3260820317
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1051098495
Short name T257
Test name
Test status
Simulation time 19850035383 ps
CPU time 1314.79 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 05:54:22 PM PDT 24
Peak memory 272580 kb
Host smart-67eecd51-7cbf-4199-af1d-2eb4b533b78e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051098495 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1051098495
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4193199817
Short name T297
Test name
Test status
Simulation time 31831587836 ps
CPU time 1953.14 seconds
Started Jul 06 05:32:28 PM PDT 24
Finished Jul 06 06:05:01 PM PDT 24
Peak memory 290376 kb
Host smart-6a33601f-e06c-4d8e-ba15-2e043204bc74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193199817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4193199817
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.4028987990
Short name T450
Test name
Test status
Simulation time 22097903863 ps
CPU time 314.32 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 05:37:42 PM PDT 24
Peak memory 257140 kb
Host smart-134e5369-c385-4c95-a36d-76fbe7260b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40289
87990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4028987990
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.767757138
Short name T85
Test name
Test status
Simulation time 90408441 ps
CPU time 7.02 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:32:33 PM PDT 24
Peak memory 249220 kb
Host smart-766a093e-ef24-4afa-a516-84d594f34426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76775
7138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.767757138
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3656392356
Short name T634
Test name
Test status
Simulation time 118628734554 ps
CPU time 3190.86 seconds
Started Jul 06 05:32:25 PM PDT 24
Finished Jul 06 06:25:37 PM PDT 24
Peak memory 289556 kb
Host smart-c34379ac-9b9e-4f08-b066-3b2973477332
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656392356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3656392356
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2821996072
Short name T647
Test name
Test status
Simulation time 14361339811 ps
CPU time 1448.63 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 05:56:36 PM PDT 24
Peak memory 282240 kb
Host smart-789cb0fe-a1b0-421f-9cdc-345a7cada8e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821996072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2821996072
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1387870167
Short name T302
Test name
Test status
Simulation time 21816423587 ps
CPU time 479.75 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:40:26 PM PDT 24
Peak memory 249260 kb
Host smart-42c02be9-67c9-42b8-a187-f8697d6d5797
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387870167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1387870167
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4140402576
Short name T361
Test name
Test status
Simulation time 256535616 ps
CPU time 26.08 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 05:32:53 PM PDT 24
Peak memory 256816 kb
Host smart-4329fe6b-ac8d-461a-814f-8b9308b873b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
02576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4140402576
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3482948139
Short name T482
Test name
Test status
Simulation time 1273700141 ps
CPU time 23.35 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:32:49 PM PDT 24
Peak memory 248784 kb
Host smart-77dce025-af08-44d1-8b46-9352aa245cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34829
48139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3482948139
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1087911443
Short name T448
Test name
Test status
Simulation time 358717141 ps
CPU time 25.57 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:32:52 PM PDT 24
Peak memory 257440 kb
Host smart-748fbf87-ce0c-4fd4-8b60-f78b5de79862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10879
11443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1087911443
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2596865902
Short name T688
Test name
Test status
Simulation time 19891628801 ps
CPU time 63.61 seconds
Started Jul 06 05:32:26 PM PDT 24
Finished Jul 06 05:33:30 PM PDT 24
Peak memory 257356 kb
Host smart-e9eb163c-4089-4e64-b453-8ef6f330ac63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
65902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2596865902
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.254092359
Short name T274
Test name
Test status
Simulation time 20384774687 ps
CPU time 1794.3 seconds
Started Jul 06 05:32:28 PM PDT 24
Finished Jul 06 06:02:22 PM PDT 24
Peak memory 298568 kb
Host smart-d7bb2308-c792-4b14-aa90-5c4496115bd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254092359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.254092359
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.847398984
Short name T59
Test name
Test status
Simulation time 254707718703 ps
CPU time 3826.57 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 06:36:14 PM PDT 24
Peak memory 306860 kb
Host smart-8ef83c37-dbe9-413e-87dd-e5943de4d92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847398984 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.847398984
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2585064826
Short name T202
Test name
Test status
Simulation time 126366943 ps
CPU time 3.45 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:30:58 PM PDT 24
Peak memory 249600 kb
Host smart-e8c5a5a3-3a59-4081-b397-6612f6c5b1e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2585064826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2585064826
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2907972726
Short name T96
Test name
Test status
Simulation time 15160130590 ps
CPU time 1457.66 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:55:11 PM PDT 24
Peak memory 290064 kb
Host smart-69f3f999-2e8a-48c5-9a3a-a74ebed61836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907972726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2907972726
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3554700123
Short name T552
Test name
Test status
Simulation time 676625221 ps
CPU time 9.84 seconds
Started Jul 06 05:30:50 PM PDT 24
Finished Jul 06 05:31:01 PM PDT 24
Peak memory 249192 kb
Host smart-4fb768ed-d8ee-4d67-97d9-437d862c6344
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3554700123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3554700123
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3904301892
Short name T222
Test name
Test status
Simulation time 1362318767 ps
CPU time 140.52 seconds
Started Jul 06 05:31:24 PM PDT 24
Finished Jul 06 05:33:45 PM PDT 24
Peak memory 257376 kb
Host smart-c11b1351-8980-4581-a856-39d4e5bae416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
01892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3904301892
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.685567259
Short name T638
Test name
Test status
Simulation time 931851032 ps
CPU time 54.08 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 05:32:05 PM PDT 24
Peak memory 249048 kb
Host smart-5a2440bf-c40b-4652-8455-589911a71707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68556
7259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.685567259
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1921002061
Short name T40
Test name
Test status
Simulation time 49903707990 ps
CPU time 1157.43 seconds
Started Jul 06 05:30:48 PM PDT 24
Finished Jul 06 05:50:06 PM PDT 24
Peak memory 282216 kb
Host smart-e0b28a21-b167-47ad-bfd8-a4cab90fe50f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921002061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1921002061
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3930291354
Short name T597
Test name
Test status
Simulation time 69342951300 ps
CPU time 1388.17 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:54:01 PM PDT 24
Peak memory 290172 kb
Host smart-b0218b36-c05c-4af9-8545-6dc9a62dc604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930291354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3930291354
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2766932849
Short name T272
Test name
Test status
Simulation time 18694004956 ps
CPU time 382.14 seconds
Started Jul 06 05:31:03 PM PDT 24
Finished Jul 06 05:37:25 PM PDT 24
Peak memory 248232 kb
Host smart-61e0f2b6-8472-4a7a-b05f-498761f0844e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766932849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2766932849
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3584451914
Short name T569
Test name
Test status
Simulation time 547455788 ps
CPU time 44.16 seconds
Started Jul 06 05:31:07 PM PDT 24
Finished Jul 06 05:31:52 PM PDT 24
Peak memory 249344 kb
Host smart-6d9d77bb-5972-4c5d-b6ed-9e1bb248b00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35844
51914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3584451914
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3237391873
Short name T55
Test name
Test status
Simulation time 357668465 ps
CPU time 33.93 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:31:23 PM PDT 24
Peak memory 257460 kb
Host smart-a6d90a95-8de4-4d0c-b0ac-34c753b01445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373
91873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3237391873
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.520771761
Short name T34
Test name
Test status
Simulation time 347844400 ps
CPU time 22.37 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:31:17 PM PDT 24
Peak memory 277508 kb
Host smart-d6d84418-4a74-4502-843a-d38872405047
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=520771761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.520771761
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3348883355
Short name T592
Test name
Test status
Simulation time 65651581 ps
CPU time 7.52 seconds
Started Jul 06 05:30:49 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 249580 kb
Host smart-fa9dafa7-7489-4c75-9607-4dd42d30e5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33488
83355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3348883355
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.29810546
Short name T220
Test name
Test status
Simulation time 104151971 ps
CPU time 10.41 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 05:31:08 PM PDT 24
Peak memory 249296 kb
Host smart-d43b33a4-343e-4e01-a65a-e0281fadb56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29810
546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.29810546
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3373351057
Short name T258
Test name
Test status
Simulation time 62772926429 ps
CPU time 3370.79 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 06:27:04 PM PDT 24
Peak memory 290356 kb
Host smart-27a8fca5-5dd9-4f21-9483-921ffbe19455
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373351057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3373351057
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2836603147
Short name T671
Test name
Test status
Simulation time 58563577262 ps
CPU time 3960.18 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 06:37:00 PM PDT 24
Peak memory 302044 kb
Host smart-f0fe54b9-ba97-42fa-a0ef-ce7b2de682f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836603147 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2836603147
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1852147152
Short name T587
Test name
Test status
Simulation time 174273797777 ps
CPU time 2614.86 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 06:16:02 PM PDT 24
Peak memory 286316 kb
Host smart-faa1e4bc-7169-4571-921e-f58d38bdb071
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852147152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1852147152
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1625793028
Short name T273
Test name
Test status
Simulation time 2423230473 ps
CPU time 98.06 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 05:34:07 PM PDT 24
Peak memory 257556 kb
Host smart-1fcdd7fd-e8d5-4af1-a10f-9b5f0bedca12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16257
93028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1625793028
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2777766282
Short name T87
Test name
Test status
Simulation time 1135501812 ps
CPU time 65.63 seconds
Started Jul 06 05:32:31 PM PDT 24
Finished Jul 06 05:33:37 PM PDT 24
Peak memory 257004 kb
Host smart-26189b36-747f-4887-a5cf-f9d69c612a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27777
66282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2777766282
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3904727253
Short name T229
Test name
Test status
Simulation time 12787863758 ps
CPU time 1096.38 seconds
Started Jul 06 05:32:30 PM PDT 24
Finished Jul 06 05:50:47 PM PDT 24
Peak memory 273248 kb
Host smart-eb88905a-1fb5-430b-bb29-4f856167244b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904727253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3904727253
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3732019190
Short name T413
Test name
Test status
Simulation time 51571940583 ps
CPU time 2890.35 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 06:20:40 PM PDT 24
Peak memory 289684 kb
Host smart-20679d4e-b80d-44c6-8cd0-fc344e6fff98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732019190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3732019190
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.696679688
Short name T310
Test name
Test status
Simulation time 38541783933 ps
CPU time 397.52 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 05:39:06 PM PDT 24
Peak memory 249352 kb
Host smart-31d33c2a-594c-4084-9790-3cbeb7732eb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696679688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.696679688
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1615573363
Short name T543
Test name
Test status
Simulation time 611177775 ps
CPU time 35.28 seconds
Started Jul 06 05:32:28 PM PDT 24
Finished Jul 06 05:33:03 PM PDT 24
Peak memory 249292 kb
Host smart-ce1372a1-9496-4f90-9150-ba00cd5bdd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16155
73363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1615573363
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3194187575
Short name T121
Test name
Test status
Simulation time 207474128 ps
CPU time 21.21 seconds
Started Jul 06 05:32:31 PM PDT 24
Finished Jul 06 05:32:53 PM PDT 24
Peak memory 248612 kb
Host smart-a44902fb-c0d5-4758-a25b-fdbab63de747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941
87575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3194187575
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.860235829
Short name T27
Test name
Test status
Simulation time 544166483 ps
CPU time 21.45 seconds
Started Jul 06 05:32:30 PM PDT 24
Finished Jul 06 05:32:52 PM PDT 24
Peak memory 256892 kb
Host smart-5e68edcd-2a2f-41fd-a909-406032024498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86023
5829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.860235829
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2555269227
Short name T116
Test name
Test status
Simulation time 240481750 ps
CPU time 17.43 seconds
Started Jul 06 05:32:27 PM PDT 24
Finished Jul 06 05:32:45 PM PDT 24
Peak memory 254460 kb
Host smart-5a9bcd9e-033a-4dfd-8671-0f82ead26e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552
69227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2555269227
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2108812251
Short name T649
Test name
Test status
Simulation time 54058716637 ps
CPU time 1128.97 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 05:51:18 PM PDT 24
Peak memory 283764 kb
Host smart-ec0073a3-1a7c-4a1f-82dd-c5c646725134
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108812251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2108812251
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.248783997
Short name T64
Test name
Test status
Simulation time 304785292165 ps
CPU time 5399.29 seconds
Started Jul 06 05:32:30 PM PDT 24
Finished Jul 06 07:02:30 PM PDT 24
Peak memory 322716 kb
Host smart-310d7812-f1f4-4827-96f9-27c523a47633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248783997 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.248783997
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3716291945
Short name T268
Test name
Test status
Simulation time 11210164771 ps
CPU time 561.79 seconds
Started Jul 06 05:32:30 PM PDT 24
Finished Jul 06 05:41:52 PM PDT 24
Peak memory 265784 kb
Host smart-1dd3dfca-dbad-4845-a343-ba38306faf2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716291945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3716291945
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.4125292643
Short name T517
Test name
Test status
Simulation time 836925001 ps
CPU time 66.2 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 05:33:35 PM PDT 24
Peak memory 257460 kb
Host smart-d5e454da-61db-4e4d-8382-2cd680f218d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41252
92643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.4125292643
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1204147492
Short name T475
Test name
Test status
Simulation time 229608706 ps
CPU time 5.67 seconds
Started Jul 06 05:32:30 PM PDT 24
Finished Jul 06 05:32:36 PM PDT 24
Peak memory 249300 kb
Host smart-6221c49d-88a5-40b9-b50e-cab263720669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12041
47492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1204147492
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3510326881
Short name T619
Test name
Test status
Simulation time 21872897710 ps
CPU time 1638.41 seconds
Started Jul 06 05:32:36 PM PDT 24
Finished Jul 06 05:59:55 PM PDT 24
Peak memory 289480 kb
Host smart-48110cfa-dc3d-4ec9-83a2-9917bd5082b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510326881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3510326881
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3119288246
Short name T387
Test name
Test status
Simulation time 26832501855 ps
CPU time 1852.89 seconds
Started Jul 06 05:32:34 PM PDT 24
Finished Jul 06 06:03:27 PM PDT 24
Peak memory 282128 kb
Host smart-b0e6ac84-3618-4222-84a3-92e63bf2bbc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119288246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3119288246
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4063121469
Short name T309
Test name
Test status
Simulation time 7663301098 ps
CPU time 318.69 seconds
Started Jul 06 05:32:31 PM PDT 24
Finished Jul 06 05:37:50 PM PDT 24
Peak memory 249412 kb
Host smart-34c4f801-8bc6-4dbc-84cc-3b0e7f1d7cf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063121469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4063121469
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1492708288
Short name T622
Test name
Test status
Simulation time 323241430 ps
CPU time 7.12 seconds
Started Jul 06 05:32:32 PM PDT 24
Finished Jul 06 05:32:39 PM PDT 24
Peak memory 249312 kb
Host smart-c4494798-09bc-43cc-840e-eadded100961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
08288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1492708288
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2174826304
Short name T81
Test name
Test status
Simulation time 85227067 ps
CPU time 7.25 seconds
Started Jul 06 05:32:30 PM PDT 24
Finished Jul 06 05:32:38 PM PDT 24
Peak memory 249248 kb
Host smart-93692a86-f0fe-4a2c-9626-512262ff3eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
26304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2174826304
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2669796691
Short name T276
Test name
Test status
Simulation time 616595020 ps
CPU time 16.52 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 05:32:46 PM PDT 24
Peak memory 249252 kb
Host smart-35680bb4-9e25-4a69-9229-6513af1dbd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26697
96691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2669796691
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3196991716
Short name T390
Test name
Test status
Simulation time 286059296 ps
CPU time 21.99 seconds
Started Jul 06 05:32:29 PM PDT 24
Finished Jul 06 05:32:52 PM PDT 24
Peak memory 257228 kb
Host smart-9f06a7e6-3076-4db3-a646-43b515a2056b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31969
91716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3196991716
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1278739389
Short name T111
Test name
Test status
Simulation time 8890540899 ps
CPU time 459.19 seconds
Started Jul 06 05:32:34 PM PDT 24
Finished Jul 06 05:40:13 PM PDT 24
Peak memory 267912 kb
Host smart-5e34a7b8-e588-442c-b0e4-588276c9f558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278739389 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1278739389
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2007842376
Short name T256
Test name
Test status
Simulation time 28856130435 ps
CPU time 1721.23 seconds
Started Jul 06 05:32:34 PM PDT 24
Finished Jul 06 06:01:16 PM PDT 24
Peak memory 284292 kb
Host smart-2b3d5837-159f-4d61-a51b-4ce4dfb18b4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007842376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2007842376
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1764094416
Short name T412
Test name
Test status
Simulation time 12955978645 ps
CPU time 182.92 seconds
Started Jul 06 05:32:36 PM PDT 24
Finished Jul 06 05:35:39 PM PDT 24
Peak memory 257096 kb
Host smart-3ffd59aa-f012-4ec6-98f5-a430284947e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17640
94416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1764094416
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.166511499
Short name T623
Test name
Test status
Simulation time 3244648638 ps
CPU time 51.15 seconds
Started Jul 06 05:32:36 PM PDT 24
Finished Jul 06 05:33:27 PM PDT 24
Peak memory 257004 kb
Host smart-fe9cdd39-56a7-44c5-a9ec-7afb90460faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16651
1499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.166511499
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1244862722
Short name T665
Test name
Test status
Simulation time 19811562849 ps
CPU time 1189.45 seconds
Started Jul 06 05:32:34 PM PDT 24
Finished Jul 06 05:52:24 PM PDT 24
Peak memory 273128 kb
Host smart-7736babd-7fcb-44f8-8399-27db8f4ec8fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244862722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1244862722
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.612005997
Short name T251
Test name
Test status
Simulation time 34583629818 ps
CPU time 1854.03 seconds
Started Jul 06 05:32:33 PM PDT 24
Finished Jul 06 06:03:27 PM PDT 24
Peak memory 273876 kb
Host smart-53de40f9-e6e6-48f8-83f4-1f4d5a24aa0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612005997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.612005997
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2320240134
Short name T321
Test name
Test status
Simulation time 10813993859 ps
CPU time 111.68 seconds
Started Jul 06 05:32:35 PM PDT 24
Finished Jul 06 05:34:27 PM PDT 24
Peak memory 249220 kb
Host smart-97ac0bfd-4af0-47e1-bb4c-10badb578007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320240134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2320240134
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4222921067
Short name T250
Test name
Test status
Simulation time 1562683800 ps
CPU time 28 seconds
Started Jul 06 05:32:34 PM PDT 24
Finished Jul 06 05:33:03 PM PDT 24
Peak memory 249216 kb
Host smart-c7ea7b68-8826-4e6c-8953-514da933102e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42229
21067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4222921067
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4045188125
Short name T83
Test name
Test status
Simulation time 396493909 ps
CPU time 36.44 seconds
Started Jul 06 05:32:32 PM PDT 24
Finished Jul 06 05:33:08 PM PDT 24
Peak memory 248668 kb
Host smart-2dd63e65-e624-456d-b81f-64dce0106f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40451
88125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4045188125
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.752299845
Short name T632
Test name
Test status
Simulation time 283560461 ps
CPU time 19.09 seconds
Started Jul 06 05:32:35 PM PDT 24
Finished Jul 06 05:32:54 PM PDT 24
Peak memory 248584 kb
Host smart-835f8327-4750-410b-964d-c14974d10fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75229
9845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.752299845
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2474528425
Short name T690
Test name
Test status
Simulation time 311751718 ps
CPU time 21.46 seconds
Started Jul 06 05:32:35 PM PDT 24
Finished Jul 06 05:32:56 PM PDT 24
Peak memory 256028 kb
Host smart-b3839514-478b-40b5-ad5d-aa87f8b1b1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
28425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2474528425
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1933217591
Short name T60
Test name
Test status
Simulation time 42229438192 ps
CPU time 1004.31 seconds
Started Jul 06 05:32:41 PM PDT 24
Finished Jul 06 05:49:26 PM PDT 24
Peak memory 287764 kb
Host smart-e21ecfea-6ad1-45cf-a6c8-0192e5d9d4bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933217591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1933217591
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1017109550
Short name T504
Test name
Test status
Simulation time 155218348 ps
CPU time 5.71 seconds
Started Jul 06 05:32:39 PM PDT 24
Finished Jul 06 05:32:45 PM PDT 24
Peak memory 249324 kb
Host smart-1d05b6b6-68a0-4a69-9e33-f40034ebfd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10171
09550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1017109550
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3929623775
Short name T431
Test name
Test status
Simulation time 262765138758 ps
CPU time 1418.5 seconds
Started Jul 06 05:32:43 PM PDT 24
Finished Jul 06 05:56:22 PM PDT 24
Peak memory 273928 kb
Host smart-b0edb397-8895-4587-a21a-3f4488546f60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929623775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3929623775
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2237514594
Short name T609
Test name
Test status
Simulation time 7562940834 ps
CPU time 173.23 seconds
Started Jul 06 05:32:39 PM PDT 24
Finished Jul 06 05:35:32 PM PDT 24
Peak memory 249340 kb
Host smart-9bd80e78-0579-45a1-ab66-f1124bc27e56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237514594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2237514594
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1358100253
Short name T698
Test name
Test status
Simulation time 1035764633 ps
CPU time 58.92 seconds
Started Jul 06 05:32:38 PM PDT 24
Finished Jul 06 05:33:37 PM PDT 24
Peak memory 256300 kb
Host smart-bdce225a-0b4a-4983-a0de-0a9d4fcd6d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13581
00253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1358100253
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4253099706
Short name T611
Test name
Test status
Simulation time 1044775107 ps
CPU time 15.77 seconds
Started Jul 06 05:32:37 PM PDT 24
Finished Jul 06 05:32:53 PM PDT 24
Peak memory 249228 kb
Host smart-33284bc2-f413-40a0-813e-44618111307d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42530
99706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4253099706
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4038308112
Short name T358
Test name
Test status
Simulation time 777327097 ps
CPU time 53.37 seconds
Started Jul 06 05:32:38 PM PDT 24
Finished Jul 06 05:33:32 PM PDT 24
Peak memory 249256 kb
Host smart-4c6d239b-354b-46e8-9ef8-84af4ffbf27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40383
08112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4038308112
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.752356804
Short name T233
Test name
Test status
Simulation time 507513239291 ps
CPU time 6063.5 seconds
Started Jul 06 05:32:46 PM PDT 24
Finished Jul 06 07:13:51 PM PDT 24
Peak memory 323076 kb
Host smart-f74ba9fa-8ee4-4919-83a0-bca5b750453b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752356804 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.752356804
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1022484431
Short name T678
Test name
Test status
Simulation time 68577481454 ps
CPU time 1895.54 seconds
Started Jul 06 05:32:46 PM PDT 24
Finished Jul 06 06:04:22 PM PDT 24
Peak memory 286700 kb
Host smart-5160710a-f02e-423e-9770-d466662df4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022484431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1022484431
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1094069849
Short name T400
Test name
Test status
Simulation time 1452575826 ps
CPU time 88.37 seconds
Started Jul 06 05:32:45 PM PDT 24
Finished Jul 06 05:34:13 PM PDT 24
Peak memory 257032 kb
Host smart-ebbe83c2-b8c9-47e5-bfd1-6e38d23f26b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
69849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1094069849
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1365832463
Short name T554
Test name
Test status
Simulation time 476865355 ps
CPU time 27.42 seconds
Started Jul 06 05:32:44 PM PDT 24
Finished Jul 06 05:33:12 PM PDT 24
Peak memory 249652 kb
Host smart-89900240-200c-4af9-91ee-f304d3e2cc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13658
32463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1365832463
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4026605000
Short name T617
Test name
Test status
Simulation time 122436388482 ps
CPU time 1940.35 seconds
Started Jul 06 05:32:44 PM PDT 24
Finished Jul 06 06:05:05 PM PDT 24
Peak memory 285152 kb
Host smart-64f3537b-956e-457f-9889-c822f289c817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026605000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4026605000
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.558902201
Short name T418
Test name
Test status
Simulation time 238721746078 ps
CPU time 3389.89 seconds
Started Jul 06 05:32:44 PM PDT 24
Finished Jul 06 06:29:14 PM PDT 24
Peak memory 290320 kb
Host smart-64d4d7c7-2abd-47e9-a6fa-032a9618d898
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558902201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.558902201
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1996362318
Short name T303
Test name
Test status
Simulation time 44470659166 ps
CPU time 514.61 seconds
Started Jul 06 05:32:44 PM PDT 24
Finished Jul 06 05:41:19 PM PDT 24
Peak memory 249404 kb
Host smart-85b11552-704e-444c-9681-49496c230a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996362318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1996362318
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1540626285
Short name T378
Test name
Test status
Simulation time 1775910274 ps
CPU time 55.96 seconds
Started Jul 06 05:32:47 PM PDT 24
Finished Jul 06 05:33:43 PM PDT 24
Peak memory 256748 kb
Host smart-d84aeca3-dd26-4476-9937-97ad5c9064ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15406
26285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1540626285
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3052080317
Short name T674
Test name
Test status
Simulation time 579661666 ps
CPU time 37.78 seconds
Started Jul 06 05:32:47 PM PDT 24
Finished Jul 06 05:33:25 PM PDT 24
Peak memory 248736 kb
Host smart-de4d719a-edd9-4acb-a90f-f7f5cca23086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30520
80317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3052080317
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1530932612
Short name T118
Test name
Test status
Simulation time 1605849380 ps
CPU time 26.3 seconds
Started Jul 06 05:32:43 PM PDT 24
Finished Jul 06 05:33:10 PM PDT 24
Peak memory 256676 kb
Host smart-8b76a621-cae9-4648-8e97-1bf0cbcd95eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
32612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1530932612
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3780663823
Short name T533
Test name
Test status
Simulation time 3280989778 ps
CPU time 60.45 seconds
Started Jul 06 05:32:42 PM PDT 24
Finished Jul 06 05:33:43 PM PDT 24
Peak memory 249404 kb
Host smart-2caf972c-fa9e-47a3-9be2-2c83e56ee9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37806
63823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3780663823
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.50283016
Short name T477
Test name
Test status
Simulation time 7634881510 ps
CPU time 461.43 seconds
Started Jul 06 05:32:44 PM PDT 24
Finished Jul 06 05:40:25 PM PDT 24
Peak memory 257540 kb
Host smart-9518175c-feea-45cd-a5c9-a86e17b40f65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50283016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_hand
ler_stress_all.50283016
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.224795710
Short name T655
Test name
Test status
Simulation time 323168891080 ps
CPU time 8731.02 seconds
Started Jul 06 05:32:50 PM PDT 24
Finished Jul 06 07:58:22 PM PDT 24
Peak memory 371524 kb
Host smart-759586f7-926b-49db-b8b1-07bb6a6bef00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224795710 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.224795710
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.365239191
Short name T68
Test name
Test status
Simulation time 93838840757 ps
CPU time 1323.95 seconds
Started Jul 06 05:32:49 PM PDT 24
Finished Jul 06 05:54:54 PM PDT 24
Peak memory 273480 kb
Host smart-601d5131-0c74-4cf6-85cd-cebd9b20ceb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365239191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.365239191
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3308398031
Short name T451
Test name
Test status
Simulation time 4782907508 ps
CPU time 42.94 seconds
Started Jul 06 05:32:49 PM PDT 24
Finished Jul 06 05:33:33 PM PDT 24
Peak memory 250376 kb
Host smart-52d6ae8f-556d-4dc6-a6c0-69e29b222e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
98031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3308398031
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1839850928
Short name T357
Test name
Test status
Simulation time 1137284138 ps
CPU time 35.85 seconds
Started Jul 06 05:32:49 PM PDT 24
Finished Jul 06 05:33:25 PM PDT 24
Peak memory 256876 kb
Host smart-582c6545-d621-4d81-9dc0-6801f6023d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
50928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1839850928
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.269711937
Short name T333
Test name
Test status
Simulation time 20839632764 ps
CPU time 1015.62 seconds
Started Jul 06 05:32:49 PM PDT 24
Finished Jul 06 05:49:45 PM PDT 24
Peak memory 273824 kb
Host smart-b38f7f97-4481-4110-97bc-0e73a8906dbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269711937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.269711937
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1549560964
Short name T612
Test name
Test status
Simulation time 42539856295 ps
CPU time 973.96 seconds
Started Jul 06 05:32:48 PM PDT 24
Finished Jul 06 05:49:03 PM PDT 24
Peak memory 273784 kb
Host smart-c675a90f-26f6-4565-8f66-fca9425b099d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549560964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1549560964
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.747120441
Short name T317
Test name
Test status
Simulation time 3129040150 ps
CPU time 126.02 seconds
Started Jul 06 05:32:49 PM PDT 24
Finished Jul 06 05:34:55 PM PDT 24
Peak memory 249384 kb
Host smart-61a8c6b4-f8ad-4abc-9769-d54d1ee9423b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747120441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.747120441
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.97855737
Short name T593
Test name
Test status
Simulation time 7817588178 ps
CPU time 63.72 seconds
Started Jul 06 05:32:50 PM PDT 24
Finished Jul 06 05:33:54 PM PDT 24
Peak memory 256684 kb
Host smart-faa7c889-9eab-4fa1-9bd7-f043c0d3df63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97855
737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.97855737
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2136893374
Short name T411
Test name
Test status
Simulation time 189471564 ps
CPU time 13.9 seconds
Started Jul 06 05:32:49 PM PDT 24
Finished Jul 06 05:33:04 PM PDT 24
Peak memory 254816 kb
Host smart-f75412bb-1a08-47ba-b3ce-f473e7aec67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21368
93374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2136893374
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4236093456
Short name T82
Test name
Test status
Simulation time 3981575903 ps
CPU time 51.95 seconds
Started Jul 06 05:32:47 PM PDT 24
Finished Jul 06 05:33:40 PM PDT 24
Peak memory 257152 kb
Host smart-2339ac67-1f10-43e0-8a0d-5ca4acf54ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42360
93456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4236093456
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.914771716
Short name T693
Test name
Test status
Simulation time 851667336 ps
CPU time 58 seconds
Started Jul 06 05:32:48 PM PDT 24
Finished Jul 06 05:33:46 PM PDT 24
Peak memory 257436 kb
Host smart-f98f5179-d67e-4c22-9e06-98c823e930b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91477
1716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.914771716
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2449958500
Short name T449
Test name
Test status
Simulation time 21749415162 ps
CPU time 1302.66 seconds
Started Jul 06 05:32:48 PM PDT 24
Finished Jul 06 05:54:31 PM PDT 24
Peak memory 290304 kb
Host smart-d3629f55-1e3e-4fbc-a71d-52b1c9ecb22a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449958500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2449958500
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2300082941
Short name T610
Test name
Test status
Simulation time 112573912607 ps
CPU time 2380.74 seconds
Started Jul 06 05:32:48 PM PDT 24
Finished Jul 06 06:12:29 PM PDT 24
Peak memory 318624 kb
Host smart-0f21fc2b-6bde-4675-82bf-46f2047975d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300082941 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2300082941
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3879005928
Short name T528
Test name
Test status
Simulation time 38979653967 ps
CPU time 911.15 seconds
Started Jul 06 05:32:57 PM PDT 24
Finished Jul 06 05:48:09 PM PDT 24
Peak memory 273956 kb
Host smart-d6dad230-4057-40c6-807e-9a4f29d6e2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879005928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3879005928
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2000955547
Short name T494
Test name
Test status
Simulation time 1740629845 ps
CPU time 64.53 seconds
Started Jul 06 05:32:54 PM PDT 24
Finished Jul 06 05:33:59 PM PDT 24
Peak memory 256780 kb
Host smart-a65ca164-67f4-4fd6-bcbd-d78c178cab04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20009
55547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2000955547
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3684950056
Short name T624
Test name
Test status
Simulation time 855166394 ps
CPU time 20.69 seconds
Started Jul 06 05:32:56 PM PDT 24
Finished Jul 06 05:33:17 PM PDT 24
Peak memory 249672 kb
Host smart-e4ceefca-b814-4854-bcaa-53eba0ae99b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36849
50056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3684950056
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3070478979
Short name T332
Test name
Test status
Simulation time 51792620996 ps
CPU time 926.97 seconds
Started Jul 06 05:32:54 PM PDT 24
Finished Jul 06 05:48:22 PM PDT 24
Peak memory 273784 kb
Host smart-883bf914-4f4f-44ca-ae4a-49703c9344f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070478979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3070478979
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3988604366
Short name T582
Test name
Test status
Simulation time 24603084643 ps
CPU time 1448.73 seconds
Started Jul 06 05:32:54 PM PDT 24
Finished Jul 06 05:57:03 PM PDT 24
Peak memory 273904 kb
Host smart-59aa0b5d-7dc7-413d-a6e9-befcc984c5d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988604366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3988604366
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1461402995
Short name T600
Test name
Test status
Simulation time 3916566194 ps
CPU time 165.59 seconds
Started Jul 06 05:32:57 PM PDT 24
Finished Jul 06 05:35:42 PM PDT 24
Peak memory 249336 kb
Host smart-592a2ef6-1154-4260-a5a9-a6cad1bb1772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461402995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1461402995
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.128285584
Short name T599
Test name
Test status
Simulation time 4652931736 ps
CPU time 64.32 seconds
Started Jul 06 05:32:54 PM PDT 24
Finished Jul 06 05:33:59 PM PDT 24
Peak memory 256680 kb
Host smart-8a04f884-8d49-4a7d-a99e-687c94b38cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12828
5584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.128285584
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3082629498
Short name T26
Test name
Test status
Simulation time 171807688 ps
CPU time 15.2 seconds
Started Jul 06 05:32:54 PM PDT 24
Finished Jul 06 05:33:10 PM PDT 24
Peak memory 255220 kb
Host smart-bf2ca4e0-16af-4089-880e-6d42c7afd1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30826
29498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3082629498
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3507719148
Short name T645
Test name
Test status
Simulation time 150747707 ps
CPU time 15.12 seconds
Started Jul 06 05:32:54 PM PDT 24
Finished Jul 06 05:33:10 PM PDT 24
Peak memory 248480 kb
Host smart-f68ca4cd-154d-4476-9d68-0b326d7845c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
19148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3507719148
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.558774229
Short name T405
Test name
Test status
Simulation time 323302821 ps
CPU time 21.18 seconds
Started Jul 06 05:32:56 PM PDT 24
Finished Jul 06 05:33:18 PM PDT 24
Peak memory 257324 kb
Host smart-4a255dbf-df55-48f5-b370-c22913715c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55877
4229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.558774229
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2137560616
Short name T591
Test name
Test status
Simulation time 39962885988 ps
CPU time 2216.21 seconds
Started Jul 06 05:32:56 PM PDT 24
Finished Jul 06 06:09:53 PM PDT 24
Peak memory 289684 kb
Host smart-517912e9-e8d1-4e99-834a-1fe923f32357
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137560616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2137560616
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1196746715
Short name T683
Test name
Test status
Simulation time 158368417797 ps
CPU time 1359.52 seconds
Started Jul 06 05:32:59 PM PDT 24
Finished Jul 06 05:55:39 PM PDT 24
Peak memory 273952 kb
Host smart-c30180af-09f9-4f7b-84c0-4955506d67c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196746715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1196746715
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.651345965
Short name T434
Test name
Test status
Simulation time 821910418 ps
CPU time 9.35 seconds
Started Jul 06 05:33:02 PM PDT 24
Finished Jul 06 05:33:11 PM PDT 24
Peak memory 255124 kb
Host smart-af62b6a3-47c6-450f-9812-f9e9c0bb0a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65134
5965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.651345965
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.897815089
Short name T285
Test name
Test status
Simulation time 2515291438 ps
CPU time 80.8 seconds
Started Jul 06 05:33:04 PM PDT 24
Finished Jul 06 05:34:25 PM PDT 24
Peak memory 249460 kb
Host smart-bfacf358-c9e1-40d8-9dd6-43c39546a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89781
5089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.897815089
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2567737268
Short name T308
Test name
Test status
Simulation time 60224995265 ps
CPU time 1644.09 seconds
Started Jul 06 05:33:01 PM PDT 24
Finished Jul 06 06:00:26 PM PDT 24
Peak memory 273956 kb
Host smart-8ef688f2-e289-4867-85b4-dda9fc16a877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567737268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2567737268
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1007736206
Short name T6
Test name
Test status
Simulation time 39873829816 ps
CPU time 2143.69 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 06:08:44 PM PDT 24
Peak memory 282924 kb
Host smart-3318f1e7-3927-4cb8-9f96-c97457c79479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007736206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1007736206
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1316852850
Short name T54
Test name
Test status
Simulation time 2156909821 ps
CPU time 41.27 seconds
Started Jul 06 05:32:56 PM PDT 24
Finished Jul 06 05:33:37 PM PDT 24
Peak memory 249316 kb
Host smart-c33a7f61-d19e-4cb5-bf6d-08c0f0d324ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
52850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1316852850
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3181564467
Short name T420
Test name
Test status
Simulation time 192721015 ps
CPU time 29.23 seconds
Started Jul 06 05:32:59 PM PDT 24
Finished Jul 06 05:33:29 PM PDT 24
Peak memory 257332 kb
Host smart-48b3328b-3e69-4118-86d6-cda84955c51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31815
64467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3181564467
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3796718918
Short name T290
Test name
Test status
Simulation time 1496061107 ps
CPU time 49.92 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 05:33:50 PM PDT 24
Peak memory 249320 kb
Host smart-ae7f478c-641b-41cc-b06a-b010481678b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967
18918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3796718918
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2036602334
Short name T641
Test name
Test status
Simulation time 366290787 ps
CPU time 23.67 seconds
Started Jul 06 05:32:56 PM PDT 24
Finished Jul 06 05:33:20 PM PDT 24
Peak memory 257024 kb
Host smart-47a2e8e1-92c9-499d-8de1-c947027c5d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
02334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2036602334
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2652329229
Short name T538
Test name
Test status
Simulation time 23988259417 ps
CPU time 84.06 seconds
Started Jul 06 05:33:02 PM PDT 24
Finished Jul 06 05:34:26 PM PDT 24
Peak memory 257616 kb
Host smart-82b73bbd-ca7b-4caf-8031-4c5865314ab6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652329229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2652329229
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.905960429
Short name T663
Test name
Test status
Simulation time 38441621055 ps
CPU time 3351.23 seconds
Started Jul 06 05:33:09 PM PDT 24
Finished Jul 06 06:29:01 PM PDT 24
Peak memory 322916 kb
Host smart-0bb133e7-0880-48fb-bd3f-6e1e53a94f7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905960429 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.905960429
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2032438567
Short name T391
Test name
Test status
Simulation time 126340939305 ps
CPU time 2267.98 seconds
Started Jul 06 05:33:07 PM PDT 24
Finished Jul 06 06:10:56 PM PDT 24
Peak memory 290068 kb
Host smart-12b2c71d-9013-4723-9562-524f6ae821c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032438567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2032438567
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.156630997
Short name T625
Test name
Test status
Simulation time 259147198 ps
CPU time 22.84 seconds
Started Jul 06 05:33:07 PM PDT 24
Finished Jul 06 05:33:31 PM PDT 24
Peak memory 256920 kb
Host smart-da78c4c7-7939-4e21-a5a1-cc8788791449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
0997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.156630997
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2086044338
Short name T544
Test name
Test status
Simulation time 1766757482 ps
CPU time 35.9 seconds
Started Jul 06 05:33:07 PM PDT 24
Finished Jul 06 05:33:43 PM PDT 24
Peak memory 256580 kb
Host smart-5d52d12c-2deb-4ba6-b553-252fc38c047d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20860
44338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2086044338
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1192405885
Short name T608
Test name
Test status
Simulation time 25851214990 ps
CPU time 1617.67 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 05:59:58 PM PDT 24
Peak memory 273940 kb
Host smart-8af1a851-e0ae-4663-a56e-d10638e3f001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192405885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1192405885
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1438359156
Short name T631
Test name
Test status
Simulation time 34860803650 ps
CPU time 2055.3 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 06:07:16 PM PDT 24
Peak memory 282804 kb
Host smart-60282bbc-5c8a-42b3-8297-88f7c7741dd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438359156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1438359156
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2185338700
Short name T316
Test name
Test status
Simulation time 59159566021 ps
CPU time 323.77 seconds
Started Jul 06 05:33:03 PM PDT 24
Finished Jul 06 05:38:27 PM PDT 24
Peak memory 249416 kb
Host smart-52eefa9d-19b0-410f-88e0-dd6b9b3df1db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185338700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2185338700
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3808441321
Short name T681
Test name
Test status
Simulation time 274033128 ps
CPU time 12.52 seconds
Started Jul 06 05:33:02 PM PDT 24
Finished Jul 06 05:33:15 PM PDT 24
Peak memory 249248 kb
Host smart-6132bc14-7b9c-4c85-b02a-a5b3f5da2ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38084
41321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3808441321
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1329918073
Short name T443
Test name
Test status
Simulation time 5842006624 ps
CPU time 23.78 seconds
Started Jul 06 05:33:01 PM PDT 24
Finished Jul 06 05:33:25 PM PDT 24
Peak memory 256216 kb
Host smart-0d0b7e61-eb48-4d4c-b6b1-921e1af37c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
18073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1329918073
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.4018809077
Short name T72
Test name
Test status
Simulation time 793936226 ps
CPU time 53.38 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 05:33:53 PM PDT 24
Peak memory 257416 kb
Host smart-ca65927f-7ad3-45fe-b214-d596c1a5ed2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40188
09077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.4018809077
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4017945106
Short name T269
Test name
Test status
Simulation time 1841626357 ps
CPU time 29.06 seconds
Started Jul 06 05:33:02 PM PDT 24
Finished Jul 06 05:33:32 PM PDT 24
Peak memory 249292 kb
Host smart-a92de052-bcdc-407e-9cba-7b604978483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40179
45106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4017945106
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3201574396
Short name T120
Test name
Test status
Simulation time 17185620704 ps
CPU time 1713.07 seconds
Started Jul 06 05:33:08 PM PDT 24
Finished Jul 06 06:01:41 PM PDT 24
Peak memory 303440 kb
Host smart-a0bafa64-9dc7-44a7-942d-d3bdcac78d24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201574396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3201574396
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2207911040
Short name T106
Test name
Test status
Simulation time 37294870050 ps
CPU time 3390.51 seconds
Started Jul 06 05:33:01 PM PDT 24
Finished Jul 06 06:29:32 PM PDT 24
Peak memory 338732 kb
Host smart-98ca8643-97ff-4f1f-be9a-8f1914eee230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207911040 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2207911040
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1146389986
Short name T654
Test name
Test status
Simulation time 17702819462 ps
CPU time 1111.15 seconds
Started Jul 06 05:33:07 PM PDT 24
Finished Jul 06 05:51:39 PM PDT 24
Peak memory 273868 kb
Host smart-ba9ed427-3b4c-4966-82ca-18acd33c669e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146389986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1146389986
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2836193719
Short name T244
Test name
Test status
Simulation time 1737689329 ps
CPU time 143.25 seconds
Started Jul 06 05:33:08 PM PDT 24
Finished Jul 06 05:35:31 PM PDT 24
Peak memory 256440 kb
Host smart-16c36346-82a3-4df8-8c16-a09f852036e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
93719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2836193719
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2166273719
Short name T79
Test name
Test status
Simulation time 152157821 ps
CPU time 3.79 seconds
Started Jul 06 05:33:06 PM PDT 24
Finished Jul 06 05:33:10 PM PDT 24
Peak memory 249300 kb
Host smart-21c9ea1b-6d6d-49f7-97fb-1d21004bdda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
73719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2166273719
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2053495851
Short name T548
Test name
Test status
Simulation time 21318401426 ps
CPU time 1205.36 seconds
Started Jul 06 05:33:05 PM PDT 24
Finished Jul 06 05:53:11 PM PDT 24
Peak memory 273876 kb
Host smart-81b34cd1-e38b-4822-9535-fc2c58f6d585
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053495851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2053495851
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1018319828
Short name T424
Test name
Test status
Simulation time 81715270678 ps
CPU time 2590.71 seconds
Started Jul 06 05:33:06 PM PDT 24
Finished Jul 06 06:16:17 PM PDT 24
Peak memory 290080 kb
Host smart-943f5abd-aeea-4e49-9019-644827544c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018319828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1018319828
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2256319763
Short name T637
Test name
Test status
Simulation time 17417907227 ps
CPU time 359.14 seconds
Started Jul 06 05:33:06 PM PDT 24
Finished Jul 06 05:39:06 PM PDT 24
Peak memory 249376 kb
Host smart-68f905f6-577d-45aa-a2a2-613cbc4687b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256319763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2256319763
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.633792109
Short name T703
Test name
Test status
Simulation time 1848828046 ps
CPU time 37.07 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 05:33:38 PM PDT 24
Peak memory 257432 kb
Host smart-e16ebe20-524a-422b-8633-f7a022dfa65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63379
2109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.633792109
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4077798305
Short name T491
Test name
Test status
Simulation time 245460434 ps
CPU time 32.88 seconds
Started Jul 06 05:33:05 PM PDT 24
Finished Jul 06 05:33:38 PM PDT 24
Peak memory 248424 kb
Host smart-8264e5d0-51c6-49e9-aeda-90557970a49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40777
98305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4077798305
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1666842204
Short name T604
Test name
Test status
Simulation time 1358683536 ps
CPU time 24.35 seconds
Started Jul 06 05:33:00 PM PDT 24
Finished Jul 06 05:33:25 PM PDT 24
Peak memory 257396 kb
Host smart-60f1f352-7d0f-42f7-a652-e701cf2f113c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16668
42204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1666842204
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2861831647
Short name T270
Test name
Test status
Simulation time 42467426754 ps
CPU time 466.63 seconds
Started Jul 06 05:33:03 PM PDT 24
Finished Jul 06 05:40:50 PM PDT 24
Peak memory 265636 kb
Host smart-fe1d5bb1-83f7-4db8-92ac-54861d019c86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861831647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2861831647
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.337394275
Short name T216
Test name
Test status
Simulation time 27829767 ps
CPU time 2.52 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:30:55 PM PDT 24
Peak memory 249580 kb
Host smart-87afa948-981e-4b90-b617-130deaaf04b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=337394275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.337394275
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4049462225
Short name T566
Test name
Test status
Simulation time 53223480004 ps
CPU time 3070.94 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 06:22:11 PM PDT 24
Peak memory 290236 kb
Host smart-554318ad-f4a7-4ad1-a58c-d4abf011187c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049462225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4049462225
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2628718061
Short name T393
Test name
Test status
Simulation time 344477178 ps
CPU time 18.28 seconds
Started Jul 06 05:31:01 PM PDT 24
Finished Jul 06 05:31:19 PM PDT 24
Peak memory 249276 kb
Host smart-54f5dde7-c5d5-4a16-9ce2-67ad4709684a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2628718061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2628718061
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1291183879
Short name T532
Test name
Test status
Simulation time 29028973192 ps
CPU time 133.82 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 05:33:11 PM PDT 24
Peak memory 257600 kb
Host smart-8f9b26ba-eb0a-41f5-84d0-11971e1be87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
83879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1291183879
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3271504598
Short name T380
Test name
Test status
Simulation time 269095161 ps
CPU time 12.84 seconds
Started Jul 06 05:31:00 PM PDT 24
Finished Jul 06 05:31:13 PM PDT 24
Peak memory 257476 kb
Host smart-2cbe5e6c-a08f-4e01-afcd-48404373809f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32715
04598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3271504598
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3371797535
Short name T339
Test name
Test status
Simulation time 113814155120 ps
CPU time 1320.97 seconds
Started Jul 06 05:30:58 PM PDT 24
Finished Jul 06 05:53:00 PM PDT 24
Peak memory 290152 kb
Host smart-58001b7d-abe5-47df-94b4-12d7f53a5534
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371797535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3371797535
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3184937901
Short name T682
Test name
Test status
Simulation time 89426121289 ps
CPU time 2563.91 seconds
Started Jul 06 05:31:05 PM PDT 24
Finished Jul 06 06:13:49 PM PDT 24
Peak memory 282212 kb
Host smart-3549152f-ac38-4e88-893d-2726fff826b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184937901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3184937901
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3385147213
Short name T29
Test name
Test status
Simulation time 1330131325 ps
CPU time 40.94 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:31:35 PM PDT 24
Peak memory 256540 kb
Host smart-c4922105-b5c8-470c-bd4b-bfed54ad77e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33851
47213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3385147213
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3270710825
Short name T557
Test name
Test status
Simulation time 786531594 ps
CPU time 15.11 seconds
Started Jul 06 05:30:55 PM PDT 24
Finished Jul 06 05:31:11 PM PDT 24
Peak memory 248392 kb
Host smart-83f6a44e-91c9-4ffb-9550-d545dfca3519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
10825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3270710825
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4234508290
Short name T584
Test name
Test status
Simulation time 145605096 ps
CPU time 9.12 seconds
Started Jul 06 05:30:52 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 249260 kb
Host smart-c0a0bf94-e7b7-46e4-8e02-978ad7ceb816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
08290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4234508290
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2650697786
Short name T415
Test name
Test status
Simulation time 1359837092 ps
CPU time 23.18 seconds
Started Jul 06 05:30:53 PM PDT 24
Finished Jul 06 05:31:16 PM PDT 24
Peak memory 249476 kb
Host smart-85aa05a1-e0e7-4386-a9d4-2752e044f4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26506
97786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2650697786
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3377819906
Short name T186
Test name
Test status
Simulation time 185051668097 ps
CPU time 8981.04 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 08:00:36 PM PDT 24
Peak memory 372364 kb
Host smart-25e0e3c5-6ade-41d7-87e7-5bfe59b3c494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377819906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3377819906
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2268788953
Short name T211
Test name
Test status
Simulation time 25657879 ps
CPU time 2.64 seconds
Started Jul 06 05:31:05 PM PDT 24
Finished Jul 06 05:31:09 PM PDT 24
Peak memory 249516 kb
Host smart-c0cd3912-5e24-48fb-9702-100ce442019d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2268788953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2268788953
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.688834331
Short name T224
Test name
Test status
Simulation time 585224888166 ps
CPU time 1758.09 seconds
Started Jul 06 05:30:57 PM PDT 24
Finished Jul 06 06:00:16 PM PDT 24
Peak memory 273496 kb
Host smart-0a0cfca5-46da-448d-8a55-f43e47bdb5c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688834331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.688834331
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.460861033
Short name T483
Test name
Test status
Simulation time 238037426 ps
CPU time 21.2 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:31:28 PM PDT 24
Peak memory 257016 kb
Host smart-f0a56495-d265-447d-a749-9b8faf91f020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46086
1033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.460861033
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1313538041
Short name T17
Test name
Test status
Simulation time 29225747 ps
CPU time 3.73 seconds
Started Jul 06 05:30:56 PM PDT 24
Finished Jul 06 05:31:01 PM PDT 24
Peak memory 240640 kb
Host smart-c6e11e38-f184-44c9-81b9-8de6faf711ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13135
38041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1313538041
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2807653866
Short name T305
Test name
Test status
Simulation time 136402528082 ps
CPU time 1806.55 seconds
Started Jul 06 05:31:12 PM PDT 24
Finished Jul 06 06:01:19 PM PDT 24
Peak memory 273900 kb
Host smart-97312286-d72c-45db-ab9e-377e5a49c72e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807653866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2807653866
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1862130237
Short name T99
Test name
Test status
Simulation time 199940319616 ps
CPU time 1553.75 seconds
Started Jul 06 05:31:02 PM PDT 24
Finished Jul 06 05:56:56 PM PDT 24
Peak memory 273816 kb
Host smart-192c6b2d-d501-463f-b3b9-9f82a8cee3ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862130237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1862130237
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3444766797
Short name T711
Test name
Test status
Simulation time 5924747087 ps
CPU time 253.74 seconds
Started Jul 06 05:31:07 PM PDT 24
Finished Jul 06 05:35:21 PM PDT 24
Peak memory 249292 kb
Host smart-4b5980b5-0827-428d-9f29-0463c8225b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444766797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3444766797
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1232231719
Short name T28
Test name
Test status
Simulation time 425200176 ps
CPU time 41.77 seconds
Started Jul 06 05:31:17 PM PDT 24
Finished Jul 06 05:31:59 PM PDT 24
Peak memory 256796 kb
Host smart-5d383c70-1ec1-47cc-847e-560ee504df50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12322
31719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1232231719
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1448888776
Short name T366
Test name
Test status
Simulation time 111899460 ps
CPU time 11.89 seconds
Started Jul 06 05:31:09 PM PDT 24
Finished Jul 06 05:31:22 PM PDT 24
Peak memory 248820 kb
Host smart-1dc40155-2440-454a-95a5-fa0863411b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
88776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1448888776
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4102697189
Short name T452
Test name
Test status
Simulation time 231322600 ps
CPU time 26.45 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 256880 kb
Host smart-f14d41ec-0ead-4880-80c8-3ae34c36089a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41026
97189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4102697189
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.799757946
Short name T509
Test name
Test status
Simulation time 155649519 ps
CPU time 6.63 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:31:13 PM PDT 24
Peak memory 252308 kb
Host smart-d3ff8a50-38c9-4bae-a57d-39885bae5095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79975
7946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.799757946
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1819769415
Short name T289
Test name
Test status
Simulation time 63677825235 ps
CPU time 1543.17 seconds
Started Jul 06 05:30:54 PM PDT 24
Finished Jul 06 05:56:38 PM PDT 24
Peak memory 290344 kb
Host smart-3a6cfbf9-c2d1-410d-a49e-ea476bc005dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819769415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1819769415
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3069377452
Short name T112
Test name
Test status
Simulation time 156134283509 ps
CPU time 3952.92 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 06:37:13 PM PDT 24
Peak memory 323032 kb
Host smart-64a75190-228a-4967-9163-925f365aae2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069377452 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3069377452
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1641154847
Short name T213
Test name
Test status
Simulation time 36165448 ps
CPU time 3.38 seconds
Started Jul 06 05:31:17 PM PDT 24
Finished Jul 06 05:31:21 PM PDT 24
Peak memory 249568 kb
Host smart-3cd0c0bf-94a7-448a-9b61-f63b233ae57b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1641154847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1641154847
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1606613493
Short name T512
Test name
Test status
Simulation time 55201523745 ps
CPU time 1633.79 seconds
Started Jul 06 05:31:08 PM PDT 24
Finished Jul 06 05:58:22 PM PDT 24
Peak memory 273936 kb
Host smart-84f735aa-f177-4cc2-a441-6af075975f30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606613493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1606613493
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.254132786
Short name T458
Test name
Test status
Simulation time 1236263410 ps
CPU time 18.4 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:31:38 PM PDT 24
Peak memory 249268 kb
Host smart-56df9bba-18ab-410d-8e60-10ccd5d59839
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=254132786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.254132786
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3760815929
Short name T499
Test name
Test status
Simulation time 6649092880 ps
CPU time 124.46 seconds
Started Jul 06 05:31:13 PM PDT 24
Finished Jul 06 05:33:18 PM PDT 24
Peak memory 257152 kb
Host smart-97c21331-d361-4922-8d91-ceacd2394972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37608
15929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3760815929
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.269142415
Short name T630
Test name
Test status
Simulation time 7817870358 ps
CPU time 60.6 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 05:32:17 PM PDT 24
Peak memory 256888 kb
Host smart-2e4607be-6844-41dd-8863-d613f8d7d6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26914
2415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.269142415
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1641862598
Short name T337
Test name
Test status
Simulation time 31606226408 ps
CPU time 1526.37 seconds
Started Jul 06 05:31:17 PM PDT 24
Finished Jul 06 05:56:44 PM PDT 24
Peak memory 289776 kb
Host smart-3c826deb-f657-4f8b-99da-807fea736789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641862598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1641862598
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2463015368
Short name T467
Test name
Test status
Simulation time 10617845325 ps
CPU time 964.88 seconds
Started Jul 06 05:31:13 PM PDT 24
Finished Jul 06 05:47:18 PM PDT 24
Peak memory 282532 kb
Host smart-d68988bb-2221-4017-9080-4dd50529717c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463015368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2463015368
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.677133253
Short name T232
Test name
Test status
Simulation time 19610720070 ps
CPU time 217.16 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:34:48 PM PDT 24
Peak memory 255580 kb
Host smart-c015fd83-e247-482b-9d5a-cd5f58789ccc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677133253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.677133253
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3026449663
Short name T704
Test name
Test status
Simulation time 381492581 ps
CPU time 12.55 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 05:31:32 PM PDT 24
Peak memory 249296 kb
Host smart-3e278055-60dc-4ccc-a1f2-3546ed05a6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30264
49663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3026449663
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3209978450
Short name T684
Test name
Test status
Simulation time 614823091 ps
CPU time 30.24 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 05:31:47 PM PDT 24
Peak memory 249196 kb
Host smart-9f7a137c-19a2-424f-9373-56d861c1406f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
78450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3209978450
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3767345162
Short name T702
Test name
Test status
Simulation time 120858721 ps
CPU time 15.43 seconds
Started Jul 06 05:31:13 PM PDT 24
Finished Jul 06 05:31:29 PM PDT 24
Peak memory 248824 kb
Host smart-4ec467d2-212d-4e0f-9d92-bb271de8c9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
45162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3767345162
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2286372318
Short name T564
Test name
Test status
Simulation time 428926311 ps
CPU time 25.47 seconds
Started Jul 06 05:31:04 PM PDT 24
Finished Jul 06 05:31:30 PM PDT 24
Peak memory 249268 kb
Host smart-da257c26-b4f9-4f46-903a-b75e75a73ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
72318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2286372318
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.615432369
Short name T249
Test name
Test status
Simulation time 121010792496 ps
CPU time 1853.34 seconds
Started Jul 06 05:31:25 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 289280 kb
Host smart-3a0a3292-3783-4254-a8f6-f8c04797ec47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615432369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.615432369
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1388340867
Short name T39
Test name
Test status
Simulation time 85521896 ps
CPU time 3.58 seconds
Started Jul 06 05:31:30 PM PDT 24
Finished Jul 06 05:31:34 PM PDT 24
Peak memory 249580 kb
Host smart-4c72ef84-ea3d-46cd-b36a-49ab42897883
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1388340867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1388340867
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3177978125
Short name T397
Test name
Test status
Simulation time 15787210195 ps
CPU time 1261.14 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:52:08 PM PDT 24
Peak memory 287644 kb
Host smart-f1a77b11-9c28-42b3-96d2-83b4ac9bcdcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177978125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3177978125
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3001047958
Short name T417
Test name
Test status
Simulation time 2500083520 ps
CPU time 28.79 seconds
Started Jul 06 05:31:08 PM PDT 24
Finished Jul 06 05:31:37 PM PDT 24
Peak memory 249372 kb
Host smart-31f3a84b-b60d-4173-9228-911bba837ba2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3001047958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3001047958
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3090964160
Short name T42
Test name
Test status
Simulation time 16563827345 ps
CPU time 235.62 seconds
Started Jul 06 05:31:12 PM PDT 24
Finished Jul 06 05:35:08 PM PDT 24
Peak memory 256760 kb
Host smart-37cdf563-f1f4-4945-b1f2-188d01edbbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
64160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3090964160
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3629005946
Short name T279
Test name
Test status
Simulation time 8826502727 ps
CPU time 81.15 seconds
Started Jul 06 05:31:10 PM PDT 24
Finished Jul 06 05:32:32 PM PDT 24
Peak memory 256232 kb
Host smart-4c855ea8-15c6-49fd-b76c-fb2342017705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36290
05946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3629005946
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.468074664
Short name T338
Test name
Test status
Simulation time 35690751424 ps
CPU time 1671.4 seconds
Started Jul 06 05:31:19 PM PDT 24
Finished Jul 06 05:59:10 PM PDT 24
Peak memory 290232 kb
Host smart-3ae7a706-18d1-4987-a167-2b59223ac887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468074664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.468074664
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3948647342
Short name T446
Test name
Test status
Simulation time 109954320452 ps
CPU time 1763.9 seconds
Started Jul 06 05:31:18 PM PDT 24
Finished Jul 06 06:00:42 PM PDT 24
Peak memory 273980 kb
Host smart-958af346-e314-442d-a65b-3d48bd535eb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948647342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3948647342
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2826572060
Short name T628
Test name
Test status
Simulation time 13945461475 ps
CPU time 215.14 seconds
Started Jul 06 05:31:15 PM PDT 24
Finished Jul 06 05:34:51 PM PDT 24
Peak memory 249292 kb
Host smart-32e7dee6-de88-4846-8167-282e9d0fd83f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826572060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2826572060
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2316133720
Short name T614
Test name
Test status
Simulation time 2137157645 ps
CPU time 37.2 seconds
Started Jul 06 05:31:12 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 257364 kb
Host smart-3dbd8d83-24a2-4e70-9434-4f0b2d3d4aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
33720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2316133720
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.4059572689
Short name T516
Test name
Test status
Simulation time 155111881 ps
CPU time 18.6 seconds
Started Jul 06 05:31:12 PM PDT 24
Finished Jul 06 05:31:31 PM PDT 24
Peak memory 248584 kb
Host smart-1e6a804f-9ae4-464a-8c76-68f5db77854c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40595
72689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.4059572689
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2477683024
Short name T673
Test name
Test status
Simulation time 504152890 ps
CPU time 34.45 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 05:31:46 PM PDT 24
Peak memory 249224 kb
Host smart-8a4c1645-6f8f-45f7-a48f-a3a38c68efa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24776
83024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2477683024
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1650820201
Short name T439
Test name
Test status
Simulation time 448075524 ps
CPU time 10.55 seconds
Started Jul 06 05:31:14 PM PDT 24
Finished Jul 06 05:31:25 PM PDT 24
Peak memory 249260 kb
Host smart-6712f8e1-59f8-43bd-ac79-b12b4e04304f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
20201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1650820201
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.906498885
Short name T41
Test name
Test status
Simulation time 5461439572 ps
CPU time 315.75 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:36:23 PM PDT 24
Peak memory 257604 kb
Host smart-93d34368-1c44-43a4-bf1d-15a9b6fcdc81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906498885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.906498885
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2574522692
Short name T115
Test name
Test status
Simulation time 32101520 ps
CPU time 3.3 seconds
Started Jul 06 05:31:13 PM PDT 24
Finished Jul 06 05:31:17 PM PDT 24
Peak memory 249572 kb
Host smart-20efa25d-7e2e-4fea-ab70-e1e0529d5069
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2574522692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2574522692
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3352502392
Short name T468
Test name
Test status
Simulation time 77435766309 ps
CPU time 1507.05 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 05:56:24 PM PDT 24
Peak memory 265816 kb
Host smart-cbb40243-653d-4006-8eff-2dc10a65d1fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352502392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3352502392
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1994112068
Short name T421
Test name
Test status
Simulation time 682149963 ps
CPU time 29.59 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 05:31:41 PM PDT 24
Peak memory 249260 kb
Host smart-48866cb7-211f-44b9-b5ce-53e2a965923a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1994112068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1994112068
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2519636959
Short name T526
Test name
Test status
Simulation time 8463351594 ps
CPU time 125.38 seconds
Started Jul 06 05:31:12 PM PDT 24
Finished Jul 06 05:33:18 PM PDT 24
Peak memory 257100 kb
Host smart-ebb0d632-12ff-47d3-a151-5f9da0a41b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
36959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2519636959
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1216987594
Short name T586
Test name
Test status
Simulation time 2444233947 ps
CPU time 8.95 seconds
Started Jul 06 05:31:15 PM PDT 24
Finished Jul 06 05:31:24 PM PDT 24
Peak memory 249348 kb
Host smart-7772ad06-56ca-4253-8a4c-139a0a1a91b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12169
87594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1216987594
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1269133946
Short name T325
Test name
Test status
Simulation time 14727703253 ps
CPU time 1372.44 seconds
Started Jul 06 05:31:15 PM PDT 24
Finished Jul 06 05:54:08 PM PDT 24
Peak memory 289736 kb
Host smart-565438f7-520b-4185-8e70-bafaf0f44a3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269133946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1269133946
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.851656651
Short name T49
Test name
Test status
Simulation time 42171278363 ps
CPU time 1241.9 seconds
Started Jul 06 05:31:06 PM PDT 24
Finished Jul 06 05:51:48 PM PDT 24
Peak memory 265764 kb
Host smart-bfd48df9-5b6b-4dbe-83bc-facaec2fbd63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851656651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.851656651
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.504350010
Short name T197
Test name
Test status
Simulation time 31686477514 ps
CPU time 343.6 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 05:37:00 PM PDT 24
Peak memory 249088 kb
Host smart-21d1fdf7-572c-4a8f-ad12-ec085a0593e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504350010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.504350010
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.4184142408
Short name T648
Test name
Test status
Simulation time 764798229 ps
CPU time 51.51 seconds
Started Jul 06 05:31:21 PM PDT 24
Finished Jul 06 05:32:13 PM PDT 24
Peak memory 256544 kb
Host smart-1b73813b-ad77-460c-ab5b-7c2ac1101630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41841
42408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.4184142408
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2605111561
Short name T409
Test name
Test status
Simulation time 421536990 ps
CPU time 37.89 seconds
Started Jul 06 05:31:16 PM PDT 24
Finished Jul 06 05:31:54 PM PDT 24
Peak memory 257428 kb
Host smart-310e14b9-c7fc-49b7-9be1-57ee7f92edde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26051
11561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2605111561
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3689965935
Short name T664
Test name
Test status
Simulation time 489533046 ps
CPU time 9.26 seconds
Started Jul 06 05:31:23 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 248784 kb
Host smart-6bd72f46-0512-4530-81b5-2b4902f38fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899
65935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3689965935
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1789803168
Short name T642
Test name
Test status
Simulation time 296751861 ps
CPU time 4.29 seconds
Started Jul 06 05:31:20 PM PDT 24
Finished Jul 06 05:31:25 PM PDT 24
Peak memory 251440 kb
Host smart-0b24a80b-231e-4e2b-a73b-1df60c5a44db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
03168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1789803168
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2169205298
Short name T90
Test name
Test status
Simulation time 47128437612 ps
CPU time 5424.35 seconds
Started Jul 06 05:31:11 PM PDT 24
Finished Jul 06 07:01:36 PM PDT 24
Peak memory 355780 kb
Host smart-ee423e5b-6687-4809-8bb1-880f928be29d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169205298 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2169205298
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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