Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	83673	1			T24	96		T7	32		T31	8
class_i[0x1]	63632	1			T21	145		T4	3921		T31	107
class_i[0x2]	35192	1			T7	4		T17	2804		T9	7
class_i[0x3]	63854	1			T7	5184		T31	2		T18	2025

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60336	1			T21	6		T4	1000		T24	28
alert[0x1]	63776	1			T21	93		T4	979		T24	24
alert[0x2]	61033	1			T21	14		T4	967		T24	12
alert[0x3]	61206	1			T21	32		T4	975		T24	32

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

246073

1

T21

145

T4

3921

T24

96

esc_ping_fail

278

1

T12

4

T13

8

T14

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60259	1			T21	6		T4	1000		T24	28
esc_integrity_fail	alert[0x1]	63708	1			T21	93		T4	979		T24	24
esc_integrity_fail	alert[0x2]	60959	1			T21	14		T4	967		T24	12
esc_integrity_fail	alert[0x3]	61147	1			T21	32		T4	975		T24	32
esc_ping_fail	alert[0x0]	77	1			T13	1		T14	3		T288	1
esc_ping_fail	alert[0x1]	68	1			T12	1		T13	2		T288	2
esc_ping_fail	alert[0x2]	74	1			T12	2		T13	3		T14	2
esc_ping_fail	alert[0x3]	59	1			T12	1		T13	2		T14	4

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	83618	1			T24	96		T7	32		T31	8
esc_integrity_fail	class_i[0x1]	63547	1			T21	145		T4	3921		T31	107
esc_integrity_fail	class_i[0x2]	35121	1			T7	4		T17	2804		T9	7
esc_integrity_fail	class_i[0x3]	63787	1			T7	5184		T31	2		T18	2025
esc_ping_fail	class_i[0x0]	55	1			T12	4		T14	1		T288	4
esc_ping_fail	class_i[0x1]	85	1			T13	8		T288	1		T290	1
esc_ping_fail	class_i[0x2]	71	1			T14	8		T288	1		T290	5
esc_ping_fail	class_i[0x3]	67	1			T289	8		T299	2		T217	1