Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	701318401	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	701318401	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	701318401	701118036	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	701318401	701118036	0	0
tb.dut.EdnKnownO_A	0	0	701318401	701118036	0	0
tb.dut.EscPKnownO_A	0	0	701318401	701118036	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	701318401	100	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	701318401	100	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	701318401	100	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	701318401	100	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	701318401	100	0	0
tb.dut.IrqAKnownO_A	0	0	701318401	701118036	0	0
tb.dut.IrqBKnownO_A	0	0	701318401	701118036	0	0
tb.dut.IrqCKnownO_A	0	0	701318401	701118036	0	0
tb.dut.IrqDKnownO_A	0	0	701318401	701118036	0	0
tb.dut.TlAReadyKnownO_A	0	0	701318401	701118036	0	0
tb.dut.TlDValidKnownO_A	0	0	701318401	701118036	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	727241714	3412061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	727241714	11799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	727241714	11897	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	727241714	11390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	727241714	11302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	727241714	11675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	727241714	11394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	727241714	10108	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	727241714	11390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	727241714	11682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	727241714	11369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	727241714	11387	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	727241714	11367	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	727241714	11355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	727241714	10576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	727241714	10539	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	727241714	10535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	727241714	10431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	727241714	11508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	727241714	10683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	727241714	11606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	727241714	10450	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	727241714	10144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	727241714	10227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	727241714	10201	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	727241714	11881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	727241714	11627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	727241714	10407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	727241714	11431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	727241714	10421	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	727241714	11527	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	727241714	11279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	727241714	11710	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	727241714	11579	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	727241714	11361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	727241714	11572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	727241714	11527	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	727241714	10743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	727241714	10225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	727241714	10590	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	727241714	10359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	727241714	12335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	727241714	10145	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	727241714	11570	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	727241714	10556	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	727241714	12713	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	727241714	12890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	727241714	12561	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	727241714	11408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	727241714	11431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	727241714	11554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	727241714	11586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	727241714	12633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	727241714	10345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	727241714	11431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	727241714	10607	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	727241714	10335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	727241714	11592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	727241714	11541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	727241714	10682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	727241714	10281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	727241714	11849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	727241714	10680	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	727241714	11403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	727241714	12635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	727241714	10265	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	727241714	10279	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	727241714	10736	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	727241714	10454	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	727241714	12631	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	727241714	18845	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	727241714	11754	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	727241714	12643	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	727241714	12547	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	727241714	10336	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	727241714	10419	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	727241714	11314	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	727241714	10225	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	727241714	11589	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	701318401	1482	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	701318401	254631	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	701318401	312893430	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	701318401	361	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	701318401	893	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	701318401	65	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	701318401	446	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	701122566	229556080	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	701318401	1019	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	701318401	986	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	701318401	968	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	701318401	945	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	701318401	1435	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	701318401	122725	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	701318401	1289	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	701318401	77	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701318401	1819	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	701318401	1519	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	701120725	701048020	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	701318401	701118036	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	701318401	4352	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	701318401	187288	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	701318401	390966442	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	701318401	354	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	701318401	494	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	701318401	31	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	701318401	226	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	701122566	306487545	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	701318401	579	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	701318401	570	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	701318401	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	701318401	562	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	701318401	1625	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	701318401	158610	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	701318401	1527	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	701318401	67	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701318401	1839	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	701318401	1539	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	701120725	701048020	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	701318401	701118036	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	701318401	2263	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	701318401	172991	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	701318401	407424165	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	701318401	379	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	701318401	460	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	701318401	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	701318401	199	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	701122566	313650953	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	701318401	540	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	701318401	529	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	701318401	523	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	701318401	516	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	701318401	1283	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	701318401	144987	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	701318401	1195	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	701318401	67	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701318401	1791	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	701318401	1491	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	701120725	701048020	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	701318401	701118036	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	701318401	100	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	701318401	4317	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	701318401	215870	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	701318401	421076952	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	701318401	396	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	701318401	494	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	701318401	30	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	701318401	227	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	701122566	358874727	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	701318401	596	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	701318401	583	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	701318401	570	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	701318401	561	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	701318401	1219	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	701318401	114290	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	701318401	1106	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	701318401	81	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701318401	1812	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	701318401	1512	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	701120725	701048020	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	701318401	701118036	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	727241714	140826877	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	727241714	726504056	0	0
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