Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	77	1			T21	1		T7	1		T65	1
class_index[0x1]	67	1			T65	1		T42	1		T70	2
class_index[0x2]	67	1			T22	1		T24	1		T65	1
class_index[0x3]	81	1			T37	1		T59	1		T60	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	123	1			T21	1		T63	1		T40	2
intr_timeout_cnt[1]	64	1			T22	1		T65	2		T38	1
intr_timeout_cnt[2]	30	1			T7	1		T37	1		T72	1
intr_timeout_cnt[3]	23	1			T24	1		T107	1		T72	1
intr_timeout_cnt[4]	14	1			T71	1		T108	1		T109	1
intr_timeout_cnt[5]	6	1			T42	1		T75	1		T234	1
intr_timeout_cnt[6]	11	1			T65	1		T59	1		T44	1
intr_timeout_cnt[7]	8	1			T60	2		T71	1		T77	1
intr_timeout_cnt[8]	8	1			T174	1		T96	1		T235	2
intr_timeout_cnt[9]	5	1			T236	1		T27	1		T237	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	40	1			T21	1		T40	2		T29	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T38	1		T83	1		T238	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T7	1		T227	3		T93	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T72	1		T95	2		T239	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T240	3		T241	1		T27	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T96	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T65	1		T242	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T60	1		T243	1		T244	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T96	1		T245	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	25	1			T71	1		T74	1		T174	5
class_index[0x1]	intr_timeout_cnt[1]	14	1			T65	1		T70	2		T73	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T228	3		T246	1		T245	1
class_index[0x1]	intr_timeout_cnt[3]	8	1			T174	2		T81	1		T82	3
class_index[0x1]	intr_timeout_cnt[4]	2	1			T243	1		T247	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T42	1		T75	1		T234	1
class_index[0x1]	intr_timeout_cnt[6]	4	1			T44	1		T248	1		T249	2
class_index[0x1]	intr_timeout_cnt[7]	2	1			T77	1		T244	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T235	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T27	1		T237	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T85	3		T95	1		T82	1
class_index[0x2]	intr_timeout_cnt[1]	19	1			T22	1		T65	1		T42	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T96	1		T52	1		T250	1
class_index[0x2]	intr_timeout_cnt[3]	9	1			T24	1		T251	1		T239	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T252	1		T253	1		T244	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T235	1		T231	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T71	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T254	1		T242	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T245	1		T255	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	36	1			T63	1		T71	1		T30	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T106	1		T256	1		T257	1
class_index[0x3]	intr_timeout_cnt[2]	10	1			T37	1		T72	1		T51	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T107	1		T245	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T71	1		T108	1		T109	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T59	1		T174	1		T27	2
class_index[0x3]	intr_timeout_cnt[7]	2	1			T60	1		T258	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T174	1		T244	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T236	1		-	-		-	-