Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	360460	1			T1	13		T2	1481		T3	13
all_values[1]	360460	1			T1	13		T2	1481		T3	13
all_values[2]	360460	1			T1	13		T2	1481		T3	13
all_values[3]	360460	1			T1	13		T2	1481		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

717716

1

T1

36

T2

2965

T3

17

auto[1]

724124

1

T1

16

T2

2959

T3

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

866742

1

T1

28

T2

2976

T3

28

auto[1]

575098

1

T1

24

T2

2948

T3

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103333	1			T1	5		T2	352		T3	2
all_values[0]	auto[0]	auto[1]	76180	1			T1	4		T2	350		T3	2
all_values[0]	auto[1]	auto[0]	104643	1			T1	2		T2	392		T3	5
all_values[0]	auto[1]	auto[1]	76304	1			T1	2		T2	387		T3	4
all_values[1]	auto[0]	auto[0]	108349	1			T1	6		T2	362		T3	2
all_values[1]	auto[0]	auto[1]	71145	1			T1	5		T2	359		T3	2
all_values[1]	auto[1]	auto[0]	109694	1			T1	1		T2	380		T3	5
all_values[1]	auto[1]	auto[1]	71272	1			T1	1		T2	380		T3	4
all_values[2]	auto[0]	auto[0]	108461	1			T1	4		T2	399		T3	3
all_values[2]	auto[0]	auto[1]	71121	1			T1	3		T2	396		T3	2
all_values[2]	auto[1]	auto[0]	109670	1			T1	3		T2	343		T3	4
all_values[2]	auto[1]	auto[1]	71208	1			T1	3		T2	343		T3	4
all_values[3]	auto[0]	auto[0]	110360	1			T1	5		T2	376		T3	2
all_values[3]	auto[0]	auto[1]	68767	1			T1	4		T2	371		T3	2
all_values[3]	auto[1]	auto[0]	112232	1			T1	2		T2	372		T3	5
all_values[3]	auto[1]	auto[1]	69101	1			T1	2		T2	362		T3	4