Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	360460	1			T1	13		T2	1481		T3	13
all_pins[1]	360460	1			T1	13		T2	1481		T3	13
all_pins[2]	360460	1			T1	13		T2	1481		T3	13
all_pins[3]	360460	1			T1	13		T2	1481		T3	13

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1153955	1			T1	44		T2	4452		T3	36
values[0x1]	287885	1			T1	8		T2	1472		T3	16
transitions[0x0=>0x1]	192051	1			T1	7		T2	940		T3	9
transitions[0x1=>0x0]	192286	1			T1	7		T2	941		T3	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	284156	1			T1	11		T2	1094		T3	9
all_pins[0]	values[0x1]	76304	1			T1	2		T2	387		T3	4
all_pins[0]	transitions[0x0=>0x1]	75753	1			T1	2		T2	386		T3	3
all_pins[0]	transitions[0x1=>0x0]	68785	1			T1	2		T2	362		T3	4
all_pins[1]	values[0x0]	289188	1			T1	12		T2	1101		T3	9
all_pins[1]	values[0x1]	71272	1			T1	1		T2	380		T3	4
all_pins[1]	transitions[0x0=>0x1]	39484	1			T1	1		T2	189		T3	2
all_pins[1]	transitions[0x1=>0x0]	44516	1			T1	2		T2	196		T3	2
all_pins[2]	values[0x0]	289252	1			T1	10		T2	1138		T3	9
all_pins[2]	values[0x1]	71208	1			T1	3		T2	343		T3	4
all_pins[2]	transitions[0x0=>0x1]	39040	1			T1	3		T2	167		T3	2
all_pins[2]	transitions[0x1=>0x0]	39104	1			T1	1		T2	204		T3	2
all_pins[3]	values[0x0]	291359	1			T1	11		T2	1119		T3	9
all_pins[3]	values[0x1]	69101	1			T1	2		T2	362		T3	4
all_pins[3]	transitions[0x0=>0x1]	37774	1			T1	1		T2	198		T3	2
all_pins[3]	transitions[0x1=>0x0]	39881	1			T1	2		T2	179		T3	2