Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	101694	1			T2	497		T4	494		T7	709
accum_cnt_1000	241271	1			T2	464		T4	527		T25	116
accum_cnt_100	27928	1			T2	30		T4	19		T24	2
accum_cnt_50	62202	1			T1	4		T2	16		T3	7
accum_cnt_10	178185	1			T1	35		T2	8		T3	14
accum_cnt_0	411421	1			T1	1		T2	3299		T3	11

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	265465	1			T1	10		T2	1098		T3	8
class_index[0x1]	265465	1			T1	10		T2	1098		T3	8
class_index[0x2]	265465	1			T1	10		T2	1098		T3	8
class_index[0x3]	265465	1			T1	10		T2	1098		T3	8

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	31848	1			T2	497		T7	709		T8	421
class_index[0x0]	accum_cnt_1000	71749	1			T2	464		T7	665		T34	2
class_index[0x0]	accum_cnt_100	9083	1			T2	30		T24	2		T7	54
class_index[0x0]	accum_cnt_50	17803	1			T2	16		T3	3		T24	21
class_index[0x0]	accum_cnt_10	46093	1			T1	10		T2	8		T3	5
class_index[0x0]	accum_cnt_0	76934	1			T2	5		T6	2		T21	2
class_index[0x1]	accum_cnt_2000	24284	1			T17	207		T18	89		T8	438
class_index[0x1]	accum_cnt_1000	63783	1			T25	41		T17	496		T18	170
class_index[0x1]	accum_cnt_100	6741	1			T25	16		T31	3		T17	27
class_index[0x1]	accum_cnt_50	14159	1			T24	19		T25	14		T17	17
class_index[0x1]	accum_cnt_10	43867	1			T1	9		T3	5		T24	7
class_index[0x1]	accum_cnt_0	104501	1			T1	1		T2	1098		T3	3
class_index[0x2]	accum_cnt_2000	22922	1			T4	494		T17	255		T8	181
class_index[0x2]	accum_cnt_1000	58137	1			T4	527		T25	38		T35	47
class_index[0x2]	accum_cnt_100	6942	1			T4	19		T25	21		T35	18
class_index[0x2]	accum_cnt_50	15240	1			T1	4		T4	20		T25	17
class_index[0x2]	accum_cnt_10	39206	1			T1	6		T4	4		T22	32
class_index[0x2]	accum_cnt_0	115476	1			T2	1098		T3	8		T6	2
class_index[0x3]	accum_cnt_2000	22640	1			T18	375		T9	237		T37	283
class_index[0x3]	accum_cnt_1000	47602	1			T25	37		T7	83		T35	38
class_index[0x3]	accum_cnt_100	5162	1			T25	17		T7	47		T35	25
class_index[0x3]	accum_cnt_50	15000	1			T3	4		T21	4		T24	15
class_index[0x3]	accum_cnt_10	49019	1			T1	10		T3	4		T21	13
class_index[0x3]	accum_cnt_0	114510	1			T2	1098		T6	2		T4	1064