Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9731	1			T20	6326		T288	1		T47	66
alert[0x1]	7348	1			T4	2532		T14	1		T105	437
alert[0x2]	3506	1			T7	2		T30	291		T289	1
alert[0x3]	5865	1			T4	1820		T18	831		T14	1
alert[0x4]	3113	1			T4	4		T20	303		T259	5
alert[0x5]	7440	1			T20	1222		T40	27		T13	1
alert[0x6]	6108	1			T18	81		T11	1		T13	1
alert[0x7]	8343	1			T18	3656		T20	1007		T288	1
alert[0x8]	3500	1			T4	2		T40	49		T288	1
alert[0x9]	14935	1			T40	99		T30	680		T47	2
alert[0xa]	3604	1			T4	177		T40	904		T43	1
alert[0xb]	8313	1			T4	118		T18	69		T20	3337
alert[0xc]	6746	1			T14	1		T105	22		T290	1
alert[0xd]	10889	1			T4	28		T59	5		T40	51
alert[0xe]	8902	1			T7	3		T18	43		T65	9
alert[0xf]	8606	1			T9	3		T59	2		T13	1
alert[0x10]	10499	1			T4	2		T20	110		T39	465
alert[0x11]	5533	1			T20	93		T65	30		T40	184
alert[0x12]	2404	1			T7	1		T59	1		T13	2
alert[0x13]	4814	1			T7	3		T20	61		T12	1
alert[0x14]	7053	1			T20	1870		T39	232		T40	702
alert[0x15]	7443	1			T7	1		T18	1205		T20	11
alert[0x16]	9514	1			T4	3		T20	510		T26	6
alert[0x17]	3710	1			T7	2		T20	945		T40	16
alert[0x18]	4099	1			T4	893		T18	32		T59	6
alert[0x19]	3654	1			T4	60		T7	8		T18	404
alert[0x1a]	3006	1			T4	123		T7	99		T40	208
alert[0x1b]	11241	1			T18	25		T20	116		T14	1
alert[0x1c]	1517	1			T18	40		T12	1		T59	10
alert[0x1d]	3352	1			T7	2		T18	122		T60	2
alert[0x1e]	22441	1			T9	2		T12	1		T40	107
alert[0x1f]	5494	1			T4	3		T18	3109		T20	330
alert[0x20]	4825	1			T20	11		T12	1		T40	3
alert[0x21]	7562	1			T20	112		T40	4241		T105	7
alert[0x22]	9079	1			T18	333		T26	1		T39	105
alert[0x23]	3257	1			T18	125		T20	52		T12	1
alert[0x24]	2721	1			T40	207		T14	1		T288	1
alert[0x25]	2140	1			T4	24		T20	64		T37	1
alert[0x26]	3322	1			T4	42		T18	16		T14	1
alert[0x27]	4964	1			T18	16		T14	3		T44	28
alert[0x28]	3839	1			T4	1120		T18	77		T26	5
alert[0x29]	3866	1			T4	71		T18	311		T20	353
alert[0x2a]	14758	1			T18	691		T20	115		T37	9
alert[0x2b]	7897	1			T7	3		T18	32		T9	2
alert[0x2c]	2348	1			T7	2		T18	7		T9	29
alert[0x2d]	2371	1			T11	1		T26	23		T37	2
alert[0x2e]	4936	1			T4	15		T18	20		T20	106
alert[0x2f]	7086	1			T4	32		T18	225		T9	1
alert[0x30]	4897	1			T4	533		T18	239		T10	2
alert[0x31]	7520	1			T4	108		T20	34		T59	4
alert[0x32]	5332	1			T4	30		T26	1		T39	228
alert[0x33]	4437	1			T4	82		T39	1321		T105	1001
alert[0x34]	2906	1			T18	141		T12	1		T40	38
alert[0x35]	6504	1			T18	39		T20	478		T39	28
alert[0x36]	4555	1			T4	15		T18	1943		T60	9
alert[0x37]	12838	1			T20	5		T12	1		T13	1
alert[0x38]	5182	1			T4	8		T20	36		T65	1
alert[0x39]	2077	1			T4	89		T7	1		T12	1
alert[0x3a]	2789	1			T18	130		T12	1		T43	28
alert[0x3b]	1561	1			T4	28		T18	306		T20	21
alert[0x3c]	9997	1			T40	9		T13	1		T71	7983
alert[0x3d]	8275	1			T4	101		T18	998		T20	3028
alert[0x3e]	6783	1			T18	17		T20	44		T37	2
alert[0x3f]	7103	1			T20	97		T26	4		T260	1
alert[0x40]	5262	1			T4	639		T18	48		T71	118

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	81393	1			T4	37		T7	2		T18	20
class_i[0x1]	100007	1			T4	9		T7	41		T18	6889
class_i[0x2]	97852	1			T4	81		T7	7		T18	8346
class_i[0x3]	126460	1			T4	8575		T7	77		T18	76

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

404997

1

T4

8702

T7

127

T18

15331

alert_ping_fail

715

1

T10

5

T11

3

T12

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9722	1			T20	6326		T47	66		T73	1
alert_integrity_fail	alert[0x1]	7337	1			T4	2532		T105	437		T71	159
alert_integrity_fail	alert[0x2]	3494	1			T7	2		T30	291		T101	669
alert_integrity_fail	alert[0x3]	5850	1			T4	1820		T18	831		T105	66
alert_integrity_fail	alert[0x4]	3106	1			T4	4		T20	303		T259	5
alert_integrity_fail	alert[0x5]	7433	1			T20	1222		T40	27		T71	11
alert_integrity_fail	alert[0x6]	6091	1			T18	81		T71	827		T44	1
alert_integrity_fail	alert[0x7]	8326	1			T18	3656		T20	1007		T105	18
alert_integrity_fail	alert[0x8]	3485	1			T4	2		T40	49		T291	29
alert_integrity_fail	alert[0x9]	14922	1			T40	99		T30	680		T47	2
alert_integrity_fail	alert[0xa]	3591	1			T4	177		T40	904		T43	1
alert_integrity_fail	alert[0xb]	8302	1			T4	118		T18	69		T20	3337
alert_integrity_fail	alert[0xc]	6730	1			T105	22		T71	1202		T292	275
alert_integrity_fail	alert[0xd]	10875	1			T4	28		T59	5		T40	51
alert_integrity_fail	alert[0xe]	8894	1			T7	3		T18	43		T65	9
alert_integrity_fail	alert[0xf]	8590	1			T9	3		T59	2		T30	2154
alert_integrity_fail	alert[0x10]	10484	1			T4	2		T20	110		T39	465
alert_integrity_fail	alert[0x11]	5528	1			T20	93		T65	30		T40	184
alert_integrity_fail	alert[0x12]	2398	1			T7	1		T59	1		T71	175
alert_integrity_fail	alert[0x13]	4801	1			T7	3		T20	61		T105	8
alert_integrity_fail	alert[0x14]	7039	1			T20	1870		T39	232		T40	702
alert_integrity_fail	alert[0x15]	7434	1			T7	1		T18	1205		T20	11
alert_integrity_fail	alert[0x16]	9506	1			T4	3		T20	510		T26	6
alert_integrity_fail	alert[0x17]	3699	1			T7	2		T20	945		T40	16
alert_integrity_fail	alert[0x18]	4089	1			T4	893		T18	32		T59	6
alert_integrity_fail	alert[0x19]	3638	1			T4	60		T7	8		T18	404
alert_integrity_fail	alert[0x1a]	3001	1			T4	123		T7	99		T40	208
alert_integrity_fail	alert[0x1b]	11232	1			T18	25		T20	116		T105	2
alert_integrity_fail	alert[0x1c]	1503	1			T18	40		T59	10		T39	7
alert_integrity_fail	alert[0x1d]	3345	1			T7	2		T18	122		T60	2
alert_integrity_fail	alert[0x1e]	22434	1			T9	2		T40	107		T71	2945
alert_integrity_fail	alert[0x1f]	5480	1			T4	3		T18	3109		T20	330
alert_integrity_fail	alert[0x20]	4811	1			T20	11		T40	3		T71	98
alert_integrity_fail	alert[0x21]	7547	1			T20	112		T40	4241		T105	7
alert_integrity_fail	alert[0x22]	9065	1			T18	333		T26	1		T39	105
alert_integrity_fail	alert[0x23]	3244	1			T18	125		T20	52		T71	137
alert_integrity_fail	alert[0x24]	2715	1			T40	207		T105	18		T259	2
alert_integrity_fail	alert[0x25]	2128	1			T4	24		T20	64		T37	1
alert_integrity_fail	alert[0x26]	3312	1			T4	42		T18	16		T105	20
alert_integrity_fail	alert[0x27]	4950	1			T18	16		T44	28		T47	7
alert_integrity_fail	alert[0x28]	3830	1			T4	1120		T18	77		T26	5
alert_integrity_fail	alert[0x29]	3856	1			T4	71		T18	311		T20	353
alert_integrity_fail	alert[0x2a]	14747	1			T18	691		T20	115		T37	9
alert_integrity_fail	alert[0x2b]	7889	1			T7	3		T18	32		T9	2
alert_integrity_fail	alert[0x2c]	2330	1			T7	2		T18	7		T9	29
alert_integrity_fail	alert[0x2d]	2352	1			T26	23		T37	2		T40	57
alert_integrity_fail	alert[0x2e]	4926	1			T4	15		T18	20		T20	106
alert_integrity_fail	alert[0x2f]	7072	1			T4	32		T18	225		T9	1
alert_integrity_fail	alert[0x30]	4876	1			T4	533		T18	239		T60	4
alert_integrity_fail	alert[0x31]	7508	1			T4	108		T20	34		T59	4
alert_integrity_fail	alert[0x32]	5322	1			T4	30		T26	1		T39	228
alert_integrity_fail	alert[0x33]	4432	1			T4	82		T39	1321		T105	1001
alert_integrity_fail	alert[0x34]	2901	1			T18	141		T40	38		T30	461
alert_integrity_fail	alert[0x35]	6499	1			T18	39		T20	478		T39	28
alert_integrity_fail	alert[0x36]	4550	1			T4	15		T18	1943		T60	9
alert_integrity_fail	alert[0x37]	12823	1			T20	5		T73	15		T174	5
alert_integrity_fail	alert[0x38]	5175	1			T4	8		T20	36		T65	1
alert_integrity_fail	alert[0x39]	2067	1			T4	89		T7	1		T41	1
alert_integrity_fail	alert[0x3a]	2771	1			T18	130		T43	28		T71	18
alert_integrity_fail	alert[0x3b]	1547	1			T4	28		T18	306		T20	21
alert_integrity_fail	alert[0x3c]	9990	1			T40	9		T71	7983		T30	27
alert_integrity_fail	alert[0x3d]	8265	1			T4	101		T18	998		T20	3028
alert_integrity_fail	alert[0x3e]	6777	1			T18	17		T20	44		T37	2
alert_integrity_fail	alert[0x3f]	7102	1			T20	97		T26	4		T260	1
alert_integrity_fail	alert[0x40]	5259	1			T4	639		T18	48		T71	118
alert_ping_fail	alert[0x0]	9	1			T288	1		T289	1		T219	1
alert_ping_fail	alert[0x1]	11	1			T14	1		T289	1		T293	1
alert_ping_fail	alert[0x2]	12	1			T289	1		T217	1		T219	1
alert_ping_fail	alert[0x3]	15	1			T14	1		T294	1		T295	1
alert_ping_fail	alert[0x4]	7	1			T296	1		T295	1		T297	1
alert_ping_fail	alert[0x5]	7	1			T13	1		T180	1		T298	1
alert_ping_fail	alert[0x6]	17	1			T11	1		T13	1		T299	1
alert_ping_fail	alert[0x7]	17	1			T288	1		T282	1		T264	1
alert_ping_fail	alert[0x8]	15	1			T288	1		T284	1		T300	1
alert_ping_fail	alert[0x9]	13	1			T301	1		T302	1		T303	1
alert_ping_fail	alert[0xa]	13	1			T283	1		T289	1		T295	1
alert_ping_fail	alert[0xb]	11	1			T304	1		T305	1		T184	1
alert_ping_fail	alert[0xc]	16	1			T14	1		T290	1		T289	1
alert_ping_fail	alert[0xd]	14	1			T14	1		T306	2		T307	1
alert_ping_fail	alert[0xe]	8	1			T304	1		T307	1		T297	1
alert_ping_fail	alert[0xf]	16	1			T13	1		T306	1		T293	1
alert_ping_fail	alert[0x10]	15	1			T14	1		T290	1		T296	2
alert_ping_fail	alert[0x11]	5	1			T180	1		T308	1		T309	1
alert_ping_fail	alert[0x12]	6	1			T13	2		T289	1		T296	1
alert_ping_fail	alert[0x13]	13	1			T12	1		T289	1		T304	1
alert_ping_fail	alert[0x14]	14	1			T14	1		T288	1		T300	2
alert_ping_fail	alert[0x15]	9	1			T10	1		T11	1		T310	1
alert_ping_fail	alert[0x16]	8	1			T289	1		T299	1		T310	1
alert_ping_fail	alert[0x17]	11	1			T14	1		T288	3		T217	1
alert_ping_fail	alert[0x18]	10	1			T296	1		T311	1		T312	2
alert_ping_fail	alert[0x19]	16	1			T13	1		T290	1		T219	2
alert_ping_fail	alert[0x1a]	5	1			T14	1		T294	1		T295	1
alert_ping_fail	alert[0x1b]	9	1			T14	1		T302	1		T184	2
alert_ping_fail	alert[0x1c]	14	1			T12	1		T290	1		T296	2
alert_ping_fail	alert[0x1d]	7	1			T13	2		T290	1		T296	1
alert_ping_fail	alert[0x1e]	7	1			T12	1		T295	1		T313	1
alert_ping_fail	alert[0x1f]	14	1			T10	1		T263	1		T296	1
alert_ping_fail	alert[0x20]	14	1			T12	1		T288	1		T296	1
alert_ping_fail	alert[0x21]	15	1			T300	1		T301	1		T305	2
alert_ping_fail	alert[0x22]	14	1			T14	1		T290	1		T295	1
alert_ping_fail	alert[0x23]	13	1			T12	1		T288	1		T296	1
alert_ping_fail	alert[0x24]	6	1			T14	1		T288	1		T290	1
alert_ping_fail	alert[0x25]	12	1			T12	1		T219	1		T304	1
alert_ping_fail	alert[0x26]	10	1			T14	1		T299	1		T305	1
alert_ping_fail	alert[0x27]	14	1			T14	3		T289	1		T306	1
alert_ping_fail	alert[0x28]	9	1			T288	1		T296	1		T313	1
alert_ping_fail	alert[0x29]	10	1			T14	1		T304	1		T301	1
alert_ping_fail	alert[0x2a]	11	1			T14	1		T288	2		T307	1
alert_ping_fail	alert[0x2b]	8	1			T293	1		T301	1		T308	1
alert_ping_fail	alert[0x2c]	18	1			T13	1		T263	1		T314	1
alert_ping_fail	alert[0x2d]	19	1			T11	1		T12	1		T14	1
alert_ping_fail	alert[0x2e]	10	1			T13	1		T307	1		T305	1
alert_ping_fail	alert[0x2f]	14	1			T10	1		T13	2		T289	2
alert_ping_fail	alert[0x30]	21	1			T10	2		T14	1		T221	1
alert_ping_fail	alert[0x31]	12	1			T14	1		T296	1		T299	2
alert_ping_fail	alert[0x32]	10	1			T13	1		T289	1		T304	1
alert_ping_fail	alert[0x33]	5	1			T290	1		T289	1		T221	1
alert_ping_fail	alert[0x34]	5	1			T12	1		T14	1		T294	1
alert_ping_fail	alert[0x35]	5	1			T304	1		T294	1		T297	1
alert_ping_fail	alert[0x36]	5	1			T290	1		T302	1		T184	1
alert_ping_fail	alert[0x37]	15	1			T12	1		T13	1		T290	1
alert_ping_fail	alert[0x38]	7	1			T304	1		T294	1		T177	1
alert_ping_fail	alert[0x39]	10	1			T12	1		T294	1		T301	1
alert_ping_fail	alert[0x3a]	18	1			T12	1		T288	1		T217	1
alert_ping_fail	alert[0x3b]	14	1			T14	1		T299	1		T304	2
alert_ping_fail	alert[0x3c]	7	1			T13	1		T296	1		T306	1
alert_ping_fail	alert[0x3d]	10	1			T13	1		T221	1		T304	2
alert_ping_fail	alert[0x3e]	6	1			T288	1		T299	1		T315	1
alert_ping_fail	alert[0x3f]	1	1			T316	1		-	-		-	-
alert_ping_fail	alert[0x40]	3	1			T317	1		T318	1		T319	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	81241	1			T4	37		T7	2		T18	20
alert_integrity_fail	class_i[0x1]	99807	1			T4	9		T7	41		T18	6889
alert_integrity_fail	class_i[0x2]	97702	1			T4	81		T7	7		T18	8346
alert_integrity_fail	class_i[0x3]	126247	1			T4	8575		T7	77		T18	76
alert_ping_fail	class_i[0x0]	152	1			T11	3		T12	9		T13	1
alert_ping_fail	class_i[0x1]	200	1			T13	14		T14	21		T288	13
alert_ping_fail	class_i[0x2]	150	1			T10	5		T12	2		T13	1
alert_ping_fail	class_i[0x3]	213	1			T14	1		T290	1		T264	1