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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.70 100.00 100.00 100.00 99.38 99.60


Total test records in report: 831
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T777 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.494872628 Jul 07 04:46:54 PM PDT 24 Jul 07 04:47:00 PM PDT 24 62179444 ps
T119 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2047252571 Jul 07 04:46:47 PM PDT 24 Jul 07 04:49:51 PM PDT 24 15072889270 ps
T778 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1808715454 Jul 07 04:46:42 PM PDT 24 Jul 07 04:47:03 PM PDT 24 827998411 ps
T125 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4014392556 Jul 07 04:46:52 PM PDT 24 Jul 07 05:02:50 PM PDT 24 25233874473 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1500686726 Jul 07 04:46:52 PM PDT 24 Jul 07 04:47:07 PM PDT 24 368176475 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1689713154 Jul 07 04:46:41 PM PDT 24 Jul 07 04:46:49 PM PDT 24 111235464 ps
T781 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3826317067 Jul 07 04:47:21 PM PDT 24 Jul 07 04:47:23 PM PDT 24 8861754 ps
T782 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2691270405 Jul 07 04:47:16 PM PDT 24 Jul 07 04:47:17 PM PDT 24 10861084 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1821151296 Jul 07 04:46:52 PM PDT 24 Jul 07 04:47:08 PM PDT 24 368072606 ps
T139 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3455952253 Jul 07 04:46:51 PM PDT 24 Jul 07 04:49:44 PM PDT 24 8632590753 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.98430045 Jul 07 04:46:56 PM PDT 24 Jul 07 04:47:10 PM PDT 24 804027856 ps
T170 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2673214819 Jul 07 04:46:50 PM PDT 24 Jul 07 04:46:53 PM PDT 24 24285221 ps
T146 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2166050875 Jul 07 04:46:48 PM PDT 24 Jul 07 04:48:57 PM PDT 24 4145692579 ps
T162 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2139639946 Jul 07 04:46:38 PM PDT 24 Jul 07 04:47:11 PM PDT 24 451012646 ps
T785 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1861253150 Jul 07 04:47:12 PM PDT 24 Jul 07 04:47:14 PM PDT 24 8192397 ps
T173 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3080040577 Jul 07 04:47:06 PM PDT 24 Jul 07 04:47:11 PM PDT 24 62514660 ps
T786 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.498637661 Jul 07 04:47:12 PM PDT 24 Jul 07 04:47:14 PM PDT 24 10371585 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3550769280 Jul 07 04:46:39 PM PDT 24 Jul 07 05:02:21 PM PDT 24 120258535105 ps
T159 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.428886813 Jul 07 04:46:49 PM PDT 24 Jul 07 04:46:53 PM PDT 24 40790621 ps
T787 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1039671985 Jul 07 04:46:53 PM PDT 24 Jul 07 04:47:02 PM PDT 24 505145821 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2728500867 Jul 07 04:46:39 PM PDT 24 Jul 07 04:50:34 PM PDT 24 6532134910 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1854974328 Jul 07 04:46:39 PM PDT 24 Jul 07 04:50:11 PM PDT 24 8592103822 ps
T790 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.17484739 Jul 07 04:46:53 PM PDT 24 Jul 07 04:47:01 PM PDT 24 367349839 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4019709951 Jul 07 04:47:00 PM PDT 24 Jul 07 04:49:53 PM PDT 24 1655323526 ps
T161 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3845625047 Jul 07 04:47:02 PM PDT 24 Jul 07 04:47:39 PM PDT 24 324032807 ps
T792 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3396699562 Jul 07 04:47:17 PM PDT 24 Jul 07 04:47:32 PM PDT 24 197327244 ps
T793 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1408547825 Jul 07 04:47:18 PM PDT 24 Jul 07 04:47:19 PM PDT 24 57166035 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1697227903 Jul 07 04:46:53 PM PDT 24 Jul 07 04:47:32 PM PDT 24 2481845746 ps
T142 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1163457636 Jul 07 04:46:49 PM PDT 24 Jul 07 04:49:46 PM PDT 24 4116838299 ps
T135 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1831840959 Jul 07 04:46:53 PM PDT 24 Jul 07 05:01:34 PM PDT 24 47602214793 ps
T795 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.200567362 Jul 07 04:46:53 PM PDT 24 Jul 07 04:46:55 PM PDT 24 8096660 ps
T796 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1210655326 Jul 07 04:47:02 PM PDT 24 Jul 07 04:47:08 PM PDT 24 57911327 ps
T797 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.92503361 Jul 07 04:47:11 PM PDT 24 Jul 07 04:47:13 PM PDT 24 17705320 ps
T172 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2327296444 Jul 07 04:47:11 PM PDT 24 Jul 07 04:47:14 PM PDT 24 103146252 ps
T798 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2815777829 Jul 07 04:47:09 PM PDT 24 Jul 07 04:47:11 PM PDT 24 18182942 ps
T799 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.803893867 Jul 07 04:47:00 PM PDT 24 Jul 07 04:47:07 PM PDT 24 43391014 ps
T800 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3892683851 Jul 07 04:46:52 PM PDT 24 Jul 07 04:46:58 PM PDT 24 272805879 ps
T140 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2646834295 Jul 07 04:46:44 PM PDT 24 Jul 07 04:49:36 PM PDT 24 9616009487 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.291494834 Jul 07 04:46:50 PM PDT 24 Jul 07 04:47:11 PM PDT 24 1029146179 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2029665276 Jul 07 04:46:52 PM PDT 24 Jul 07 04:47:15 PM PDT 24 720233255 ps
T803 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2734237681 Jul 07 04:47:04 PM PDT 24 Jul 07 04:49:20 PM PDT 24 1637712804 ps
T134 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1576059891 Jul 07 04:46:53 PM PDT 24 Jul 07 04:57:13 PM PDT 24 48555717483 ps
T143 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1023100872 Jul 07 04:46:53 PM PDT 24 Jul 07 04:49:23 PM PDT 24 4136817658 ps
T804 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.362631576 Jul 07 04:47:03 PM PDT 24 Jul 07 04:47:29 PM PDT 24 1822524227 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3411479548 Jul 07 04:47:11 PM PDT 24 Jul 07 04:47:24 PM PDT 24 150250285 ps
T806 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2946827316 Jul 07 04:46:57 PM PDT 24 Jul 07 04:47:12 PM PDT 24 383665210 ps
T807 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3293915780 Jul 07 04:46:39 PM PDT 24 Jul 07 04:46:41 PM PDT 24 18523198 ps
T150 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1994064303 Jul 07 04:47:04 PM PDT 24 Jul 07 04:48:50 PM PDT 24 2977986506 ps
T808 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4035311291 Jul 07 04:47:19 PM PDT 24 Jul 07 04:47:21 PM PDT 24 51172379 ps
T809 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.519949220 Jul 07 04:46:49 PM PDT 24 Jul 07 04:46:54 PM PDT 24 111720948 ps
T123 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2804380524 Jul 07 04:46:55 PM PDT 24 Jul 07 04:59:05 PM PDT 24 17959021653 ps
T124 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.354389168 Jul 07 04:46:39 PM PDT 24 Jul 07 05:05:54 PM PDT 24 61891992402 ps
T810 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.323050598 Jul 07 04:47:19 PM PDT 24 Jul 07 04:47:22 PM PDT 24 16518650 ps
T811 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1928863373 Jul 07 04:47:12 PM PDT 24 Jul 07 04:47:14 PM PDT 24 9799532 ps
T812 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.233587363 Jul 07 04:47:22 PM PDT 24 Jul 07 04:47:24 PM PDT 24 10141308 ps
T813 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1520828475 Jul 07 04:47:20 PM PDT 24 Jul 07 04:47:22 PM PDT 24 44323870 ps
T160 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3640308421 Jul 07 04:46:52 PM PDT 24 Jul 07 04:47:16 PM PDT 24 163293210 ps
T814 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2576327355 Jul 07 04:47:19 PM PDT 24 Jul 07 04:47:20 PM PDT 24 44510367 ps
T815 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1205220347 Jul 07 04:47:03 PM PDT 24 Jul 07 04:47:26 PM PDT 24 1308030756 ps
T816 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1324433032 Jul 07 04:46:54 PM PDT 24 Jul 07 04:47:07 PM PDT 24 184932006 ps
T817 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.311629618 Jul 07 04:47:10 PM PDT 24 Jul 07 04:47:13 PM PDT 24 11559444 ps
T818 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.209315580 Jul 07 04:46:59 PM PDT 24 Jul 07 04:47:07 PM PDT 24 108998981 ps
T819 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3973866557 Jul 07 04:46:37 PM PDT 24 Jul 07 04:47:09 PM PDT 24 2772106227 ps
T148 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.57668517 Jul 07 04:46:48 PM PDT 24 Jul 07 04:56:14 PM PDT 24 13276189246 ps
T149 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1645396672 Jul 07 04:46:50 PM PDT 24 Jul 07 05:04:01 PM PDT 24 15052133242 ps
T820 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1274414873 Jul 07 04:47:26 PM PDT 24 Jul 07 04:47:28 PM PDT 24 71065292 ps
T821 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1876169343 Jul 07 04:47:10 PM PDT 24 Jul 07 04:47:12 PM PDT 24 143154233 ps
T822 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4111915702 Jul 07 04:47:00 PM PDT 24 Jul 07 04:47:12 PM PDT 24 683254586 ps
T158 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1343572308 Jul 07 04:47:05 PM PDT 24 Jul 07 04:48:20 PM PDT 24 2771453934 ps
T823 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.316748356 Jul 07 04:47:16 PM PDT 24 Jul 07 04:47:18 PM PDT 24 6311992 ps
T824 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1513681626 Jul 07 04:47:17 PM PDT 24 Jul 07 04:47:21 PM PDT 24 23454024 ps
T141 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2946327959 Jul 07 04:46:49 PM PDT 24 Jul 07 04:52:33 PM PDT 24 5300825286 ps
T825 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1697938465 Jul 07 04:47:06 PM PDT 24 Jul 07 04:47:30 PM PDT 24 350026757 ps
T151 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3852786243 Jul 07 04:47:07 PM PDT 24 Jul 07 04:50:25 PM PDT 24 10878735406 ps
T826 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1297147735 Jul 07 04:47:00 PM PDT 24 Jul 07 04:47:19 PM PDT 24 572515072 ps
T827 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3498588320 Jul 07 04:47:14 PM PDT 24 Jul 07 04:47:16 PM PDT 24 32018596 ps
T828 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2607940517 Jul 07 04:47:13 PM PDT 24 Jul 07 04:47:27 PM PDT 24 468809142 ps
T829 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2614385669 Jul 07 04:46:52 PM PDT 24 Jul 07 04:49:24 PM PDT 24 3858419677 ps
T830 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.651217113 Jul 07 04:46:51 PM PDT 24 Jul 07 04:47:06 PM PDT 24 220017604 ps
T831 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2604013160 Jul 07 04:46:51 PM PDT 24 Jul 07 04:46:58 PM PDT 24 115138062 ps
T145 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2139107377 Jul 07 04:47:00 PM PDT 24 Jul 07 04:58:43 PM PDT 24 7829491558 ps

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3411885013
Short name T24
Test name
Test status
Simulation time 566860856 ps
CPU time 27.92 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 256644 kb
Host smart-e144e7df-49fc-49a7-ab5f-b89dc0b63f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34118
85013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3411885013
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.71837308
Short name T18
Test name
Test status
Simulation time 34011893438 ps
CPU time 1963.4 seconds
Started Jul 07 04:48:38 PM PDT 24
Finished Jul 07 05:21:22 PM PDT 24
Peak memory 305956 kb
Host smart-96e0c136-c12b-4de3-9941-a697b969256c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71837308 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.71837308
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4170525748
Short name T5
Test name
Test status
Simulation time 1635767756 ps
CPU time 21.36 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 04:47:51 PM PDT 24
Peak memory 267728 kb
Host smart-bb2bbc9f-0301-4fd4-aeb2-4a4dba6dbd56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4170525748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4170525748
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2473311959
Short name T26
Test name
Test status
Simulation time 57388314886 ps
CPU time 3295.05 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 05:43:22 PM PDT 24
Peak memory 290132 kb
Host smart-3edcbc44-dff1-4e71-a244-893fa936e341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473311959 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2473311959
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2837283766
Short name T153
Test name
Test status
Simulation time 1453222855 ps
CPU time 46.92 seconds
Started Jul 07 04:46:44 PM PDT 24
Finished Jul 07 04:47:31 PM PDT 24
Peak memory 240276 kb
Host smart-44f4cbf6-fa07-4357-92c7-b835e6915244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2837283766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2837283766
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1729445192
Short name T79
Test name
Test status
Simulation time 215326201 ps
CPU time 12.06 seconds
Started Jul 07 04:47:42 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 249084 kb
Host smart-74e3ca44-5930-45dc-a41a-efa5a04c5830
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1729445192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1729445192
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.557550353
Short name T30
Test name
Test status
Simulation time 99656442953 ps
CPU time 1899.92 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 05:19:31 PM PDT 24
Peak memory 301956 kb
Host smart-11e6b62f-381a-4352-8de8-64d88ee80247
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557550353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.557550353
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3110710845
Short name T558
Test name
Test status
Simulation time 37716471943 ps
CPU time 2238.95 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 306168 kb
Host smart-0f935a56-9a32-4430-86f3-d58cdcc12dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110710845 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3110710845
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2730766340
Short name T133
Test name
Test status
Simulation time 9253965308 ps
CPU time 342.77 seconds
Started Jul 07 04:46:59 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 265640 kb
Host smart-83ef26dc-088a-40f8-b951-461ef20aa626
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2730766340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2730766340
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.835053060
Short name T284
Test name
Test status
Simulation time 135443321157 ps
CPU time 2058.29 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 289152 kb
Host smart-ecb59076-46a1-4d46-bc72-9e053c205b46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835053060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.835053060
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1519341822
Short name T7
Test name
Test status
Simulation time 44990719140 ps
CPU time 1883.99 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 05:19:33 PM PDT 24
Peak memory 306156 kb
Host smart-a2cf7971-73da-444c-a0aa-c2eac2ca88e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519341822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1519341822
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4038813662
Short name T239
Test name
Test status
Simulation time 21533828662 ps
CPU time 2172.62 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 05:23:41 PM PDT 24
Peak memory 304604 kb
Host smart-dcf7949d-d167-4a64-b40b-feab54b6c985
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038813662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4038813662
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2875573254
Short name T126
Test name
Test status
Simulation time 4435703182 ps
CPU time 836.51 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 05:01:02 PM PDT 24
Peak memory 265144 kb
Host smart-e61e45d5-9c67-4060-9e40-03d7438a00d0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875573254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2875573254
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2561356041
Short name T59
Test name
Test status
Simulation time 63056619237 ps
CPU time 3495.51 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 05:46:23 PM PDT 24
Peak memory 305900 kb
Host smart-4c11f5bd-6207-4f3f-8ac7-12fbe64acd92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561356041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2561356041
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4022237667
Short name T131
Test name
Test status
Simulation time 1613928550 ps
CPU time 190.6 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 265172 kb
Host smart-88639ca7-090b-4314-81d1-c6567add1512
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4022237667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4022237667
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2271574963
Short name T91
Test name
Test status
Simulation time 469410863090 ps
CPU time 8922.62 seconds
Started Jul 07 04:48:53 PM PDT 24
Finished Jul 07 07:17:37 PM PDT 24
Peak memory 338612 kb
Host smart-d9719fae-7fba-43d2-9090-cde8b5081bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271574963 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2271574963
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.750123921
Short name T14
Test name
Test status
Simulation time 15124178765 ps
CPU time 602.93 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:58:38 PM PDT 24
Peak memory 249112 kb
Host smart-56bb506c-79ed-4e22-ae81-1bf087fafbeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750123921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.750123921
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.864663237
Short name T132
Test name
Test status
Simulation time 24878816137 ps
CPU time 1070.26 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 05:04:42 PM PDT 24
Peak memory 265432 kb
Host smart-c728d867-cf27-4584-ab66-2609fd5eb887
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864663237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.864663237
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2450220940
Short name T10
Test name
Test status
Simulation time 51574470376 ps
CPU time 2976.65 seconds
Started Jul 07 04:47:55 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 289440 kb
Host smart-d64fcfbd-165a-43e4-8501-3f03ad2a178d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450220940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2450220940
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3530551518
Short name T343
Test name
Test status
Simulation time 35600353 ps
CPU time 1.62 seconds
Started Jul 07 04:47:24 PM PDT 24
Finished Jul 07 04:47:26 PM PDT 24
Peak memory 237292 kb
Host smart-060320d8-cf92-47ca-928d-2c85d07c8f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3530551518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3530551518
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2946327959
Short name T141
Test name
Test status
Simulation time 5300825286 ps
CPU time 342.65 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:52:33 PM PDT 24
Peak memory 270616 kb
Host smart-c5e78ea3-911f-4102-9cf9-0b4de93f2b8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2946327959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2946327959
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.205038421
Short name T304
Test name
Test status
Simulation time 13028698896 ps
CPU time 549.57 seconds
Started Jul 07 04:48:52 PM PDT 24
Finished Jul 07 04:58:02 PM PDT 24
Peak memory 249344 kb
Host smart-1ceb9764-10b5-4a66-bc98-f68d83e1147b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205038421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.205038421
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.354389168
Short name T124
Test name
Test status
Simulation time 61891992402 ps
CPU time 1154.47 seconds
Started Jul 07 04:46:39 PM PDT 24
Finished Jul 07 05:05:54 PM PDT 24
Peak memory 273424 kb
Host smart-a915011e-23b9-471e-8eae-ee4870a5d58d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354389168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.354389168
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1876550406
Short name T303
Test name
Test status
Simulation time 53766431084 ps
CPU time 3062.19 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 05:38:51 PM PDT 24
Peak memory 289888 kb
Host smart-aa5d4014-cf77-4cfc-810e-a1226ec04ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876550406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1876550406
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.553289464
Short name T174
Test name
Test status
Simulation time 65392192313 ps
CPU time 5605.68 seconds
Started Jul 07 04:47:39 PM PDT 24
Finished Jul 07 06:21:06 PM PDT 24
Peak memory 323440 kb
Host smart-47533926-af5d-45b9-a97d-e5daaa231916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553289464 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.553289464
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3550769280
Short name T147
Test name
Test status
Simulation time 120258535105 ps
CPU time 941.41 seconds
Started Jul 07 04:46:39 PM PDT 24
Finished Jul 07 05:02:21 PM PDT 24
Peak memory 265292 kb
Host smart-92b42d43-e837-48a8-9bf1-de6d33b70236
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550769280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3550769280
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2798109550
Short name T71
Test name
Test status
Simulation time 336990578193 ps
CPU time 3037.61 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 05:38:57 PM PDT 24
Peak memory 297968 kb
Host smart-7b1dc2ab-91ea-49c2-b774-1b65c7f24c56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798109550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2798109550
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1201912083
Short name T11
Test name
Test status
Simulation time 35960624743 ps
CPU time 1934.97 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 05:20:50 PM PDT 24
Peak memory 284744 kb
Host smart-effdc8fc-e071-4a17-af93-15307f3c321b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201912083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1201912083
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.569523666
Short name T41
Test name
Test status
Simulation time 242781524084 ps
CPU time 3578.52 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 05:47:08 PM PDT 24
Peak memory 288744 kb
Host smart-a44cb34a-1419-4180-8b1c-bd725f973182
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569523666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.569523666
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1538091214
Short name T137
Test name
Test status
Simulation time 3269299853 ps
CPU time 200.76 seconds
Started Jul 07 04:47:09 PM PDT 24
Finished Jul 07 04:50:31 PM PDT 24
Peak memory 272912 kb
Host smart-9268d304-cb9e-45da-9e08-d18327ecf900
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1538091214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1538091214
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.239118927
Short name T298
Test name
Test status
Simulation time 28423565562 ps
CPU time 1462.6 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:12:44 PM PDT 24
Peak memory 272992 kb
Host smart-bd588a13-0962-4981-ab81-4ac0b0fb3fae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239118927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.239118927
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.729653879
Short name T13
Test name
Test status
Simulation time 44044018379 ps
CPU time 468.59 seconds
Started Jul 07 04:47:24 PM PDT 24
Finished Jul 07 04:55:13 PM PDT 24
Peak memory 249216 kb
Host smart-96e39b60-20e3-4e9f-8b22-6d1ea02c510e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729653879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.729653879
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2278960939
Short name T116
Test name
Test status
Simulation time 5956313266 ps
CPU time 389.61 seconds
Started Jul 07 04:46:45 PM PDT 24
Finished Jul 07 04:53:15 PM PDT 24
Peak memory 265260 kb
Host smart-f26fb964-17c5-4b53-b507-86af5843e853
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2278960939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2278960939
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.979278632
Short name T347
Test name
Test status
Simulation time 11255881 ps
CPU time 1.6 seconds
Started Jul 07 04:46:50 PM PDT 24
Finished Jul 07 04:46:52 PM PDT 24
Peak memory 235436 kb
Host smart-cf732ad0-3b80-49ff-81b5-749fd7bd88ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=979278632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.979278632
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.166259590
Short name T42
Test name
Test status
Simulation time 32789199264 ps
CPU time 1291.68 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 05:09:22 PM PDT 24
Peak memory 273084 kb
Host smart-729d7aca-66ef-4d11-9beb-8d8c3176927a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166259590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.166259590
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3380021484
Short name T336
Test name
Test status
Simulation time 62641779237 ps
CPU time 2099.15 seconds
Started Jul 07 04:48:49 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 285636 kb
Host smart-db885da0-5a4e-4aae-a649-f8966ca5fb88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380021484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3380021484
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.633613494
Short name T52
Test name
Test status
Simulation time 66644925356 ps
CPU time 641.18 seconds
Started Jul 07 04:48:08 PM PDT 24
Finished Jul 07 04:58:49 PM PDT 24
Peak memory 272352 kb
Host smart-0ca99bc9-e025-4beb-8895-0a06cb5c693e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633613494 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.633613494
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.711129517
Short name T295
Test name
Test status
Simulation time 8239524320 ps
CPU time 357.52 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 04:54:06 PM PDT 24
Peak memory 249504 kb
Host smart-4e38d5e5-01fc-44fc-8b38-51555559f4e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711129517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.711129517
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1831840959
Short name T135
Test name
Test status
Simulation time 47602214793 ps
CPU time 880.01 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 05:01:34 PM PDT 24
Peak memory 272760 kb
Host smart-de00d2bf-a8c7-4242-bf85-ec2917526e8c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831840959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1831840959
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1196267652
Short name T323
Test name
Test status
Simulation time 79932935899 ps
CPU time 2409.83 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 05:27:58 PM PDT 24
Peak memory 290060 kb
Host smart-66fc4e8f-8a7f-4a58-bf84-f76e473dcf67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196267652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1196267652
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1838232623
Short name T245
Test name
Test status
Simulation time 76574638236 ps
CPU time 5068.88 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 06:12:54 PM PDT 24
Peak memory 306720 kb
Host smart-82589086-f995-423a-84c5-90cdc76f9e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838232623 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1838232623
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.711638587
Short name T191
Test name
Test status
Simulation time 42970333 ps
CPU time 3.34 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:05 PM PDT 24
Peak memory 237792 kb
Host smart-1a9cc19d-979e-40b1-a133-95d448800a37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=711638587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.711638587
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4021788468
Short name T288
Test name
Test status
Simulation time 53138389833 ps
CPU time 468.85 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:55:35 PM PDT 24
Peak memory 249244 kb
Host smart-7d6960f1-2427-4a58-9a30-07c23080bf6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021788468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4021788468
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1672140217
Short name T235
Test name
Test status
Simulation time 314633415079 ps
CPU time 3071.76 seconds
Started Jul 07 04:47:53 PM PDT 24
Finished Jul 07 05:39:05 PM PDT 24
Peak memory 290164 kb
Host smart-fb87ee42-734a-4f34-b369-7397133bf9b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672140217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1672140217
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1528321084
Short name T301
Test name
Test status
Simulation time 86246051542 ps
CPU time 283.53 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:52:57 PM PDT 24
Peak memory 249212 kb
Host smart-76f51754-346c-4e65-be82-b1a9d1888b26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528321084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1528321084
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1566965322
Short name T101
Test name
Test status
Simulation time 56088691849 ps
CPU time 5759.56 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 06:24:38 PM PDT 24
Peak memory 354856 kb
Host smart-cc65c9fe-9be0-440e-a060-9088153c553b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566965322 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1566965322
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1182060058
Short name T244
Test name
Test status
Simulation time 10629582885 ps
CPU time 616.63 seconds
Started Jul 07 04:48:53 PM PDT 24
Finished Jul 07 04:59:10 PM PDT 24
Peak memory 267320 kb
Host smart-8ee8c1c6-df25-41ba-ac5e-57f0f3753f0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182060058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1182060058
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1645396672
Short name T149
Test name
Test status
Simulation time 15052133242 ps
CPU time 1030.78 seconds
Started Jul 07 04:46:50 PM PDT 24
Finished Jul 07 05:04:01 PM PDT 24
Peak memory 271400 kb
Host smart-d0d97bdf-3820-453b-a3fc-001f82ce3d26
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645396672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1645396672
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2869665452
Short name T332
Test name
Test status
Simulation time 33861613481 ps
CPU time 1061.72 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 05:05:29 PM PDT 24
Peak memory 265552 kb
Host smart-a2481f07-a937-48ed-b858-342101426fff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869665452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2869665452
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1278582612
Short name T27
Test name
Test status
Simulation time 339214032769 ps
CPU time 2476.1 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 05:29:06 PM PDT 24
Peak memory 298508 kb
Host smart-49560d2d-fe74-4212-9c12-8bdf127ab217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278582612 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1278582612
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3657561171
Short name T207
Test name
Test status
Simulation time 197468507 ps
CPU time 3.17 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 04:47:26 PM PDT 24
Peak memory 249388 kb
Host smart-e2e6950c-208d-4236-9e7b-b4765b05fcc3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3657561171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3657561171
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3574386598
Short name T178
Test name
Test status
Simulation time 22081375 ps
CPU time 2.24 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 04:47:32 PM PDT 24
Peak memory 249476 kb
Host smart-b960f4f9-d083-4629-ad7c-cc6281f1b17b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574386598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3574386598
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3149445314
Short name T198
Test name
Test status
Simulation time 17861792 ps
CPU time 2.4 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 04:47:47 PM PDT 24
Peak memory 249432 kb
Host smart-99893151-60a9-46cd-9c40-cd2818554664
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3149445314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3149445314
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3056015657
Short name T201
Test name
Test status
Simulation time 44550302 ps
CPU time 2.52 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 249408 kb
Host smart-2fb150b5-d42d-4127-a016-1300837f193d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3056015657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3056015657
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3427393495
Short name T113
Test name
Test status
Simulation time 1991935656 ps
CPU time 216.93 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 04:50:28 PM PDT 24
Peak memory 266120 kb
Host smart-b71523f8-54c0-4f06-88bc-6e4a00c92976
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3427393495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3427393495
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.536698569
Short name T20
Test name
Test status
Simulation time 84493328191 ps
CPU time 1156.85 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 273760 kb
Host smart-9ec389f9-547f-4190-8dd8-5305f38dc43e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536698569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.536698569
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1607713584
Short name T311
Test name
Test status
Simulation time 79563291449 ps
CPU time 459.82 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:55:28 PM PDT 24
Peak memory 249212 kb
Host smart-18b8affe-c5c2-4e8c-9648-ddc4a2a3de79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607713584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1607713584
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3162627867
Short name T242
Test name
Test status
Simulation time 734970075 ps
CPU time 16.9 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:47:51 PM PDT 24
Peak memory 248488 kb
Host smart-94d38227-036d-4f17-8a9d-7a0dd6144a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626
27867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3162627867
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1848793540
Short name T547
Test name
Test status
Simulation time 42481789050 ps
CPU time 466.22 seconds
Started Jul 07 04:48:44 PM PDT 24
Finished Jul 07 04:56:31 PM PDT 24
Peak memory 256432 kb
Host smart-43abeef4-0c4c-424f-a6ae-0a5216068d3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848793540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1848793540
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.982719261
Short name T96
Test name
Test status
Simulation time 48561854101 ps
CPU time 2731.39 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 05:33:59 PM PDT 24
Peak memory 289692 kb
Host smart-d780bea2-be1d-45e4-adc7-1d3ac7290058
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982719261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.982719261
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.57668517
Short name T148
Test name
Test status
Simulation time 13276189246 ps
CPU time 565.81 seconds
Started Jul 07 04:46:48 PM PDT 24
Finished Jul 07 04:56:14 PM PDT 24
Peak memory 265288 kb
Host smart-2e3b2692-b02d-404c-8f20-3c6d8ada985d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57668517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.57668517
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2131895331
Short name T319
Test name
Test status
Simulation time 47693097194 ps
CPU time 442.31 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 04:54:44 PM PDT 24
Peak memory 249340 kb
Host smart-a61723b7-aa4b-4da0-b8e9-6507a0f096ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131895331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2131895331
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3093248863
Short name T338
Test name
Test status
Simulation time 16055451708 ps
CPU time 1519.19 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 05:12:48 PM PDT 24
Peak memory 288836 kb
Host smart-03c9d744-65be-4840-b349-da806d413ba4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093248863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3093248863
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3236278765
Short name T50
Test name
Test status
Simulation time 290337703 ps
CPU time 29.28 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 04:48:14 PM PDT 24
Peak memory 249132 kb
Host smart-efe6ef65-21f6-48a4-9f86-2455867457ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32362
78765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3236278765
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.931979573
Short name T423
Test name
Test status
Simulation time 1730555481 ps
CPU time 61.22 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:50 PM PDT 24
Peak memory 256968 kb
Host smart-e80a9623-cf5f-4148-b475-14154da1a026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93197
9573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.931979573
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4191996502
Short name T44
Test name
Test status
Simulation time 147835585 ps
CPU time 15.56 seconds
Started Jul 07 04:47:45 PM PDT 24
Finished Jul 07 04:48:01 PM PDT 24
Peak memory 256544 kb
Host smart-8a504fff-bb1f-4a73-96c6-006a641d3f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41919
96502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4191996502
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1902559193
Short name T276
Test name
Test status
Simulation time 245023140072 ps
CPU time 2058.5 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 300344 kb
Host smart-c8de0978-e452-488e-9d74-624f75df3ef8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902559193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1902559193
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2124427815
Short name T247
Test name
Test status
Simulation time 2858942690 ps
CPU time 51.56 seconds
Started Jul 07 04:47:50 PM PDT 24
Finished Jul 07 04:48:42 PM PDT 24
Peak memory 248984 kb
Host smart-6c784692-da78-4b2a-ad58-499875c3ddc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
27815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2124427815
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.62655522
Short name T60
Test name
Test status
Simulation time 327815709 ps
CPU time 23.83 seconds
Started Jul 07 04:48:05 PM PDT 24
Finished Jul 07 04:48:30 PM PDT 24
Peak memory 249028 kb
Host smart-a74ad479-cf5d-4377-a9f0-ef988949503d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62655
522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.62655522
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2969811348
Short name T210
Test name
Test status
Simulation time 42009535645 ps
CPU time 989.36 seconds
Started Jul 07 04:48:03 PM PDT 24
Finished Jul 07 05:04:32 PM PDT 24
Peak memory 273552 kb
Host smart-eba02cfb-7eba-4177-91a0-224ead5bf082
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969811348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2969811348
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1199545925
Short name T212
Test name
Test status
Simulation time 31363847257 ps
CPU time 1971.94 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 05:21:10 PM PDT 24
Peak memory 273680 kb
Host smart-b7e01958-dae6-4d42-b09c-8a4bcf7f5997
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199545925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1199545925
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1467478091
Short name T262
Test name
Test status
Simulation time 27411893779 ps
CPU time 1165.87 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 05:06:58 PM PDT 24
Peak memory 273468 kb
Host smart-ce9120bd-560a-4c79-ad88-016b402f9304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467478091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1467478091
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3230853678
Short name T316
Test name
Test status
Simulation time 8021637625 ps
CPU time 337.21 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 04:53:06 PM PDT 24
Peak memory 249040 kb
Host smart-e0440840-79fc-441b-a137-d00e965d038c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230853678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3230853678
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3199991344
Short name T236
Test name
Test status
Simulation time 909652478 ps
CPU time 31.96 seconds
Started Jul 07 04:48:52 PM PDT 24
Finished Jul 07 04:49:25 PM PDT 24
Peak memory 248652 kb
Host smart-a701b8e5-ad54-4636-8b21-a9c454688719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
91344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3199991344
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.428886813
Short name T159
Test name
Test status
Simulation time 40790621 ps
CPU time 3.42 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:46:53 PM PDT 24
Peak memory 237388 kb
Host smart-7b54be07-e699-4d90-b2a4-a0f5a3a6a243
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=428886813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.428886813
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3231034167
Short name T136
Test name
Test status
Simulation time 862460718 ps
CPU time 127.46 seconds
Started Jul 07 04:47:13 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 265156 kb
Host smart-52d40687-0064-4ae4-bb50-5601cfb735a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3231034167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3231034167
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1343572308
Short name T158
Test name
Test status
Simulation time 2771453934 ps
CPU time 74.28 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:48:20 PM PDT 24
Peak memory 240360 kb
Host smart-3a3da9e3-16ae-41b8-8f9f-fd39b782bf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1343572308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1343572308
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1023100872
Short name T143
Test name
Test status
Simulation time 4136817658 ps
CPU time 149.86 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 265232 kb
Host smart-e4e44158-9fb9-4620-9b1f-b6425685742c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1023100872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1023100872
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3015219792
Short name T152
Test name
Test status
Simulation time 587524711 ps
CPU time 39.85 seconds
Started Jul 07 04:46:59 PM PDT 24
Finished Jul 07 04:47:40 PM PDT 24
Peak memory 240344 kb
Host smart-a87edd20-fcf2-4d36-8c4e-01d75b9f91b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3015219792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3015219792
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3640308421
Short name T160
Test name
Test status
Simulation time 163293210 ps
CPU time 23.8 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:47:16 PM PDT 24
Peak memory 240736 kb
Host smart-004a4e99-7620-456a-9c72-8b286f39776e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3640308421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3640308421
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3845625047
Short name T161
Test name
Test status
Simulation time 324032807 ps
CPU time 36.76 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:39 PM PDT 24
Peak memory 240316 kb
Host smart-cc441db6-5977-4560-b1df-75152255d4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3845625047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3845625047
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3136851813
Short name T163
Test name
Test status
Simulation time 451498128 ps
CPU time 3.32 seconds
Started Jul 07 04:46:55 PM PDT 24
Finished Jul 07 04:46:59 PM PDT 24
Peak memory 237252 kb
Host smart-dd7e5b1e-01f3-4019-89bf-2d4747e04058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3136851813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3136851813
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3538527827
Short name T166
Test name
Test status
Simulation time 156672657 ps
CPU time 19.96 seconds
Started Jul 07 04:46:48 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 245596 kb
Host smart-b52cc378-c019-4060-8fa2-8afb04384b00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3538527827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3538527827
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2139639946
Short name T162
Test name
Test status
Simulation time 451012646 ps
CPU time 32.26 seconds
Started Jul 07 04:46:38 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 240352 kb
Host smart-06c59b39-b53d-455e-a62a-6501c35cd98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2139639946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2139639946
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.787495828
Short name T164
Test name
Test status
Simulation time 52523635 ps
CPU time 2.15 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:46:51 PM PDT 24
Peak memory 237804 kb
Host smart-f97ce6fa-871c-4530-90a9-088f98ef0574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=787495828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.787495828
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.541046317
Short name T167
Test name
Test status
Simulation time 184030462 ps
CPU time 2.36 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 238416 kb
Host smart-db91afa7-9542-43f8-9c1c-fcff9b4f668b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=541046317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.541046317
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2166050875
Short name T146
Test name
Test status
Simulation time 4145692579 ps
CPU time 129.02 seconds
Started Jul 07 04:46:48 PM PDT 24
Finished Jul 07 04:48:57 PM PDT 24
Peak memory 267776 kb
Host smart-54dba691-2c9e-46d9-a27e-ac2eb4416355
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2166050875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2166050875
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2171235970
Short name T154
Test name
Test status
Simulation time 116564755 ps
CPU time 3.14 seconds
Started Jul 07 04:47:07 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 236548 kb
Host smart-97af840f-4fb8-42c6-8abd-61618d4cdbed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2171235970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2171235970
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.4113958942
Short name T168
Test name
Test status
Simulation time 183006338 ps
CPU time 23.05 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:47:13 PM PDT 24
Peak memory 237600 kb
Host smart-1398d5af-c5e6-4726-844f-225bb1005f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4113958942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.4113958942
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2327296444
Short name T172
Test name
Test status
Simulation time 103146252 ps
CPU time 3.11 seconds
Started Jul 07 04:47:11 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 237376 kb
Host smart-c19988b5-f31a-43af-8e1f-3a7e44c5cb05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2327296444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2327296444
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3080040577
Short name T173
Test name
Test status
Simulation time 62514660 ps
CPU time 4.33 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 237384 kb
Host smart-298c285c-9e0d-4163-8ab6-5e93eb0f84fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3080040577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3080040577
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2673214819
Short name T170
Test name
Test status
Simulation time 24285221 ps
CPU time 2.41 seconds
Started Jul 07 04:46:50 PM PDT 24
Finished Jul 07 04:46:53 PM PDT 24
Peak memory 237692 kb
Host smart-b0ded452-67e4-4bd0-bf45-6df8eb9789ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2673214819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2673214819
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2734237681
Short name T803
Test name
Test status
Simulation time 1637712804 ps
CPU time 135.13 seconds
Started Jul 07 04:47:04 PM PDT 24
Finished Jul 07 04:49:20 PM PDT 24
Peak memory 240328 kb
Host smart-a40702b8-11e6-4180-9b97-15f01c05fcba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2734237681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2734237681
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2728500867
Short name T788
Test name
Test status
Simulation time 6532134910 ps
CPU time 235.21 seconds
Started Jul 07 04:46:39 PM PDT 24
Finished Jul 07 04:50:34 PM PDT 24
Peak memory 237420 kb
Host smart-34e7de00-c40e-4345-9d04-a72da8530335
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2728500867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2728500867
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1457608546
Short name T721
Test name
Test status
Simulation time 485553480 ps
CPU time 8.76 seconds
Started Jul 07 04:46:38 PM PDT 24
Finished Jul 07 04:46:47 PM PDT 24
Peak memory 240436 kb
Host smart-953686b0-0aaf-4bf0-879f-a2cdf7b0d2d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1457608546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1457608546
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1474263445
Short name T350
Test name
Test status
Simulation time 60996438 ps
CPU time 9.21 seconds
Started Jul 07 04:46:47 PM PDT 24
Finished Jul 07 04:46:56 PM PDT 24
Peak memory 249608 kb
Host smart-a6787ed3-2885-47cf-9d3d-ace24ca1318a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474263445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1474263445
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.519949220
Short name T809
Test name
Test status
Simulation time 111720948 ps
CPU time 4.56 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:46:54 PM PDT 24
Peak memory 237368 kb
Host smart-97cbc4b6-d1ee-43eb-9acb-1f2ed6d13dbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=519949220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.519949220
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3462939901
Short name T745
Test name
Test status
Simulation time 6871140 ps
CPU time 1.54 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 237400 kb
Host smart-a99db7a0-821b-4452-8577-6b4dd85da761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3462939901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3462939901
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.4200183555
Short name T722
Test name
Test status
Simulation time 490214103 ps
CPU time 18.14 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 245580 kb
Host smart-fe77bdb2-98bc-4dc9-9e46-ecd4f095d309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4200183555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.4200183555
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1163457636
Short name T142
Test name
Test status
Simulation time 4116838299 ps
CPU time 176.53 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:49:46 PM PDT 24
Peak memory 266252 kb
Host smart-21334c01-87c1-4016-9fbe-ccb0a6719cd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1163457636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1163457636
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.803893867
Short name T799
Test name
Test status
Simulation time 43391014 ps
CPU time 6.23 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 254840 kb
Host smart-a0f95066-2318-4e89-af45-4e66761c6085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=803893867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.803893867
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.915705547
Short name T775
Test name
Test status
Simulation time 1737361441 ps
CPU time 125.25 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:48:59 PM PDT 24
Peak memory 236972 kb
Host smart-cc174629-7a10-4964-b3c7-d9321efd25f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=915705547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.915705547
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2081533783
Short name T349
Test name
Test status
Simulation time 3404365429 ps
CPU time 214.87 seconds
Started Jul 07 04:46:58 PM PDT 24
Finished Jul 07 04:50:33 PM PDT 24
Peak memory 237256 kb
Host smart-e5505e0f-c6ca-4dd8-9f56-472387cf9806
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2081533783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2081533783
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1124124847
Short name T735
Test name
Test status
Simulation time 380257754 ps
CPU time 9.37 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:47:04 PM PDT 24
Peak memory 249020 kb
Host smart-02c42bf0-6194-4e72-b170-5c3f98e25fd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1124124847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1124124847
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.209315580
Short name T818
Test name
Test status
Simulation time 108998981 ps
CPU time 7.65 seconds
Started Jul 07 04:46:59 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 251792 kb
Host smart-d697e86c-f01d-43ea-942e-6eb1d145e337
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209315580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.209315580
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.299438264
Short name T750
Test name
Test status
Simulation time 113975792 ps
CPU time 5.51 seconds
Started Jul 07 04:47:01 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 240348 kb
Host smart-be7c1316-64d6-409e-ab3e-bb532c50dfbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=299438264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.299438264
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1928863373
Short name T811
Test name
Test status
Simulation time 9799532 ps
CPU time 1.53 seconds
Started Jul 07 04:47:12 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 237384 kb
Host smart-f0b62d2b-53b0-490f-90a2-6e60579d550f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1928863373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1928863373
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2029665276
Short name T802
Test name
Test status
Simulation time 720233255 ps
CPU time 23.2 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:47:15 PM PDT 24
Peak memory 240344 kb
Host smart-16d6ef94-20d7-423a-a005-c694517f4da2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2029665276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2029665276
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2675590576
Short name T728
Test name
Test status
Simulation time 36156966 ps
CPU time 5.2 seconds
Started Jul 07 04:46:41 PM PDT 24
Finished Jul 07 04:46:47 PM PDT 24
Peak memory 248688 kb
Host smart-fdfe7341-6704-48c0-a424-63f517749ced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2675590576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2675590576
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1099023481
Short name T707
Test name
Test status
Simulation time 116635667 ps
CPU time 9.46 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:47:03 PM PDT 24
Peak memory 239076 kb
Host smart-b21230f1-3eee-4c07-b046-9444fc419bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099023481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1099023481
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1851059453
Short name T169
Test name
Test status
Simulation time 62922064 ps
CPU time 5.53 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:46:55 PM PDT 24
Peak memory 240332 kb
Host smart-a1334dab-232a-4ab6-997e-b7dcc0cff986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1851059453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1851059453
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3322361707
Short name T346
Test name
Test status
Simulation time 9459775 ps
CPU time 1.39 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:04 PM PDT 24
Peak memory 236408 kb
Host smart-8991af80-80ad-4fc4-b719-4286f410fce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3322361707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3322361707
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3980526232
Short name T718
Test name
Test status
Simulation time 330896068 ps
CPU time 25.99 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:33 PM PDT 24
Peak memory 245584 kb
Host smart-18ed4481-4b6b-40e9-b552-27c0af7c37aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3980526232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3980526232
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1107068879
Short name T117
Test name
Test status
Simulation time 8055561153 ps
CPU time 172.58 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:49:58 PM PDT 24
Peak memory 265240 kb
Host smart-964e9948-8802-4bd9-9a5c-939933fe5037
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1107068879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1107068879
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3664734098
Short name T762
Test name
Test status
Simulation time 119824647 ps
CPU time 6.9 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:46:59 PM PDT 24
Peak memory 254472 kb
Host smart-e9bb126e-15d3-42ff-8c3c-910242dd6454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3664734098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3664734098
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1663487593
Short name T737
Test name
Test status
Simulation time 507116969 ps
CPU time 11.09 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:47:01 PM PDT 24
Peak memory 239268 kb
Host smart-b4d66d19-e120-4ec5-8b8b-30dee12bcbb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663487593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1663487593
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1039671985
Short name T787
Test name
Test status
Simulation time 505145821 ps
CPU time 9.43 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:47:02 PM PDT 24
Peak memory 237420 kb
Host smart-4753747c-f45d-4387-b029-d720b3ecd6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1039671985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1039671985
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2910708456
Short name T344
Test name
Test status
Simulation time 21657833 ps
CPU time 1.41 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:46:55 PM PDT 24
Peak memory 236384 kb
Host smart-9f7d7986-7e8b-430b-af21-c099f5970e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2910708456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2910708456
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1808715454
Short name T778
Test name
Test status
Simulation time 827998411 ps
CPU time 20.57 seconds
Started Jul 07 04:46:42 PM PDT 24
Finished Jul 07 04:47:03 PM PDT 24
Peak memory 244628 kb
Host smart-b736ca1c-ab7e-4c73-80c6-d0436fb2a26b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1808715454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1808715454
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3455952253
Short name T139
Test name
Test status
Simulation time 8632590753 ps
CPU time 172.12 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 04:49:44 PM PDT 24
Peak memory 265236 kb
Host smart-17778613-1c26-41c3-8ed9-00bd7759bd38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3455952253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3455952253
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1077481420
Short name T120
Test name
Test status
Simulation time 7388088655 ps
CPU time 471.63 seconds
Started Jul 07 04:46:58 PM PDT 24
Finished Jul 07 04:54:50 PM PDT 24
Peak memory 265224 kb
Host smart-68b0e806-9f9d-4931-81e6-6da4a8c4f46b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077481420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1077481420
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.651217113
Short name T830
Test name
Test status
Simulation time 220017604 ps
CPU time 14.2 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 04:47:06 PM PDT 24
Peak memory 250908 kb
Host smart-e811b032-108a-4ca2-9b64-1eecc89d6d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=651217113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.651217113
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1697227903
Short name T794
Test name
Test status
Simulation time 2481845746 ps
CPU time 38.71 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:47:32 PM PDT 24
Peak memory 240356 kb
Host smart-c269a5d0-0799-4558-b65d-f55e97227a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1697227903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1697227903
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1210655326
Short name T796
Test name
Test status
Simulation time 57911327 ps
CPU time 4.88 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 239768 kb
Host smart-c06d85f8-dd44-4aa1-9216-58626094772e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210655326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1210655326
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.481048972
Short name T769
Test name
Test status
Simulation time 130935410 ps
CPU time 9.81 seconds
Started Jul 07 04:47:12 PM PDT 24
Finished Jul 07 04:47:22 PM PDT 24
Peak memory 237384 kb
Host smart-f5cec9ee-b2ce-4d80-bb09-e5f01f2739da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=481048972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.481048972
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.200567362
Short name T795
Test name
Test status
Simulation time 8096660 ps
CPU time 1.39 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:46:55 PM PDT 24
Peak memory 236420 kb
Host smart-5da42719-2778-4ac0-bfec-9198a9534bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=200567362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.200567362
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1205220347
Short name T815
Test name
Test status
Simulation time 1308030756 ps
CPU time 22.65 seconds
Started Jul 07 04:47:03 PM PDT 24
Finished Jul 07 04:47:26 PM PDT 24
Peak memory 240352 kb
Host smart-8c60c9cc-5b13-4d84-b9a2-f7ac4ed2ee54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1205220347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1205220347
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2238449525
Short name T118
Test name
Test status
Simulation time 9294744656 ps
CPU time 356.34 seconds
Started Jul 07 04:47:04 PM PDT 24
Finished Jul 07 04:53:01 PM PDT 24
Peak memory 265224 kb
Host smart-3d27610d-4250-4ef4-8b1d-f7cdb43c0ec3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238449525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2238449525
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1684387859
Short name T706
Test name
Test status
Simulation time 679208805 ps
CPU time 22.26 seconds
Started Jul 07 04:46:55 PM PDT 24
Finished Jul 07 04:47:18 PM PDT 24
Peak memory 248612 kb
Host smart-cc908cd3-9c81-4019-b1b0-be5342fb1093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1684387859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1684387859
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3208999952
Short name T736
Test name
Test status
Simulation time 305729328 ps
CPU time 6.44 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:46:59 PM PDT 24
Peak memory 240900 kb
Host smart-373045eb-09cc-4589-9ba4-7641d353aa0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208999952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3208999952
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.494872628
Short name T777
Test name
Test status
Simulation time 62179444 ps
CPU time 5.71 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:47:00 PM PDT 24
Peak memory 237348 kb
Host smart-84b98146-28b9-493f-92d4-249ee5b35ed1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=494872628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.494872628
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.729880559
Short name T739
Test name
Test status
Simulation time 14852816 ps
CPU time 1.46 seconds
Started Jul 07 04:47:09 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 237388 kb
Host smart-cb9eac54-bdce-49ce-b83c-b422069d1d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=729880559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.729880559
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3653833279
Short name T188
Test name
Test status
Simulation time 786604675 ps
CPU time 43.81 seconds
Started Jul 07 04:47:03 PM PDT 24
Finished Jul 07 04:47:47 PM PDT 24
Peak memory 248532 kb
Host smart-599f4c1b-18d0-4e87-8ba8-88826c915b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3653833279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3653833279
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1412768391
Short name T138
Test name
Test status
Simulation time 4228789203 ps
CPU time 316.19 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:52:11 PM PDT 24
Peak memory 271272 kb
Host smart-f6130b62-be65-4127-8324-b165b9d6b033
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1412768391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1412768391
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1434230379
Short name T715
Test name
Test status
Simulation time 195197877 ps
CPU time 8.07 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 251740 kb
Host smart-964ed5f1-10d1-4e20-a67b-efd7e306744a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434230379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1434230379
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1393931946
Short name T757
Test name
Test status
Simulation time 61651910 ps
CPU time 6.18 seconds
Started Jul 07 04:47:04 PM PDT 24
Finished Jul 07 04:47:10 PM PDT 24
Peak memory 249008 kb
Host smart-0c410c3e-ce65-4095-885b-0fb2f6dc3e19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393931946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1393931946
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4172783596
Short name T744
Test name
Test status
Simulation time 348930959 ps
CPU time 5.23 seconds
Started Jul 07 04:47:10 PM PDT 24
Finished Jul 07 04:47:16 PM PDT 24
Peak memory 237476 kb
Host smart-69c68cfa-1931-4320-95b7-f45b540e4175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4172783596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4172783596
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1877456598
Short name T724
Test name
Test status
Simulation time 3426165520 ps
CPU time 21.86 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:25 PM PDT 24
Peak memory 245656 kb
Host smart-5d1ff16a-14ef-4f56-9d8d-0dfe19212296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1877456598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1877456598
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2639131684
Short name T130
Test name
Test status
Simulation time 54531194786 ps
CPU time 930.05 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 05:02:28 PM PDT 24
Peak memory 265420 kb
Host smart-7d59ff68-0649-478f-9880-679c69b09d21
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639131684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2639131684
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.98430045
Short name T784
Test name
Test status
Simulation time 804027856 ps
CPU time 14.04 seconds
Started Jul 07 04:46:56 PM PDT 24
Finished Jul 07 04:47:10 PM PDT 24
Peak memory 253768 kb
Host smart-a2d73bc1-662d-4cea-8e6c-70b18bbbe414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=98430045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.98430045
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3594325505
Short name T733
Test name
Test status
Simulation time 138550346 ps
CPU time 5.73 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:12 PM PDT 24
Peak memory 248652 kb
Host smart-04bed4fa-d947-4e45-ac54-31239d2fa7a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594325505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3594325505
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1215522773
Short name T716
Test name
Test status
Simulation time 43576859 ps
CPU time 3.41 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 236384 kb
Host smart-b76a7761-43b4-4f2b-822b-9ef925d91a21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1215522773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1215522773
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1102458571
Short name T156
Test name
Test status
Simulation time 11988896 ps
CPU time 1.35 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 04:46:59 PM PDT 24
Peak memory 236452 kb
Host smart-2d25dbf4-8a93-4639-a14d-543beca56a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102458571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1102458571
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.362631576
Short name T804
Test name
Test status
Simulation time 1822524227 ps
CPU time 25.96 seconds
Started Jul 07 04:47:03 PM PDT 24
Finished Jul 07 04:47:29 PM PDT 24
Peak memory 245656 kb
Host smart-c0311178-00a9-4e7c-ba80-59a0d0af3246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362631576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.362631576
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3852786243
Short name T151
Test name
Test status
Simulation time 10878735406 ps
CPU time 197.6 seconds
Started Jul 07 04:47:07 PM PDT 24
Finished Jul 07 04:50:25 PM PDT 24
Peak memory 265296 kb
Host smart-c55e1edd-92e3-4b05-99fd-22790b1f27c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3852786243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3852786243
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4048686831
Short name T127
Test name
Test status
Simulation time 49951339706 ps
CPU time 1075.24 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 05:04:48 PM PDT 24
Peak memory 273300 kb
Host smart-d632fd69-8fc5-4dd1-98f3-4f90098353ec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048686831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4048686831
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2437566115
Short name T740
Test name
Test status
Simulation time 215712468 ps
CPU time 15.52 seconds
Started Jul 07 04:46:58 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 254496 kb
Host smart-e6eb7dbe-49fb-4e4b-91bc-ab70b0405c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2437566115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2437566115
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.215363111
Short name T748
Test name
Test status
Simulation time 122239884 ps
CPU time 5.27 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 248684 kb
Host smart-1a501a52-8ff3-44ce-99c1-f04518c54e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215363111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.215363111
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1519116074
Short name T763
Test name
Test status
Simulation time 176890887 ps
CPU time 8.06 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 240388 kb
Host smart-dac2a05a-f658-49ab-83ef-209c2b7abade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1519116074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1519116074
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1123901637
Short name T731
Test name
Test status
Simulation time 7250660 ps
CPU time 1.65 seconds
Started Jul 07 04:47:04 PM PDT 24
Finished Jul 07 04:47:06 PM PDT 24
Peak memory 237436 kb
Host smart-f68286f8-e80f-444d-9450-432cf56b36fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1123901637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1123901637
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.740359770
Short name T717
Test name
Test status
Simulation time 2129669372 ps
CPU time 35.91 seconds
Started Jul 07 04:47:04 PM PDT 24
Finished Jul 07 04:47:41 PM PDT 24
Peak memory 245596 kb
Host smart-a1f0f4e8-b750-4569-bcc7-e2825fbd90c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=740359770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.740359770
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1635808247
Short name T129
Test name
Test status
Simulation time 885923868 ps
CPU time 116.24 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:49:03 PM PDT 24
Peak memory 256960 kb
Host smart-b3f64e5c-daeb-4a39-9049-2570eaa63eca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1635808247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1635808247
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3752857918
Short name T729
Test name
Test status
Simulation time 590811978 ps
CPU time 10.73 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 254716 kb
Host smart-3cb2f29d-de1b-491a-bcd8-43b2d9282ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3752857918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3752857918
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2663296003
Short name T768
Test name
Test status
Simulation time 235373970 ps
CPU time 8.67 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 238464 kb
Host smart-26a9f817-d9a2-4163-8733-f6300344a818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663296003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2663296003
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1513681626
Short name T824
Test name
Test status
Simulation time 23454024 ps
CPU time 3.45 seconds
Started Jul 07 04:47:17 PM PDT 24
Finished Jul 07 04:47:21 PM PDT 24
Peak memory 236428 kb
Host smart-7f191e46-62a6-4b4f-b605-2ceb2b2e3ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1513681626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1513681626
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1767960549
Short name T741
Test name
Test status
Simulation time 80722956 ps
CPU time 1.37 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 237260 kb
Host smart-411fed07-fc96-4463-89cc-0fee058412a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1767960549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1767960549
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1697938465
Short name T825
Test name
Test status
Simulation time 350026757 ps
CPU time 22.87 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:30 PM PDT 24
Peak memory 248532 kb
Host smart-b81c5116-5798-4421-8045-74b6d5541f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1697938465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1697938465
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1184372473
Short name T122
Test name
Test status
Simulation time 15954938165 ps
CPU time 278.84 seconds
Started Jul 07 04:47:11 PM PDT 24
Finished Jul 07 04:51:50 PM PDT 24
Peak memory 265268 kb
Host smart-fd11f4b2-dcc3-493a-a45c-73a89b82e6ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1184372473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1184372473
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1719213077
Short name T121
Test name
Test status
Simulation time 14642285350 ps
CPU time 1119.67 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 05:05:43 PM PDT 24
Peak memory 273360 kb
Host smart-4893487c-5dfa-47cf-9e5f-f5b51582f677
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719213077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1719213077
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.96835442
Short name T713
Test name
Test status
Simulation time 95415746 ps
CPU time 10.61 seconds
Started Jul 07 04:47:09 PM PDT 24
Finished Jul 07 04:47:20 PM PDT 24
Peak memory 249720 kb
Host smart-105bdea7-2d05-408b-ad38-8b575b2640f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=96835442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.96835442
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3411479548
Short name T805
Test name
Test status
Simulation time 150250285 ps
CPU time 12.82 seconds
Started Jul 07 04:47:11 PM PDT 24
Finished Jul 07 04:47:24 PM PDT 24
Peak memory 252120 kb
Host smart-91e00ab0-9487-4460-b78f-2057865205af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411479548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3411479548
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3870280657
Short name T725
Test name
Test status
Simulation time 21418668 ps
CPU time 3.46 seconds
Started Jul 07 04:47:09 PM PDT 24
Finished Jul 07 04:47:12 PM PDT 24
Peak memory 240216 kb
Host smart-8d5ecac5-f673-4c6f-b4c1-8fb7aaf57334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3870280657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3870280657
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.663805759
Short name T727
Test name
Test status
Simulation time 7720093 ps
CPU time 1.41 seconds
Started Jul 07 04:47:07 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 237428 kb
Host smart-2bf60fc9-53b9-4d51-a45f-71377af97c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=663805759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.663805759
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.306147750
Short name T186
Test name
Test status
Simulation time 677003825 ps
CPU time 25.02 seconds
Started Jul 07 04:47:09 PM PDT 24
Finished Jul 07 04:47:34 PM PDT 24
Peak memory 245596 kb
Host smart-348c1be1-1ff4-427f-91ac-37ea96758c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=306147750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.306147750
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2139107377
Short name T145
Test name
Test status
Simulation time 7829491558 ps
CPU time 702.19 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:58:43 PM PDT 24
Peak memory 272532 kb
Host smart-b7cb33cd-9541-4d48-877c-433e1a7bfb97
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139107377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2139107377
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3396699562
Short name T792
Test name
Test status
Simulation time 197327244 ps
CPU time 14.59 seconds
Started Jul 07 04:47:17 PM PDT 24
Finished Jul 07 04:47:32 PM PDT 24
Peak memory 247860 kb
Host smart-c80feca7-f43b-4f64-a952-fe95663754a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3396699562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3396699562
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1876169343
Short name T821
Test name
Test status
Simulation time 143154233 ps
CPU time 2.06 seconds
Started Jul 07 04:47:10 PM PDT 24
Finished Jul 07 04:47:12 PM PDT 24
Peak memory 237436 kb
Host smart-aab5dea4-48b5-452d-a03f-ecf5ff8b3cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1876169343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1876169343
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2635694792
Short name T776
Test name
Test status
Simulation time 35824134 ps
CPU time 5.05 seconds
Started Jul 07 04:47:10 PM PDT 24
Finished Jul 07 04:47:16 PM PDT 24
Peak memory 248640 kb
Host smart-d1c78dc3-8934-4514-9b16-f8a13153d22f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635694792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2635694792
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3049567250
Short name T711
Test name
Test status
Simulation time 66268790 ps
CPU time 3.34 seconds
Started Jul 07 04:47:14 PM PDT 24
Finished Jul 07 04:47:18 PM PDT 24
Peak memory 240316 kb
Host smart-40dcc8a6-851d-4390-a82b-36a0d8042bf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3049567250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3049567250
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.337598965
Short name T712
Test name
Test status
Simulation time 23876348 ps
CPU time 1.51 seconds
Started Jul 07 04:47:12 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 236456 kb
Host smart-2c30b2be-0def-4ef3-8c1b-28a358c6a393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=337598965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.337598965
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2979445411
Short name T773
Test name
Test status
Simulation time 345345741 ps
CPU time 23.02 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:30 PM PDT 24
Peak memory 248552 kb
Host smart-9d92b428-4bfb-47fe-8d4f-6784b77ea132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2979445411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2979445411
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1413380570
Short name T115
Test name
Test status
Simulation time 3677106260 ps
CPU time 371.38 seconds
Started Jul 07 04:47:03 PM PDT 24
Finished Jul 07 04:53:15 PM PDT 24
Peak memory 266232 kb
Host smart-4273e07f-2e6a-47f5-9b1f-3ec538cc5708
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413380570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1413380570
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2607940517
Short name T828
Test name
Test status
Simulation time 468809142 ps
CPU time 13.49 seconds
Started Jul 07 04:47:13 PM PDT 24
Finished Jul 07 04:47:27 PM PDT 24
Peak memory 248752 kb
Host smart-835a9774-0f1a-4c46-9f8b-3e59c9b8a066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2607940517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2607940517
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4065067042
Short name T764
Test name
Test status
Simulation time 15557931359 ps
CPU time 150.42 seconds
Started Jul 07 04:46:39 PM PDT 24
Finished Jul 07 04:49:10 PM PDT 24
Peak memory 240408 kb
Host smart-75f40525-d968-4289-8b26-957d7015aa7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4065067042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4065067042
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3663465292
Short name T732
Test name
Test status
Simulation time 11409582602 ps
CPU time 405.86 seconds
Started Jul 07 04:47:01 PM PDT 24
Finished Jul 07 04:53:47 PM PDT 24
Peak memory 240404 kb
Host smart-c7fed8e0-afe8-448d-8f7d-23b77613d77c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3663465292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3663465292
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3060644708
Short name T719
Test name
Test status
Simulation time 108340763 ps
CPU time 4.98 seconds
Started Jul 07 04:46:46 PM PDT 24
Finished Jul 07 04:46:51 PM PDT 24
Peak memory 248532 kb
Host smart-ed99b759-06bb-448d-8db3-f137fab2d34b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3060644708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3060644708
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1423747480
Short name T710
Test name
Test status
Simulation time 149130628 ps
CPU time 6.83 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 239796 kb
Host smart-5973e985-081a-47c5-b188-52a073302022
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423747480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1423747480
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1995630643
Short name T738
Test name
Test status
Simulation time 125670816 ps
CPU time 3.47 seconds
Started Jul 07 04:46:36 PM PDT 24
Finished Jul 07 04:46:40 PM PDT 24
Peak memory 240312 kb
Host smart-dabe6239-b4a9-40ab-94d5-a46b1b355ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1995630643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1995630643
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1291756816
Short name T155
Test name
Test status
Simulation time 7025759 ps
CPU time 1.48 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 04:46:59 PM PDT 24
Peak memory 237136 kb
Host smart-e733a7a2-4e50-4d8d-ba14-8bec24b4be07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1291756816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1291756816
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3255035429
Short name T708
Test name
Test status
Simulation time 91055844 ps
CPU time 12.57 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 248568 kb
Host smart-db144824-3031-4ff2-a234-3bc7605b846c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3255035429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3255035429
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2614385669
Short name T829
Test name
Test status
Simulation time 3858419677 ps
CPU time 151.27 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:49:24 PM PDT 24
Peak memory 266180 kb
Host smart-bc915b74-5628-4d0d-a767-13db3d45fb77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2614385669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2614385669
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1821151296
Short name T783
Test name
Test status
Simulation time 368072606 ps
CPU time 14.97 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:47:08 PM PDT 24
Peak memory 246900 kb
Host smart-257c6670-5e99-4760-84be-75b3a6baae35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1821151296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1821151296
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1861253150
Short name T785
Test name
Test status
Simulation time 8192397 ps
CPU time 1.45 seconds
Started Jul 07 04:47:12 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 237396 kb
Host smart-dcb2b1f1-5249-418e-ba21-d46ef753b07b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1861253150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1861253150
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2815777829
Short name T798
Test name
Test status
Simulation time 18182942 ps
CPU time 1.48 seconds
Started Jul 07 04:47:09 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 237404 kb
Host smart-a921951e-133d-4925-a360-21742440c70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2815777829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2815777829
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1505642233
Short name T157
Test name
Test status
Simulation time 23162973 ps
CPU time 1.38 seconds
Started Jul 07 04:47:21 PM PDT 24
Finished Jul 07 04:47:23 PM PDT 24
Peak memory 235464 kb
Host smart-cceb19c9-1791-4fb8-9a20-47f118beaab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1505642233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1505642233
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.311629618
Short name T817
Test name
Test status
Simulation time 11559444 ps
CPU time 1.69 seconds
Started Jul 07 04:47:10 PM PDT 24
Finished Jul 07 04:47:13 PM PDT 24
Peak memory 236416 kb
Host smart-fa9cbbd6-2011-4d07-a5d5-89e07c1ac599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311629618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.311629618
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3319756838
Short name T755
Test name
Test status
Simulation time 10069682 ps
CPU time 1.74 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 236480 kb
Host smart-808da1cf-4a06-49f9-9f4e-e7d548ba6e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3319756838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3319756838
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2828308924
Short name T770
Test name
Test status
Simulation time 10205551 ps
CPU time 1.4 seconds
Started Jul 07 04:47:06 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 237404 kb
Host smart-6744fcc7-2fe7-4b43-8d01-127ae61295c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2828308924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2828308924
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.498637661
Short name T786
Test name
Test status
Simulation time 10371585 ps
CPU time 1.31 seconds
Started Jul 07 04:47:12 PM PDT 24
Finished Jul 07 04:47:14 PM PDT 24
Peak memory 236424 kb
Host smart-761323e6-2e52-492b-b54c-a82253e7c047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498637661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.498637661
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1441436852
Short name T342
Test name
Test status
Simulation time 11363080 ps
CPU time 1.59 seconds
Started Jul 07 04:47:16 PM PDT 24
Finished Jul 07 04:47:18 PM PDT 24
Peak memory 237492 kb
Host smart-86c4f558-c867-4590-9c7e-c3621fc4849d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1441436852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1441436852
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2090802895
Short name T348
Test name
Test status
Simulation time 26113602 ps
CPU time 1.4 seconds
Started Jul 07 04:47:13 PM PDT 24
Finished Jul 07 04:47:16 PM PDT 24
Peak memory 236428 kb
Host smart-f84bf7c6-acfd-4421-b1e0-ad162c0c71e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2090802895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2090802895
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3118562196
Short name T345
Test name
Test status
Simulation time 14739121 ps
CPU time 1.58 seconds
Started Jul 07 04:47:19 PM PDT 24
Finished Jul 07 04:47:20 PM PDT 24
Peak memory 236452 kb
Host smart-29aff827-bc08-462f-a9c8-41c970993f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3118562196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3118562196
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2102730827
Short name T187
Test name
Test status
Simulation time 5736341471 ps
CPU time 173.15 seconds
Started Jul 07 04:46:50 PM PDT 24
Finished Jul 07 04:49:44 PM PDT 24
Peak memory 240584 kb
Host smart-3dc475a9-2234-4481-ba03-a0fda7240c7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2102730827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2102730827
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4019709951
Short name T791
Test name
Test status
Simulation time 1655323526 ps
CPU time 172.74 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:49:53 PM PDT 24
Peak memory 236404 kb
Host smart-95c1e289-238a-4cc4-9e64-8ae926bb8b37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4019709951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4019709951
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3585733010
Short name T760
Test name
Test status
Simulation time 222318638 ps
CPU time 6.57 seconds
Started Jul 07 04:46:37 PM PDT 24
Finished Jul 07 04:46:44 PM PDT 24
Peak memory 249248 kb
Host smart-12800d97-c419-47bf-9f9a-3fedcd4b5583
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3585733010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3585733010
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2831708491
Short name T351
Test name
Test status
Simulation time 135469831 ps
CPU time 6.85 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 04:47:05 PM PDT 24
Peak memory 256412 kb
Host smart-68624f86-73ef-4a2b-8203-a46d1aca7ea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831708491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2831708491
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4030548502
Short name T714
Test name
Test status
Simulation time 20249591 ps
CPU time 3.81 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:05 PM PDT 24
Peak memory 237368 kb
Host smart-f920b2b1-b491-41e0-98e1-9d2e6ae9bcb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4030548502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4030548502
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.600884281
Short name T743
Test name
Test status
Simulation time 8159100 ps
CPU time 1.3 seconds
Started Jul 07 04:47:05 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 236416 kb
Host smart-b61970ef-254c-44f4-a2b6-a7d44c086ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=600884281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.600884281
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1500686726
Short name T779
Test name
Test status
Simulation time 368176475 ps
CPU time 14.28 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 238932 kb
Host smart-bc9400f1-9145-49fb-a92f-98bd34e85179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1500686726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1500686726
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4013095175
Short name T720
Test name
Test status
Simulation time 68957563 ps
CPU time 9.61 seconds
Started Jul 07 04:47:02 PM PDT 24
Finished Jul 07 04:47:12 PM PDT 24
Peak memory 248252 kb
Host smart-d5424c49-0ff6-4a20-b841-6bc2510076ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4013095175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4013095175
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.323050598
Short name T810
Test name
Test status
Simulation time 16518650 ps
CPU time 1.87 seconds
Started Jul 07 04:47:19 PM PDT 24
Finished Jul 07 04:47:22 PM PDT 24
Peak memory 236464 kb
Host smart-28798b6b-e3d9-4c0d-94bb-91c747630f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=323050598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.323050598
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3498588320
Short name T827
Test name
Test status
Simulation time 32018596 ps
CPU time 1.19 seconds
Started Jul 07 04:47:14 PM PDT 24
Finished Jul 07 04:47:16 PM PDT 24
Peak memory 237260 kb
Host smart-4d4574dc-2082-4023-8365-9e7f050b11b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3498588320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3498588320
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1408547825
Short name T793
Test name
Test status
Simulation time 57166035 ps
CPU time 1.3 seconds
Started Jul 07 04:47:18 PM PDT 24
Finished Jul 07 04:47:19 PM PDT 24
Peak memory 235492 kb
Host smart-aca9e360-ae80-4e7d-a6a2-4d2c577c0a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1408547825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1408547825
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2034750945
Short name T747
Test name
Test status
Simulation time 26098841 ps
CPU time 2.25 seconds
Started Jul 07 04:47:20 PM PDT 24
Finished Jul 07 04:47:23 PM PDT 24
Peak memory 237800 kb
Host smart-e201b74d-abcd-455c-b7a2-fce5957d63a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034750945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2034750945
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2253958699
Short name T772
Test name
Test status
Simulation time 19637968 ps
CPU time 1.46 seconds
Started Jul 07 04:47:19 PM PDT 24
Finished Jul 07 04:47:21 PM PDT 24
Peak memory 236448 kb
Host smart-1123c295-b9a4-4ec3-803f-61534f879e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2253958699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2253958699
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1520828475
Short name T813
Test name
Test status
Simulation time 44323870 ps
CPU time 1.34 seconds
Started Jul 07 04:47:20 PM PDT 24
Finished Jul 07 04:47:22 PM PDT 24
Peak memory 237412 kb
Host smart-dfbc4fe5-0720-4678-86b5-f203937dbc3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1520828475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1520828475
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3436715486
Short name T771
Test name
Test status
Simulation time 13108768 ps
CPU time 1.81 seconds
Started Jul 07 04:47:21 PM PDT 24
Finished Jul 07 04:47:23 PM PDT 24
Peak memory 235544 kb
Host smart-226e20f4-6184-4642-bcfb-ad091b721219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3436715486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3436715486
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4193199396
Short name T730
Test name
Test status
Simulation time 9180701 ps
CPU time 1.3 seconds
Started Jul 07 04:47:24 PM PDT 24
Finished Jul 07 04:47:25 PM PDT 24
Peak memory 237368 kb
Host smart-1a5f8235-a394-4879-b7c7-5c7ec046b115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4193199396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4193199396
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.290024929
Short name T742
Test name
Test status
Simulation time 14887544 ps
CPU time 1.41 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 04:47:24 PM PDT 24
Peak memory 236452 kb
Host smart-32d51390-b05f-4868-b895-72be229bf28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=290024929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.290024929
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.233587363
Short name T812
Test name
Test status
Simulation time 10141308 ps
CPU time 1.32 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 04:47:24 PM PDT 24
Peak memory 237396 kb
Host smart-0e67af47-59be-413f-bad2-bfad2cb40a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=233587363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.233587363
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.634920591
Short name T746
Test name
Test status
Simulation time 2189534180 ps
CPU time 142.7 seconds
Started Jul 07 04:46:43 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 237412 kb
Host smart-2c896ec5-f23f-4823-abae-61524e9c5a88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=634920591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.634920591
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1854974328
Short name T789
Test name
Test status
Simulation time 8592103822 ps
CPU time 211.41 seconds
Started Jul 07 04:46:39 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 237476 kb
Host smart-9ad3f03d-1bd3-4091-aae0-08fe124dcc13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1854974328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1854974328
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.21325633
Short name T751
Test name
Test status
Simulation time 71698782 ps
CPU time 3.51 seconds
Started Jul 07 04:46:55 PM PDT 24
Finished Jul 07 04:46:59 PM PDT 24
Peak memory 240272 kb
Host smart-7d2ae80b-0b3b-41b3-815c-58c00f2e2a45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=21325633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.21325633
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.127811304
Short name T759
Test name
Test status
Simulation time 171150421 ps
CPU time 11.67 seconds
Started Jul 07 04:46:46 PM PDT 24
Finished Jul 07 04:46:58 PM PDT 24
Peak memory 251700 kb
Host smart-9a124518-d8ad-4cb3-9de3-caf641608327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127811304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.127811304
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2785727803
Short name T766
Test name
Test status
Simulation time 117996247 ps
CPU time 5.32 seconds
Started Jul 07 04:46:59 PM PDT 24
Finished Jul 07 04:47:05 PM PDT 24
Peak memory 236412 kb
Host smart-08f72426-45b3-45ef-9324-a03f69b49db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2785727803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2785727803
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3293915780
Short name T807
Test name
Test status
Simulation time 18523198 ps
CPU time 1.35 seconds
Started Jul 07 04:46:39 PM PDT 24
Finished Jul 07 04:46:41 PM PDT 24
Peak memory 237404 kb
Host smart-fa57691a-522d-4ad8-b4cd-01442d248ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3293915780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3293915780
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3973866557
Short name T819
Test name
Test status
Simulation time 2772106227 ps
CPU time 32.02 seconds
Started Jul 07 04:46:37 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 244720 kb
Host smart-94e09dad-240b-4ac6-a12f-0b54792a75d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3973866557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3973866557
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2646834295
Short name T140
Test name
Test status
Simulation time 9616009487 ps
CPU time 171.92 seconds
Started Jul 07 04:46:44 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 272760 kb
Host smart-bb8ef091-3448-4d5a-9864-7ade7b6706fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2646834295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2646834295
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4014392556
Short name T125
Test name
Test status
Simulation time 25233874473 ps
CPU time 957.42 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 05:02:50 PM PDT 24
Peak memory 263840 kb
Host smart-3186f259-25e8-49c8-9352-09622c93c66d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014392556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.4014392556
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2946827316
Short name T806
Test name
Test status
Simulation time 383665210 ps
CPU time 14.36 seconds
Started Jul 07 04:46:57 PM PDT 24
Finished Jul 07 04:47:12 PM PDT 24
Peak memory 248600 kb
Host smart-052812d1-1190-460c-be20-6a8d9c418d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2946827316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2946827316
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2551266015
Short name T165
Test name
Test status
Simulation time 164771011 ps
CPU time 18.49 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:47:13 PM PDT 24
Peak memory 240276 kb
Host smart-9c3aa9fc-420b-490d-ab83-87f6fb39c417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2551266015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2551266015
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.316748356
Short name T823
Test name
Test status
Simulation time 6311992 ps
CPU time 1.49 seconds
Started Jul 07 04:47:16 PM PDT 24
Finished Jul 07 04:47:18 PM PDT 24
Peak memory 237344 kb
Host smart-c4a6b1de-db6a-4596-949c-4f1706309f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316748356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.316748356
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2576327355
Short name T814
Test name
Test status
Simulation time 44510367 ps
CPU time 1.42 seconds
Started Jul 07 04:47:19 PM PDT 24
Finished Jul 07 04:47:20 PM PDT 24
Peak memory 236444 kb
Host smart-a56e5d02-08e8-410a-96b7-30edccc1f05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2576327355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2576327355
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2691270405
Short name T782
Test name
Test status
Simulation time 10861084 ps
CPU time 1.38 seconds
Started Jul 07 04:47:16 PM PDT 24
Finished Jul 07 04:47:17 PM PDT 24
Peak memory 235332 kb
Host smart-9a611770-8c73-4e38-b23e-5a1226868e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2691270405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2691270405
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3826317067
Short name T781
Test name
Test status
Simulation time 8861754 ps
CPU time 1.26 seconds
Started Jul 07 04:47:21 PM PDT 24
Finished Jul 07 04:47:23 PM PDT 24
Peak memory 235540 kb
Host smart-d5259264-8c9b-4ff7-95f6-f5525757de48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3826317067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3826317067
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4035311291
Short name T808
Test name
Test status
Simulation time 51172379 ps
CPU time 1.45 seconds
Started Jul 07 04:47:19 PM PDT 24
Finished Jul 07 04:47:21 PM PDT 24
Peak memory 237276 kb
Host smart-f80654ef-cc84-459f-a9e5-1b20c5a21f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4035311291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4035311291
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2464264460
Short name T756
Test name
Test status
Simulation time 11988689 ps
CPU time 1.41 seconds
Started Jul 07 04:47:21 PM PDT 24
Finished Jul 07 04:47:23 PM PDT 24
Peak memory 237436 kb
Host smart-6be41a72-9c3c-48bb-814a-face6551e47b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2464264460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2464264460
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.141019059
Short name T754
Test name
Test status
Simulation time 11887167 ps
CPU time 1.5 seconds
Started Jul 07 04:47:14 PM PDT 24
Finished Jul 07 04:47:16 PM PDT 24
Peak memory 236412 kb
Host smart-e363f8a8-a586-4675-808c-13a9a97b62cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=141019059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.141019059
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1274414873
Short name T820
Test name
Test status
Simulation time 71065292 ps
CPU time 1.33 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 04:47:28 PM PDT 24
Peak memory 236336 kb
Host smart-e0e8a2a6-d277-4736-b032-d71b3ec41b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1274414873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1274414873
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4106674352
Short name T222
Test name
Test status
Simulation time 12861461 ps
CPU time 1.31 seconds
Started Jul 07 04:47:23 PM PDT 24
Finished Jul 07 04:47:25 PM PDT 24
Peak memory 236468 kb
Host smart-fb4bd29d-a879-40eb-b3f2-573a319fe722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4106674352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4106674352
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.538636495
Short name T765
Test name
Test status
Simulation time 86679658 ps
CPU time 8.38 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 253624 kb
Host smart-8f700d86-cc8c-4d1e-bf62-5903b9926c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538636495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.538636495
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.17484739
Short name T790
Test name
Test status
Simulation time 367349839 ps
CPU time 7.73 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:47:01 PM PDT 24
Peak memory 240280 kb
Host smart-a0d4b20d-e310-4eb9-8744-de230ec46c40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=17484739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.17484739
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.92503361
Short name T797
Test name
Test status
Simulation time 17705320 ps
CPU time 1.47 seconds
Started Jul 07 04:47:11 PM PDT 24
Finished Jul 07 04:47:13 PM PDT 24
Peak memory 236468 kb
Host smart-622bf67f-0c82-402c-b01e-c622edbeab36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=92503361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.92503361
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.297869377
Short name T709
Test name
Test status
Simulation time 676552909 ps
CPU time 25.3 seconds
Started Jul 07 04:47:01 PM PDT 24
Finished Jul 07 04:47:27 PM PDT 24
Peak memory 245596 kb
Host smart-f89488e0-474d-4d77-9f02-7ab1a51edc0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=297869377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.297869377
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1576059891
Short name T134
Test name
Test status
Simulation time 48555717483 ps
CPU time 620.03 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:57:13 PM PDT 24
Peak memory 265016 kb
Host smart-245e19c8-64f0-4eae-b6e0-949959948059
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576059891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1576059891
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3957119671
Short name T774
Test name
Test status
Simulation time 38122798 ps
CPU time 5.21 seconds
Started Jul 07 04:47:03 PM PDT 24
Finished Jul 07 04:47:09 PM PDT 24
Peak memory 248612 kb
Host smart-6c7b669a-9d8a-432c-928e-d29a41eff474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3957119671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3957119671
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1784563344
Short name T752
Test name
Test status
Simulation time 118620894 ps
CPU time 8.04 seconds
Started Jul 07 04:46:42 PM PDT 24
Finished Jul 07 04:46:51 PM PDT 24
Peak memory 240324 kb
Host smart-b772f155-0bd5-4e0d-94fb-3bdbdcb123ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784563344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1784563344
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1689713154
Short name T780
Test name
Test status
Simulation time 111235464 ps
CPU time 7.44 seconds
Started Jul 07 04:46:41 PM PDT 24
Finished Jul 07 04:46:49 PM PDT 24
Peak memory 236424 kb
Host smart-fd170bcf-79ab-4a71-8335-f8fe368a47c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1689713154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1689713154
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3922060984
Short name T749
Test name
Test status
Simulation time 12679668 ps
CPU time 1.39 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 04:46:53 PM PDT 24
Peak memory 236468 kb
Host smart-f620e717-a284-4e17-b572-c04d0ae00943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3922060984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3922060984
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2777238260
Short name T189
Test name
Test status
Simulation time 5402881841 ps
CPU time 35.92 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:47:28 PM PDT 24
Peak memory 248608 kb
Host smart-b18795e8-bfa7-433c-b071-f2b2f225dc0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2777238260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2777238260
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1464667679
Short name T128
Test name
Test status
Simulation time 16923921837 ps
CPU time 604.45 seconds
Started Jul 07 04:46:55 PM PDT 24
Finished Jul 07 04:57:00 PM PDT 24
Peak memory 265308 kb
Host smart-e127e778-1ee1-4e68-bc88-4f7f9fa623b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464667679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1464667679
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2604013160
Short name T831
Test name
Test status
Simulation time 115138062 ps
CPU time 6.75 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 04:46:58 PM PDT 24
Peak memory 247228 kb
Host smart-bdffd3cd-e493-4e79-92ec-da638aedd084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604013160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2604013160
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2651056466
Short name T767
Test name
Test status
Simulation time 189801448 ps
CPU time 7.03 seconds
Started Jul 07 04:46:47 PM PDT 24
Finished Jul 07 04:46:54 PM PDT 24
Peak memory 239784 kb
Host smart-e1be326c-c20b-494b-9ca9-9c669d8e3159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651056466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2651056466
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4066912303
Short name T185
Test name
Test status
Simulation time 218670101 ps
CPU time 4.89 seconds
Started Jul 07 04:46:48 PM PDT 24
Finished Jul 07 04:46:54 PM PDT 24
Peak memory 236420 kb
Host smart-40d0d501-4be8-4101-91e9-f80fd3c3d8ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4066912303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4066912303
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1423054307
Short name T726
Test name
Test status
Simulation time 31181935 ps
CPU time 2.27 seconds
Started Jul 07 04:46:55 PM PDT 24
Finished Jul 07 04:46:58 PM PDT 24
Peak memory 237400 kb
Host smart-2e2bd470-6364-4658-b45d-e22bb6b652da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423054307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1423054307
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.291494834
Short name T801
Test name
Test status
Simulation time 1029146179 ps
CPU time 21.2 seconds
Started Jul 07 04:46:50 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 245612 kb
Host smart-9db733a4-7bb2-403d-9d54-e04164baaa37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=291494834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.291494834
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2047252571
Short name T119
Test name
Test status
Simulation time 15072889270 ps
CPU time 184.02 seconds
Started Jul 07 04:46:47 PM PDT 24
Finished Jul 07 04:49:51 PM PDT 24
Peak memory 265260 kb
Host smart-e3a1a039-2d48-4497-81cc-f63cb23ee2ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2047252571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2047252571
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1033890309
Short name T114
Test name
Test status
Simulation time 7313247906 ps
CPU time 460.87 seconds
Started Jul 07 04:46:53 PM PDT 24
Finished Jul 07 04:54:35 PM PDT 24
Peak memory 268048 kb
Host smart-fe1236c4-a134-4197-befc-7f35990b8316
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033890309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1033890309
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3333996248
Short name T753
Test name
Test status
Simulation time 208397509 ps
CPU time 7.09 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:46:57 PM PDT 24
Peak memory 248500 kb
Host smart-7a9d54c3-85d2-4779-9da6-7daeb2879340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333996248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3333996248
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1324433032
Short name T816
Test name
Test status
Simulation time 184932006 ps
CPU time 13.23 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:47:07 PM PDT 24
Peak memory 251636 kb
Host smart-ad9bb657-b48d-4b2a-83c9-ede05f02130e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324433032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1324433032
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.127901987
Short name T171
Test name
Test status
Simulation time 92480277 ps
CPU time 7.66 seconds
Started Jul 07 04:47:03 PM PDT 24
Finished Jul 07 04:47:11 PM PDT 24
Peak memory 237396 kb
Host smart-67206972-681f-444c-ae38-5d5765c8dc0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=127901987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.127901987
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3769564347
Short name T758
Test name
Test status
Simulation time 7728015 ps
CPU time 1.49 seconds
Started Jul 07 04:46:48 PM PDT 24
Finished Jul 07 04:46:50 PM PDT 24
Peak memory 235372 kb
Host smart-cb97e7db-4662-42da-b98b-1e3162fb8424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3769564347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3769564347
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1864968015
Short name T723
Test name
Test status
Simulation time 2831467683 ps
CPU time 49.27 seconds
Started Jul 07 04:46:54 PM PDT 24
Finished Jul 07 04:47:44 PM PDT 24
Peak memory 248552 kb
Host smart-0dfc2b21-95e6-460d-8249-bd89b8d680fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1864968015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1864968015
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1994064303
Short name T150
Test name
Test status
Simulation time 2977986506 ps
CPU time 105.62 seconds
Started Jul 07 04:47:04 PM PDT 24
Finished Jul 07 04:48:50 PM PDT 24
Peak memory 257064 kb
Host smart-ce7ab687-80a3-48b7-93f6-af2d7eaead58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1994064303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1994064303
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2460325900
Short name T144
Test name
Test status
Simulation time 6572664791 ps
CPU time 499.12 seconds
Started Jul 07 04:46:59 PM PDT 24
Finished Jul 07 04:55:19 PM PDT 24
Peak memory 271088 kb
Host smart-505a1296-5849-41e9-9b1a-17baca0e5828
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460325900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2460325900
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1297147735
Short name T826
Test name
Test status
Simulation time 572515072 ps
CPU time 18.78 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:19 PM PDT 24
Peak memory 255180 kb
Host smart-b89d60ac-31fd-4d49-91f4-28f9d5ac893b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1297147735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1297147735
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3892683851
Short name T800
Test name
Test status
Simulation time 272805879 ps
CPU time 5.99 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:46:58 PM PDT 24
Peak memory 239664 kb
Host smart-c901f062-db08-480f-8387-0fb54d4bef75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892683851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3892683851
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2653078245
Short name T190
Test name
Test status
Simulation time 120410586 ps
CPU time 5.27 seconds
Started Jul 07 04:46:51 PM PDT 24
Finished Jul 07 04:46:57 PM PDT 24
Peak memory 237420 kb
Host smart-9db6d57e-a64b-464f-8280-bc24d487567f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2653078245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2653078245
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1136920157
Short name T761
Test name
Test status
Simulation time 9327746 ps
CPU time 1.49 seconds
Started Jul 07 04:46:52 PM PDT 24
Finished Jul 07 04:46:54 PM PDT 24
Peak memory 235436 kb
Host smart-535b7f34-830a-412f-9d44-82ce65bcc626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136920157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1136920157
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3971150410
Short name T734
Test name
Test status
Simulation time 662587319 ps
CPU time 13.58 seconds
Started Jul 07 04:46:49 PM PDT 24
Finished Jul 07 04:47:03 PM PDT 24
Peak memory 245568 kb
Host smart-48ac7fd2-f973-4ff7-9e40-9e7b8485288d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3971150410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3971150410
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2804380524
Short name T123
Test name
Test status
Simulation time 17959021653 ps
CPU time 729.73 seconds
Started Jul 07 04:46:55 PM PDT 24
Finished Jul 07 04:59:05 PM PDT 24
Peak memory 265172 kb
Host smart-2dcf84a3-86b3-4208-8482-ca4881696c07
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804380524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2804380524
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4111915702
Short name T822
Test name
Test status
Simulation time 683254586 ps
CPU time 11.64 seconds
Started Jul 07 04:47:00 PM PDT 24
Finished Jul 07 04:47:12 PM PDT 24
Peak memory 248384 kb
Host smart-05e7f81f-d3c3-45d9-96aa-ecc650eddd04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4111915702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4111915702
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2949796931
Short name T43
Test name
Test status
Simulation time 11099527773 ps
CPU time 651.37 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:58:19 PM PDT 24
Peak memory 273092 kb
Host smart-62271823-1e1a-4bfc-b588-896acfdc2982
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949796931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2949796931
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3383313125
Short name T460
Test name
Test status
Simulation time 544683237 ps
CPU time 8.73 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 04:47:37 PM PDT 24
Peak memory 249048 kb
Host smart-d7905718-af2e-4b1a-9ae6-b36274308968
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3383313125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3383313125
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2038397483
Short name T491
Test name
Test status
Simulation time 299785326 ps
CPU time 19.29 seconds
Started Jul 07 04:47:21 PM PDT 24
Finished Jul 07 04:47:41 PM PDT 24
Peak memory 255488 kb
Host smart-1632edbb-9a48-4ac6-a95b-4c9b52e7ed7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
97483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2038397483
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1724572061
Short name T63
Test name
Test status
Simulation time 1100525678 ps
CPU time 59.61 seconds
Started Jul 07 04:47:23 PM PDT 24
Finished Jul 07 04:48:23 PM PDT 24
Peak memory 256408 kb
Host smart-3fcaf796-34fc-4269-992e-450454b99327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
72061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1724572061
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2205156414
Short name T337
Test name
Test status
Simulation time 18845087562 ps
CPU time 1669.21 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 05:15:12 PM PDT 24
Peak memory 289540 kb
Host smart-4ad586c3-1fb8-4feb-bae0-cbb5a57f306f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205156414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2205156414
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4033818040
Short name T56
Test name
Test status
Simulation time 290204028993 ps
CPU time 2114.04 seconds
Started Jul 07 04:47:23 PM PDT 24
Finished Jul 07 05:22:38 PM PDT 24
Peak memory 284268 kb
Host smart-894240d6-aa58-4530-a649-1c3a779bb4fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033818040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4033818040
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3188175725
Short name T397
Test name
Test status
Simulation time 6750611935 ps
CPU time 56.88 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:48:24 PM PDT 24
Peak memory 256596 kb
Host smart-c27f3135-b2f5-4559-aa3b-ee0f8a8b3cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
75725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3188175725
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1593004801
Short name T541
Test name
Test status
Simulation time 2487020036 ps
CPU time 26.79 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 04:47:55 PM PDT 24
Peak memory 256976 kb
Host smart-5bec6f5a-76d9-42e1-9418-82db30029e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
04801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1593004801
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.106325743
Short name T32
Test name
Test status
Simulation time 583981204 ps
CPU time 30.21 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 04:47:59 PM PDT 24
Peak memory 272208 kb
Host smart-51f11524-4f71-49c9-8eed-2b40195fd30b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=106325743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.106325743
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.162878080
Short name T620
Test name
Test status
Simulation time 100526370 ps
CPU time 11.48 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 04:47:34 PM PDT 24
Peak memory 248492 kb
Host smart-09deaa6f-0072-4240-a2aa-7cef4d31c78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287
8080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.162878080
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.633717569
Short name T400
Test name
Test status
Simulation time 178694465 ps
CPU time 16.05 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:47:43 PM PDT 24
Peak memory 256992 kb
Host smart-c7886559-1249-4ce4-b6f2-ebbaaa32409d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63371
7569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.633717569
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2011020948
Short name T509
Test name
Test status
Simulation time 57226776973 ps
CPU time 1178.16 seconds
Started Jul 07 04:47:25 PM PDT 24
Finished Jul 07 05:07:04 PM PDT 24
Peak memory 289360 kb
Host smart-fad735d2-85aa-4004-bf1f-51fbcc276491
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011020948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2011020948
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3923487152
Short name T526
Test name
Test status
Simulation time 35201513480 ps
CPU time 832.02 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 05:01:18 PM PDT 24
Peak memory 273768 kb
Host smart-904cc5b5-c521-4a00-a537-684263c14684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923487152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3923487152
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1577820461
Short name T521
Test name
Test status
Simulation time 148199341 ps
CPU time 8.47 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:47:36 PM PDT 24
Peak memory 249124 kb
Host smart-28f26efa-eec5-4130-9fbc-e7cd70200429
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1577820461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1577820461
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3868577698
Short name T452
Test name
Test status
Simulation time 483651745 ps
CPU time 28.58 seconds
Started Jul 07 04:47:25 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 256872 kb
Host smart-d1d2a7ba-20c4-4705-be19-4826071be22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
77698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3868577698
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4146636093
Short name T95
Test name
Test status
Simulation time 816228187 ps
CPU time 17.59 seconds
Started Jul 07 04:47:25 PM PDT 24
Finished Jul 07 04:47:44 PM PDT 24
Peak memory 255592 kb
Host smart-6ada39d6-6e4c-40b4-a371-fec68aa5677a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
36093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4146636093
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1705487852
Short name T472
Test name
Test status
Simulation time 21133304350 ps
CPU time 1319.21 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 290028 kb
Host smart-bbd80c10-8e2e-4747-8b47-0e2440f0d15c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705487852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1705487852
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3195395852
Short name T549
Test name
Test status
Simulation time 2185730879 ps
CPU time 63.38 seconds
Started Jul 07 04:47:22 PM PDT 24
Finished Jul 07 04:48:26 PM PDT 24
Peak memory 249284 kb
Host smart-92f7db3c-deca-4af1-a41c-6a4fa81b51f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31953
95852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3195395852
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2164071666
Short name T394
Test name
Test status
Simulation time 948134438 ps
CPU time 16.53 seconds
Started Jul 07 04:47:30 PM PDT 24
Finished Jul 07 04:47:46 PM PDT 24
Peak memory 248672 kb
Host smart-b4af8e36-7f4e-48a7-aec3-c74d29268134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
71666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2164071666
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4092002007
Short name T16
Test name
Test status
Simulation time 353035783 ps
CPU time 22.12 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 04:47:49 PM PDT 24
Peak memory 275324 kb
Host smart-f4962068-81a2-46ca-bf6b-3e9d76c85f58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4092002007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4092002007
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2383338588
Short name T665
Test name
Test status
Simulation time 222233376 ps
CPU time 13.15 seconds
Started Jul 07 04:47:21 PM PDT 24
Finished Jul 07 04:47:34 PM PDT 24
Peak memory 249660 kb
Host smart-3904a1bf-b6da-496b-ab68-0904709ed0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23833
38588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2383338588
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2977096960
Short name T457
Test name
Test status
Simulation time 4956792501 ps
CPU time 28.32 seconds
Started Jul 07 04:47:20 PM PDT 24
Finished Jul 07 04:47:49 PM PDT 24
Peak memory 257104 kb
Host smart-49cd6d69-5e87-4e09-85c4-35c757d4048a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29770
96960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2977096960
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.444975391
Short name T464
Test name
Test status
Simulation time 352952146739 ps
CPU time 5550.08 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 06:19:59 PM PDT 24
Peak memory 305928 kb
Host smart-20b9a912-9285-4ef0-9745-d7440cc8c478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444975391 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.444975391
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.149727723
Short name T661
Test name
Test status
Simulation time 169960337 ps
CPU time 8.03 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 249196 kb
Host smart-ad591768-2a1d-45a4-ac3f-908bbfc8de4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=149727723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.149727723
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2341651119
Short name T376
Test name
Test status
Simulation time 4961131418 ps
CPU time 292.45 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 252452 kb
Host smart-3656573a-9828-4967-830f-343269627eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23416
51119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2341651119
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.464395933
Short name T503
Test name
Test status
Simulation time 1835081105 ps
CPU time 34.78 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:48:24 PM PDT 24
Peak memory 256900 kb
Host smart-37edee2c-ccd5-424b-b074-e9889bb0e508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46439
5933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.464395933
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1580101163
Short name T577
Test name
Test status
Simulation time 39479586351 ps
CPU time 2392.91 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 05:27:42 PM PDT 24
Peak memory 289880 kb
Host smart-6ecacf84-2278-4c8a-ad02-af6e1892e380
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580101163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1580101163
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1371731415
Short name T390
Test name
Test status
Simulation time 1072627958 ps
CPU time 17.5 seconds
Started Jul 07 04:47:43 PM PDT 24
Finished Jul 07 04:48:00 PM PDT 24
Peak memory 249200 kb
Host smart-6fe0cb35-a05d-4b80-b672-a56c45dc9dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
31415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1371731415
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1480730332
Short name T484
Test name
Test status
Simulation time 349853807 ps
CPU time 4.82 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:47:52 PM PDT 24
Peak memory 240868 kb
Host smart-5b973210-5154-4b41-837b-40a5c448198b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14807
30332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1480730332
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.43247152
Short name T455
Test name
Test status
Simulation time 1438523219 ps
CPU time 34.81 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:48:22 PM PDT 24
Peak memory 249080 kb
Host smart-a213924e-ae44-43e0-acec-475fa17b06b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43247
152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.43247152
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2942854439
Short name T595
Test name
Test status
Simulation time 167618960006 ps
CPU time 2246.07 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 289712 kb
Host smart-3f78a6d8-b8f7-4898-9cd4-03c98b293ade
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942854439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2942854439
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.4275196076
Short name T200
Test name
Test status
Simulation time 30787055 ps
CPU time 3.31 seconds
Started Jul 07 04:47:43 PM PDT 24
Finished Jul 07 04:47:47 PM PDT 24
Peak memory 249364 kb
Host smart-24085480-3008-42dd-b89e-215a15e0de18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4275196076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.4275196076
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3161587757
Short name T687
Test name
Test status
Simulation time 37548391659 ps
CPU time 2367.3 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 05:27:19 PM PDT 24
Peak memory 288600 kb
Host smart-b28ffe6a-cb62-4ed1-a7c0-530b1c49358f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161587757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3161587757
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2649978853
Short name T430
Test name
Test status
Simulation time 1131805090 ps
CPU time 38.52 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:26 PM PDT 24
Peak memory 249108 kb
Host smart-ec8db54a-35fa-488a-bd99-a0be727a2c48
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2649978853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2649978853
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.749052881
Short name T371
Test name
Test status
Simulation time 13220456782 ps
CPU time 133.21 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:49:59 PM PDT 24
Peak memory 257444 kb
Host smart-147b43e4-852a-478c-b10d-bc23f77a14cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74905
2881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.749052881
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.763794149
Short name T467
Test name
Test status
Simulation time 17275656147 ps
CPU time 864.64 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 05:02:12 PM PDT 24
Peak memory 273828 kb
Host smart-96201ca8-f09f-4f28-b9d5-6802647cf102
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763794149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.763794149
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4160940023
Short name T221
Test name
Test status
Simulation time 8122941917 ps
CPU time 189.51 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:50:59 PM PDT 24
Peak memory 256300 kb
Host smart-38e11bb9-cee4-4e66-9203-ccc2e743eed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160940023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4160940023
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2094033520
Short name T427
Test name
Test status
Simulation time 1922814716 ps
CPU time 31.26 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 04:48:16 PM PDT 24
Peak memory 256420 kb
Host smart-b082b84c-1a3e-4933-9e88-7f8c04f91a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20940
33520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2094033520
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.784679528
Short name T697
Test name
Test status
Simulation time 3585216966 ps
CPU time 32.82 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:21 PM PDT 24
Peak memory 257144 kb
Host smart-37ba50c4-ef9c-4bf8-96ec-b4289ebe5a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78467
9528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.784679528
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3315856159
Short name T246
Test name
Test status
Simulation time 1237077967 ps
CPU time 46.8 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:34 PM PDT 24
Peak memory 248656 kb
Host smart-c2085d8e-d87b-4bdb-a6db-2eb84f76012c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
56159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3315856159
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.913951465
Short name T640
Test name
Test status
Simulation time 2687606222 ps
CPU time 48.09 seconds
Started Jul 07 04:47:42 PM PDT 24
Finished Jul 07 04:48:31 PM PDT 24
Peak memory 249556 kb
Host smart-b6d72083-8d6b-4f71-a741-3db27a89a9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91395
1465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.913951465
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3226435728
Short name T39
Test name
Test status
Simulation time 425310205209 ps
CPU time 2023 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 281940 kb
Host smart-7f3230ad-f8bf-4335-b56e-86119c3662b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226435728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3226435728
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3042274378
Short name T203
Test name
Test status
Simulation time 181963441 ps
CPU time 3.57 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 04:48:11 PM PDT 24
Peak memory 249376 kb
Host smart-bbd89ddc-16d6-4f46-9064-904cb63d2e5a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3042274378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3042274378
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1039754128
Short name T579
Test name
Test status
Simulation time 30064810151 ps
CPU time 1852.54 seconds
Started Jul 07 04:47:54 PM PDT 24
Finished Jul 07 05:18:47 PM PDT 24
Peak memory 273836 kb
Host smart-6a219718-3469-42e2-b76a-bd92d35baeb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039754128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1039754128
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1746318659
Short name T515
Test name
Test status
Simulation time 226259882 ps
CPU time 13.7 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:48:00 PM PDT 24
Peak memory 249220 kb
Host smart-a3260b98-38f6-4c15-bfe3-f1bc7c67c9e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1746318659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1746318659
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.175943460
Short name T361
Test name
Test status
Simulation time 5427395663 ps
CPU time 111.32 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 257556 kb
Host smart-3f2e247d-5145-4fd6-943c-ea0430b496c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17594
3460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.175943460
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.276405397
Short name T432
Test name
Test status
Simulation time 6047588291 ps
CPU time 26.36 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:15 PM PDT 24
Peak memory 248532 kb
Host smart-a198a942-ba92-466d-9591-ed8a52307131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
5397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.276405397
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1052194792
Short name T328
Test name
Test status
Simulation time 21255901573 ps
CPU time 1273.93 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 273752 kb
Host smart-a425a5d5-b92f-4236-b9f2-5035b62fdf8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052194792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1052194792
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2680868111
Short name T414
Test name
Test status
Simulation time 24952174112 ps
CPU time 694.1 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:59:23 PM PDT 24
Peak memory 273664 kb
Host smart-93a4d4ba-02b8-4fff-9c97-e968209a0425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680868111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2680868111
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1909453911
Short name T642
Test name
Test status
Simulation time 6083316920 ps
CPU time 253.1 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:52:00 PM PDT 24
Peak memory 255468 kb
Host smart-efefad16-a31e-46e4-bfbe-f5ebc049465c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909453911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1909453911
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2833200846
Short name T574
Test name
Test status
Simulation time 1469489491 ps
CPU time 18.7 seconds
Started Jul 07 04:47:45 PM PDT 24
Finished Jul 07 04:48:04 PM PDT 24
Peak memory 256680 kb
Host smart-57ad1319-737d-4f32-b8bb-f1a31f6997ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28332
00846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2833200846
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2540219684
Short name T480
Test name
Test status
Simulation time 3082816700 ps
CPU time 50.72 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 04:48:35 PM PDT 24
Peak memory 249256 kb
Host smart-84f6575b-5ae3-4e9e-ab02-b26edd1a17e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
19684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2540219684
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3126384560
Short name T364
Test name
Test status
Simulation time 589732589 ps
CPU time 40.11 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 04:48:27 PM PDT 24
Peak memory 257376 kb
Host smart-69dcebce-6e23-4874-8dd6-a6ed13eabc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31263
84560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3126384560
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2070840807
Short name T193
Test name
Test status
Simulation time 54052758 ps
CPU time 3.19 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 04:47:56 PM PDT 24
Peak memory 249376 kb
Host smart-29359961-f537-4ddf-ab97-469632f7fcc4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2070840807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2070840807
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3886460392
Short name T434
Test name
Test status
Simulation time 32836437598 ps
CPU time 932.7 seconds
Started Jul 07 04:47:46 PM PDT 24
Finished Jul 07 05:03:19 PM PDT 24
Peak memory 273184 kb
Host smart-c3e585e9-7add-4ecc-8997-ea5104592b41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886460392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3886460392
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1868529030
Short name T663
Test name
Test status
Simulation time 1347430440 ps
CPU time 59.2 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 249064 kb
Host smart-76fe7b40-fe04-480c-87bd-e2e20b32bb38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1868529030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1868529030
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3356840650
Short name T424
Test name
Test status
Simulation time 229624740 ps
CPU time 17.29 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:48:06 PM PDT 24
Peak memory 256248 kb
Host smart-43ec52d3-489a-4449-819f-3bae23b36c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33568
40650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3356840650
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.913521048
Short name T561
Test name
Test status
Simulation time 1003842319 ps
CPU time 15.94 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:48:05 PM PDT 24
Peak memory 253748 kb
Host smart-0057fa61-c672-4b5f-9395-5632804a90c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91352
1048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.913521048
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1514826177
Short name T363
Test name
Test status
Simulation time 42330327366 ps
CPU time 2606.35 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 05:31:24 PM PDT 24
Peak memory 289560 kb
Host smart-b957b87c-eced-4cc9-bf50-3455e07986fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514826177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1514826177
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3234474077
Short name T578
Test name
Test status
Simulation time 217495641 ps
CPU time 21.32 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:48:15 PM PDT 24
Peak memory 256700 kb
Host smart-395e8cc2-45bd-4ee4-92ac-d1f3b32724f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
74077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3234474077
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2863357334
Short name T218
Test name
Test status
Simulation time 1047719012 ps
CPU time 48.71 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 04:48:39 PM PDT 24
Peak memory 256184 kb
Host smart-e3b413d8-7af1-4e65-91c1-19cf606ece87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28633
57334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2863357334
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3955691633
Short name T448
Test name
Test status
Simulation time 1458877690 ps
CPU time 26.27 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:48:15 PM PDT 24
Peak memory 255712 kb
Host smart-dc765741-d0d2-4a34-b859-c9e985084aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39556
91633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3955691633
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.70982767
Short name T238
Test name
Test status
Simulation time 3173729991 ps
CPU time 42.43 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:30 PM PDT 24
Peak memory 257376 kb
Host smart-01accdb4-e28b-445b-870b-3294f58ed4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70982
767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.70982767
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1306642304
Short name T17
Test name
Test status
Simulation time 8774625085 ps
CPU time 777.06 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 05:00:47 PM PDT 24
Peak memory 273716 kb
Host smart-41b0962c-1c94-438f-82dd-1f152caf5977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306642304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1306642304
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1388420104
Short name T417
Test name
Test status
Simulation time 229831639 ps
CPU time 13.95 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:01 PM PDT 24
Peak memory 249036 kb
Host smart-62cc9f80-6e38-4650-9fa9-89303652be4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1388420104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1388420104
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2487395798
Short name T408
Test name
Test status
Simulation time 1667766954 ps
CPU time 57.45 seconds
Started Jul 07 04:47:50 PM PDT 24
Finished Jul 07 04:48:47 PM PDT 24
Peak memory 256484 kb
Host smart-d3c28552-7f65-489b-b430-93ce3673c449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
95798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2487395798
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3548080152
Short name T214
Test name
Test status
Simulation time 976611582 ps
CPU time 29.96 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:18 PM PDT 24
Peak memory 248928 kb
Host smart-f3d14438-d163-4d35-8079-f1d6c518ae52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35480
80152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3548080152
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1259744522
Short name T419
Test name
Test status
Simulation time 17045866559 ps
CPU time 975.19 seconds
Started Jul 07 04:47:54 PM PDT 24
Finished Jul 07 05:04:10 PM PDT 24
Peak memory 273800 kb
Host smart-caae63cd-8723-4c6b-bb48-98b6fed76834
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259744522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1259744522
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1101145604
Short name T297
Test name
Test status
Simulation time 14995245182 ps
CPU time 316.81 seconds
Started Jul 07 04:48:10 PM PDT 24
Finished Jul 07 04:53:27 PM PDT 24
Peak memory 256280 kb
Host smart-8290461a-5701-45c6-980d-9600fa6faebf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101145604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1101145604
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2817210141
Short name T529
Test name
Test status
Simulation time 364313681 ps
CPU time 17.63 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:48:06 PM PDT 24
Peak memory 249104 kb
Host smart-2a28558c-d0bd-424f-a996-7fbab4e79d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
10141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2817210141
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1737206945
Short name T622
Test name
Test status
Simulation time 3685246889 ps
CPU time 58.85 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:48:50 PM PDT 24
Peak memory 248868 kb
Host smart-fff2c78a-2803-4a6b-9f33-d0f51b11ea0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
06945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1737206945
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3757499738
Short name T614
Test name
Test status
Simulation time 1702914431 ps
CPU time 17.4 seconds
Started Jul 07 04:48:01 PM PDT 24
Finished Jul 07 04:48:19 PM PDT 24
Peak memory 257292 kb
Host smart-90ec35a8-7dc1-406f-a512-83a804f70bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
99738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3757499738
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.429405008
Short name T192
Test name
Test status
Simulation time 152015651 ps
CPU time 2.53 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 04:48:14 PM PDT 24
Peak memory 249448 kb
Host smart-402855f6-3b83-4138-a2db-3020568ad75a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=429405008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.429405008
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2280871489
Short name T87
Test name
Test status
Simulation time 48446227556 ps
CPU time 1177.47 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 282604 kb
Host smart-6e776de2-4402-4582-bc67-38e6b461e165
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280871489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2280871489
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2661675667
Short name T379
Test name
Test status
Simulation time 169681300 ps
CPU time 9.79 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:48:01 PM PDT 24
Peak memory 249112 kb
Host smart-8ff639ce-7178-4157-81be-deef2ee6895a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2661675667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2661675667
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3686740099
Short name T700
Test name
Test status
Simulation time 43282130130 ps
CPU time 202.32 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:51:29 PM PDT 24
Peak memory 256776 kb
Host smart-abbb499d-98ea-4d2b-9b21-5d89b7228303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36867
40099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3686740099
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3941556917
Short name T507
Test name
Test status
Simulation time 1191922830 ps
CPU time 7.96 seconds
Started Jul 07 04:47:53 PM PDT 24
Finished Jul 07 04:48:01 PM PDT 24
Peak memory 252188 kb
Host smart-ce59d3c6-9304-4b83-8e13-97c85ba5d234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39415
56917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3941556917
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2080174380
Short name T698
Test name
Test status
Simulation time 85373292999 ps
CPU time 1727.34 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 05:16:39 PM PDT 24
Peak memory 289732 kb
Host smart-56adc504-0194-45fc-bbf7-8e55a15921b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080174380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2080174380
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2288379106
Short name T179
Test name
Test status
Simulation time 54068915489 ps
CPU time 1471.26 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 268804 kb
Host smart-c94248b1-0cd9-43f2-8fa2-f43bea7983b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288379106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2288379106
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2832814683
Short name T699
Test name
Test status
Simulation time 48808113873 ps
CPU time 499.06 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 04:56:16 PM PDT 24
Peak memory 249204 kb
Host smart-73c98493-3aa5-4b4b-903e-d8a269d85035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832814683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2832814683
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.223357520
Short name T693
Test name
Test status
Simulation time 2986362785 ps
CPU time 52.88 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:48:45 PM PDT 24
Peak memory 249696 kb
Host smart-7a03af0a-8d92-49bb-8be0-f97e3deeb1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
7520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.223357520
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3456785049
Short name T78
Test name
Test status
Simulation time 1116214124 ps
CPU time 27.71 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:48:19 PM PDT 24
Peak memory 257304 kb
Host smart-c7099fa2-8888-4d81-8cc0-65c7dc5305da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34567
85049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3456785049
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3817438720
Short name T557
Test name
Test status
Simulation time 320486805 ps
CPU time 23.05 seconds
Started Jul 07 04:47:59 PM PDT 24
Finished Jul 07 04:48:22 PM PDT 24
Peak memory 256632 kb
Host smart-ee26e0f3-988f-4abe-aa4c-8e0a9c7bb597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38174
38720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3817438720
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.7649627
Short name T266
Test name
Test status
Simulation time 69840228719 ps
CPU time 1209.58 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 282124 kb
Host smart-f4acba00-590e-4ac0-a093-d820c16d9a97
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7649627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handl
er_stress_all.7649627
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3870924047
Short name T405
Test name
Test status
Simulation time 142720437929 ps
CPU time 3976.28 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 05:54:09 PM PDT 24
Peak memory 322876 kb
Host smart-f39a3321-830d-4f4f-8e4f-1a6014302556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870924047 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3870924047
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4034277456
Short name T209
Test name
Test status
Simulation time 45882493 ps
CPU time 2.57 seconds
Started Jul 07 04:47:50 PM PDT 24
Finished Jul 07 04:47:53 PM PDT 24
Peak memory 249352 kb
Host smart-a1456490-8df1-42dc-bae8-6c44ea6e53c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4034277456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4034277456
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.955231096
Short name T616
Test name
Test status
Simulation time 214375689254 ps
CPU time 1696.42 seconds
Started Jul 07 04:47:55 PM PDT 24
Finished Jul 07 05:16:11 PM PDT 24
Peak memory 273448 kb
Host smart-1d39413e-76c0-4858-b17d-0a00a12de32e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955231096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.955231096
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4128925182
Short name T225
Test name
Test status
Simulation time 1870677397 ps
CPU time 38.13 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 04:48:34 PM PDT 24
Peak memory 249040 kb
Host smart-cfffde08-f407-495b-b1ed-73298d1e8926
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4128925182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4128925182
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3114852395
Short name T648
Test name
Test status
Simulation time 10563870074 ps
CPU time 119.5 seconds
Started Jul 07 04:47:48 PM PDT 24
Finished Jul 07 04:49:48 PM PDT 24
Peak memory 257436 kb
Host smart-3955ea6f-3579-4260-8cf8-e76fa67f00ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
52395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3114852395
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2667699264
Short name T582
Test name
Test status
Simulation time 4354704818 ps
CPU time 24.23 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 04:48:14 PM PDT 24
Peak memory 256692 kb
Host smart-9f17915d-230e-45d2-b3df-937d1199e437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26676
99264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2667699264
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3814154312
Short name T623
Test name
Test status
Simulation time 22620794517 ps
CPU time 1313.31 seconds
Started Jul 07 04:47:50 PM PDT 24
Finished Jul 07 05:09:44 PM PDT 24
Peak memory 289544 kb
Host smart-13196511-7d03-469a-a627-314db150fb38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814154312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3814154312
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1428014835
Short name T553
Test name
Test status
Simulation time 7257969326 ps
CPU time 303.35 seconds
Started Jul 07 04:47:47 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 257420 kb
Host smart-5a2af301-29c4-42e5-adaa-b8c536b93a7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428014835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1428014835
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1650168732
Short name T216
Test name
Test status
Simulation time 106296488 ps
CPU time 9.1 seconds
Started Jul 07 04:47:54 PM PDT 24
Finished Jul 07 04:48:03 PM PDT 24
Peak memory 249132 kb
Host smart-7ae4ff34-727b-40f5-8f85-7223de56467d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16501
68732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1650168732
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2446117697
Short name T281
Test name
Test status
Simulation time 746692752 ps
CPU time 24.23 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:48:15 PM PDT 24
Peak memory 255888 kb
Host smart-5dbf0ece-45b0-4f38-9091-777d7163d8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24461
17697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2446117697
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3032352509
Short name T501
Test name
Test status
Simulation time 499527705 ps
CPU time 25.96 seconds
Started Jul 07 04:48:05 PM PDT 24
Finished Jul 07 04:48:32 PM PDT 24
Peak memory 256692 kb
Host smart-0796a40d-906e-40ed-8a3c-95a6ab8e070a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30323
52509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3032352509
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2979863012
Short name T359
Test name
Test status
Simulation time 591136249 ps
CPU time 31.61 seconds
Started Jul 07 04:47:49 PM PDT 24
Finished Jul 07 04:48:21 PM PDT 24
Peak memory 256760 kb
Host smart-8fa26b0c-79b5-4b22-9641-be2c7d4fcade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29798
63012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2979863012
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2448061346
Short name T197
Test name
Test status
Simulation time 86752854 ps
CPU time 3.46 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 249332 kb
Host smart-05889e74-110f-4900-b9a6-fc5f1f968414
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2448061346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2448061346
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3070642580
Short name T692
Test name
Test status
Simulation time 24153959254 ps
CPU time 1745.91 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 05:17:03 PM PDT 24
Peak memory 288988 kb
Host smart-4a6666b4-b6c5-4e17-b42b-233bc6978258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070642580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3070642580
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1836777596
Short name T580
Test name
Test status
Simulation time 395131644 ps
CPU time 6.94 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:47:58 PM PDT 24
Peak memory 249036 kb
Host smart-636e0825-b696-479d-b7e8-a9ae1e808d8e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1836777596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1836777596
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2313685182
Short name T381
Test name
Test status
Simulation time 772099308 ps
CPU time 14.02 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 04:48:10 PM PDT 24
Peak memory 256908 kb
Host smart-8dfa44bc-2629-4519-9afe-ed0e3b906d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
85182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2313685182
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1200788564
Short name T584
Test name
Test status
Simulation time 1137220837 ps
CPU time 14.57 seconds
Started Jul 07 04:48:00 PM PDT 24
Finished Jul 07 04:48:14 PM PDT 24
Peak memory 249064 kb
Host smart-34dff607-cbc0-4a16-9350-84c8c5eaf5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12007
88564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1200788564
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.566569107
Short name T269
Test name
Test status
Simulation time 147599911162 ps
CPU time 2833.16 seconds
Started Jul 07 04:48:04 PM PDT 24
Finished Jul 07 05:35:18 PM PDT 24
Peak memory 286936 kb
Host smart-c19c6903-e3cf-408e-851d-57a106a88057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566569107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.566569107
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3419762479
Short name T219
Test name
Test status
Simulation time 16815951399 ps
CPU time 151 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:50:23 PM PDT 24
Peak memory 249256 kb
Host smart-9fdb7498-ab89-416b-be9b-01c0c65497d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419762479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3419762479
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4291025676
Short name T272
Test name
Test status
Simulation time 515692297 ps
CPU time 14.45 seconds
Started Jul 07 04:48:03 PM PDT 24
Finished Jul 07 04:48:18 PM PDT 24
Peak memory 256496 kb
Host smart-aedfb122-3ba0-4fb6-a5f1-50e5403147e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42910
25676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4291025676
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3136541694
Short name T1
Test name
Test status
Simulation time 238397165 ps
CPU time 16.11 seconds
Started Jul 07 04:48:01 PM PDT 24
Finished Jul 07 04:48:17 PM PDT 24
Peak memory 248900 kb
Host smart-822c2a4b-b520-4f1d-877e-20d9d8ea702c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
41694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3136541694
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3871190535
Short name T243
Test name
Test status
Simulation time 191564724 ps
CPU time 22.79 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:48:15 PM PDT 24
Peak memory 248508 kb
Host smart-8e2c089e-6222-4086-9130-c70d323194ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
90535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3871190535
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3801651911
Short name T183
Test name
Test status
Simulation time 2734756830 ps
CPU time 45.05 seconds
Started Jul 07 04:47:59 PM PDT 24
Finished Jul 07 04:48:44 PM PDT 24
Peak memory 249416 kb
Host smart-4bf0792b-c215-42be-acaf-32afcf988582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38016
51911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3801651911
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2194995094
Short name T279
Test name
Test status
Simulation time 17558572415 ps
CPU time 641.29 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 04:58:50 PM PDT 24
Peak memory 257464 kb
Host smart-664dc324-2086-4967-a24e-29232896c239
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194995094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2194995094
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.64455051
Short name T202
Test name
Test status
Simulation time 18625140 ps
CPU time 2.78 seconds
Started Jul 07 04:47:54 PM PDT 24
Finished Jul 07 04:47:57 PM PDT 24
Peak memory 249408 kb
Host smart-b7166ad6-74c6-480d-b200-e23afcac71d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=64455051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.64455051
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2636173987
Short name T275
Test name
Test status
Simulation time 25759425891 ps
CPU time 1570.12 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 05:14:16 PM PDT 24
Peak memory 273636 kb
Host smart-3245bd99-85a4-47d6-8ba3-38d60133ee3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636173987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2636173987
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.270420849
Short name T451
Test name
Test status
Simulation time 734654566 ps
CPU time 17.24 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 04:48:10 PM PDT 24
Peak memory 249040 kb
Host smart-9431294b-bc49-4ecf-9e64-8e85353768d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=270420849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.270420849
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3562691527
Short name T25
Test name
Test status
Simulation time 31668819039 ps
CPU time 306.2 seconds
Started Jul 07 04:47:52 PM PDT 24
Finished Jul 07 04:52:58 PM PDT 24
Peak memory 251556 kb
Host smart-4371d809-e544-4e3a-a662-90bd23ba3e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35626
91527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3562691527
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2063883117
Short name T581
Test name
Test status
Simulation time 632630675 ps
CPU time 42.56 seconds
Started Jul 07 04:48:05 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 257196 kb
Host smart-2036f667-a4e9-4052-a9d6-e6fd3ed6454a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
83117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2063883117
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4211924295
Short name T282
Test name
Test status
Simulation time 13062315960 ps
CPU time 1279.01 seconds
Started Jul 07 04:48:01 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 283252 kb
Host smart-ec92afe8-f38b-4542-b757-0d5b5de0b4be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211924295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4211924295
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2498421519
Short name T667
Test name
Test status
Simulation time 48182717263 ps
CPU time 2869.07 seconds
Started Jul 07 04:48:02 PM PDT 24
Finished Jul 07 05:35:51 PM PDT 24
Peak memory 289948 kb
Host smart-419947c4-3680-40d4-bfe6-ec86d7503433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498421519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2498421519
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1577160163
Short name T518
Test name
Test status
Simulation time 16680469482 ps
CPU time 122.55 seconds
Started Jul 07 04:47:55 PM PDT 24
Finished Jul 07 04:49:57 PM PDT 24
Peak memory 248900 kb
Host smart-3b3cdbcf-cdf2-4ccc-9b6b-fcc8f168fe05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577160163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1577160163
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3006401556
Short name T388
Test name
Test status
Simulation time 9151450795 ps
CPU time 38.08 seconds
Started Jul 07 04:48:04 PM PDT 24
Finished Jul 07 04:48:43 PM PDT 24
Peak memory 256640 kb
Host smart-7e1dfff7-a3c9-4706-9b7e-1ea4f3990355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30064
01556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3006401556
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.887255112
Short name T563
Test name
Test status
Simulation time 1159549269 ps
CPU time 40.48 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:48:54 PM PDT 24
Peak memory 257300 kb
Host smart-306c7769-80da-4783-9934-6fc3c21a6dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88725
5112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.887255112
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2298713583
Short name T438
Test name
Test status
Simulation time 40967491 ps
CPU time 7.11 seconds
Started Jul 07 04:48:02 PM PDT 24
Finished Jul 07 04:48:09 PM PDT 24
Peak memory 248576 kb
Host smart-5944ae1f-e3c0-4764-adc7-0838f5020db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
13583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2298713583
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1652297367
Short name T657
Test name
Test status
Simulation time 433347098 ps
CPU time 7.71 seconds
Started Jul 07 04:47:51 PM PDT 24
Finished Jul 07 04:47:59 PM PDT 24
Peak memory 249048 kb
Host smart-99b21aa2-4c6f-4519-ac62-019dce1966ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16522
97367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1652297367
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.944517522
Short name T206
Test name
Test status
Simulation time 166637346 ps
CPU time 3.76 seconds
Started Jul 07 04:48:02 PM PDT 24
Finished Jul 07 04:48:06 PM PDT 24
Peak memory 249524 kb
Host smart-f3fd4bd5-b73d-4566-ab2a-287e87e553fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=944517522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.944517522
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3146316850
Short name T421
Test name
Test status
Simulation time 41287114483 ps
CPU time 2400.86 seconds
Started Jul 07 04:48:08 PM PDT 24
Finished Jul 07 05:28:09 PM PDT 24
Peak memory 290092 kb
Host smart-253b9943-e5f5-4bdd-8060-6d4c8bc15e83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146316850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3146316850
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1515443100
Short name T624
Test name
Test status
Simulation time 316593407 ps
CPU time 15.7 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:48:22 PM PDT 24
Peak memory 249060 kb
Host smart-09800d24-2d0e-49be-8b6c-a98181abadf4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1515443100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1515443100
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1615707007
Short name T676
Test name
Test status
Simulation time 2672762167 ps
CPU time 44.48 seconds
Started Jul 07 04:47:50 PM PDT 24
Finished Jul 07 04:48:35 PM PDT 24
Peak memory 256588 kb
Host smart-8d545309-d2bd-4232-84b4-b992459f26bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16157
07007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1615707007
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2889909473
Short name T638
Test name
Test status
Simulation time 614680198 ps
CPU time 18.29 seconds
Started Jul 07 04:47:59 PM PDT 24
Finished Jul 07 04:48:18 PM PDT 24
Peak memory 248600 kb
Host smart-66b4bc5b-192d-4b64-8010-33a86fc3736a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28899
09473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2889909473
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2782823322
Short name T322
Test name
Test status
Simulation time 58125289524 ps
CPU time 1631.25 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 05:15:21 PM PDT 24
Peak memory 273736 kb
Host smart-56d00110-392b-454c-b555-49b2dc8d53bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782823322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2782823322
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3059542781
Short name T367
Test name
Test status
Simulation time 107132435478 ps
CPU time 1583.4 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 05:14:20 PM PDT 24
Peak memory 273856 kb
Host smart-e186f568-5962-4e31-8000-37bebf9c18ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059542781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3059542781
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1238019764
Short name T296
Test name
Test status
Simulation time 12229794988 ps
CPU time 494.74 seconds
Started Jul 07 04:48:02 PM PDT 24
Finished Jul 07 04:56:17 PM PDT 24
Peak memory 249340 kb
Host smart-e0822352-61b3-4166-9e6f-da295839200b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238019764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1238019764
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1522397032
Short name T654
Test name
Test status
Simulation time 435509522 ps
CPU time 34.71 seconds
Started Jul 07 04:47:54 PM PDT 24
Finished Jul 07 04:48:29 PM PDT 24
Peak memory 256620 kb
Host smart-cdd96c9d-b56d-4414-a891-f31cd2670974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15223
97032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1522397032
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1923680824
Short name T655
Test name
Test status
Simulation time 608066645 ps
CPU time 28.48 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 04:48:38 PM PDT 24
Peak memory 256636 kb
Host smart-94c491ea-4c20-4a98-ad8d-24585ade12b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19236
80824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1923680824
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1931044652
Short name T320
Test name
Test status
Simulation time 151600270 ps
CPU time 11.02 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 04:48:07 PM PDT 24
Peak memory 254028 kb
Host smart-97c56155-9ab6-4469-8a28-395c3c7366b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
44652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1931044652
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1811320178
Short name T548
Test name
Test status
Simulation time 736792463 ps
CPU time 13.28 seconds
Started Jul 07 04:47:59 PM PDT 24
Finished Jul 07 04:48:13 PM PDT 24
Peak memory 255268 kb
Host smart-2414bcc5-9f9e-42eb-8601-681aa6f2cb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18113
20178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1811320178
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.437241076
Short name T291
Test name
Test status
Simulation time 40020004877 ps
CPU time 1359.54 seconds
Started Jul 07 04:48:03 PM PDT 24
Finished Jul 07 05:10:43 PM PDT 24
Peak memory 290016 kb
Host smart-90d287c1-4447-440c-8c63-8439f6688e5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437241076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.437241076
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1364243824
Short name T229
Test name
Test status
Simulation time 43665052644 ps
CPU time 1579.04 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 05:14:29 PM PDT 24
Peak memory 284588 kb
Host smart-cc04b57d-31e7-4119-9b83-4ee3544c6be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364243824 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1364243824
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3468792240
Short name T195
Test name
Test status
Simulation time 35025075 ps
CPU time 3.58 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 04:47:30 PM PDT 24
Peak memory 249844 kb
Host smart-6e56806e-680e-4fe5-96c3-952a1700a194
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3468792240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3468792240
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2972132740
Short name T103
Test name
Test status
Simulation time 15360929728 ps
CPU time 1461.99 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 05:11:49 PM PDT 24
Peak memory 290188 kb
Host smart-b296ed2c-7048-46a5-bf26-ea6fb83ac557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972132740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2972132740
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.4014339782
Short name T677
Test name
Test status
Simulation time 1438038074 ps
CPU time 8.62 seconds
Started Jul 07 04:47:25 PM PDT 24
Finished Jul 07 04:47:35 PM PDT 24
Peak memory 249136 kb
Host smart-66889271-20df-4254-b232-e5e3209d2c11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4014339782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.4014339782
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3411948355
Short name T604
Test name
Test status
Simulation time 1217540271 ps
CPU time 45.37 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 04:48:12 PM PDT 24
Peak memory 257252 kb
Host smart-7c55d42f-4d64-47d0-816f-f3ddc4903437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34119
48355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3411948355
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.628151707
Short name T538
Test name
Test status
Simulation time 670084215 ps
CPU time 39.98 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:48:07 PM PDT 24
Peak memory 256300 kb
Host smart-1fe3f348-a3ad-46a7-80da-0e1fba601225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62815
1707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.628151707
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3568582512
Short name T333
Test name
Test status
Simulation time 211621718331 ps
CPU time 1353.46 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 05:10:03 PM PDT 24
Peak memory 290120 kb
Host smart-bf704bf6-f942-4ac6-a0e5-1448e03a570b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568582512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3568582512
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2226509376
Short name T69
Test name
Test status
Simulation time 8507504563 ps
CPU time 777.61 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 05:00:27 PM PDT 24
Peak memory 273880 kb
Host smart-c042b1b8-d4eb-491b-8cc8-d2e567170cf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226509376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2226509376
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3562899464
Short name T217
Test name
Test status
Simulation time 39394716117 ps
CPU time 89.5 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:49:03 PM PDT 24
Peak memory 249248 kb
Host smart-16180a18-d8e6-4d75-aa80-9141e8d80c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562899464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3562899464
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2301596350
Short name T80
Test name
Test status
Simulation time 648582726 ps
CPU time 40.29 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 04:48:09 PM PDT 24
Peak memory 256348 kb
Host smart-36805a5f-50a9-44e5-a2e7-7563a131f4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23015
96350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2301596350
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1993757955
Short name T428
Test name
Test status
Simulation time 832114051 ps
CPU time 19.2 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:47:51 PM PDT 24
Peak memory 254352 kb
Host smart-ca84c69d-87ef-40c1-90fc-e04433f68e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19937
57955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1993757955
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1843648009
Short name T532
Test name
Test status
Simulation time 188598037 ps
CPU time 14.44 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 04:47:42 PM PDT 24
Peak memory 249072 kb
Host smart-8a4de670-e506-41ac-9aec-ee43b82d7415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18436
48009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1843648009
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4138131025
Short name T446
Test name
Test status
Simulation time 156441788 ps
CPU time 9.28 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:47:37 PM PDT 24
Peak memory 255292 kb
Host smart-fbf651bf-4364-49e8-a49b-2c3a1793acf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41381
31025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4138131025
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3514085285
Short name T610
Test name
Test status
Simulation time 178487082702 ps
CPU time 4120.53 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 298420 kb
Host smart-0ee14ed2-d2e3-4b43-ae5c-b09c54569ae0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514085285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3514085285
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3389956663
Short name T260
Test name
Test status
Simulation time 39530975979 ps
CPU time 2724.82 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 289908 kb
Host smart-f8f86daa-da68-41f1-8d56-bb7b7ebf9f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389956663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3389956663
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3683076242
Short name T583
Test name
Test status
Simulation time 1920154231 ps
CPU time 156.05 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 04:50:48 PM PDT 24
Peak memory 256564 kb
Host smart-93e8fe59-b75f-4625-ae16-51bf1adb1362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36830
76242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3683076242
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1191623292
Short name T375
Test name
Test status
Simulation time 1012155425 ps
CPU time 29.83 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 248572 kb
Host smart-374b0bfa-12a1-447b-a70d-4179df27315e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
23292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1191623292
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2844947650
Short name T340
Test name
Test status
Simulation time 40061814060 ps
CPU time 2209.16 seconds
Started Jul 07 04:48:14 PM PDT 24
Finished Jul 07 05:25:04 PM PDT 24
Peak memory 288448 kb
Host smart-d2a287ba-1654-4cae-8286-9d912b3641be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844947650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2844947650
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2756593787
Short name T57
Test name
Test status
Simulation time 27318102316 ps
CPU time 896.54 seconds
Started Jul 07 04:48:01 PM PDT 24
Finished Jul 07 05:02:58 PM PDT 24
Peak memory 273292 kb
Host smart-7f3eb26e-0cfd-44e2-bc7f-4e79ba4b88dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756593787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2756593787
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.435314996
Short name T305
Test name
Test status
Simulation time 20291591032 ps
CPU time 392.63 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:54:53 PM PDT 24
Peak memory 255800 kb
Host smart-441e197a-a0a7-448d-8ffb-857af1fed3ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435314996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.435314996
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.709233672
Short name T370
Test name
Test status
Simulation time 992963769 ps
CPU time 58.09 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:49:04 PM PDT 24
Peak memory 249112 kb
Host smart-595c1662-fedf-4d11-a4cf-88956af62cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70923
3672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.709233672
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2044158740
Short name T679
Test name
Test status
Simulation time 2674314845 ps
CPU time 44.62 seconds
Started Jul 07 04:48:01 PM PDT 24
Finished Jul 07 04:48:46 PM PDT 24
Peak memory 249372 kb
Host smart-6f78dbd8-dc26-456d-8bda-d68a08f9c3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20441
58740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2044158740
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.140024062
Short name T420
Test name
Test status
Simulation time 357129291 ps
CPU time 21.18 seconds
Started Jul 07 04:48:04 PM PDT 24
Finished Jul 07 04:48:25 PM PDT 24
Peak memory 249812 kb
Host smart-332bcb11-8d64-48ef-90bb-c7f1d6b77e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14002
4062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.140024062
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.362116776
Short name T475
Test name
Test status
Simulation time 488558169 ps
CPU time 14.94 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 04:48:32 PM PDT 24
Peak memory 257320 kb
Host smart-5c1a42e8-8c67-47d9-b1c7-bc972559fdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211
6776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.362116776
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.89036364
Short name T537
Test name
Test status
Simulation time 66278866486 ps
CPU time 3504.91 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 306164 kb
Host smart-202f39ee-89a0-4525-bb47-167d8974e11a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89036364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_hand
ler_stress_all.89036364
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3001077785
Short name T227
Test name
Test status
Simulation time 57895023329 ps
CPU time 3253.37 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:42:34 PM PDT 24
Peak memory 306492 kb
Host smart-96822902-9ebe-45c5-9382-edf5a2653ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001077785 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3001077785
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.604831549
Short name T625
Test name
Test status
Simulation time 20401953893 ps
CPU time 1254.98 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 05:09:10 PM PDT 24
Peak memory 273176 kb
Host smart-cd1970e6-6d35-4c55-b86f-2c695a191dd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604831549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.604831549
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2092701280
Short name T398
Test name
Test status
Simulation time 4226444623 ps
CPU time 242.36 seconds
Started Jul 07 04:48:10 PM PDT 24
Finished Jul 07 04:52:12 PM PDT 24
Peak memory 256960 kb
Host smart-0147d875-3ebb-489c-84ea-0714d8693041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20927
01280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2092701280
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3832480504
Short name T459
Test name
Test status
Simulation time 520968255 ps
CPU time 29.82 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:48:36 PM PDT 24
Peak memory 256332 kb
Host smart-c47d3523-f5f0-437b-8be0-2f9ae62c2efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38324
80504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3832480504
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1111620332
Short name T278
Test name
Test status
Simulation time 18451310647 ps
CPU time 1524.41 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 05:13:43 PM PDT 24
Peak memory 288824 kb
Host smart-ab4a08ec-a33c-42b3-9d84-2eae266bc604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111620332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1111620332
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1748223267
Short name T589
Test name
Test status
Simulation time 70623658633 ps
CPU time 2096.41 seconds
Started Jul 07 04:48:08 PM PDT 24
Finished Jul 07 05:23:05 PM PDT 24
Peak memory 283016 kb
Host smart-b79e60fd-1501-47ee-9ba4-0720e1a659fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748223267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1748223267
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3946098191
Short name T530
Test name
Test status
Simulation time 21542380 ps
CPU time 2.81 seconds
Started Jul 07 04:48:19 PM PDT 24
Finished Jul 07 04:48:23 PM PDT 24
Peak memory 249080 kb
Host smart-63ba076b-2ca9-400e-8358-d1ac13a66b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39460
98191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3946098191
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3390074048
Short name T89
Test name
Test status
Simulation time 323286976 ps
CPU time 21.45 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:48:35 PM PDT 24
Peak memory 256328 kb
Host smart-c1d2d0a5-8236-4494-a2b7-c2846d422c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33900
74048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3390074048
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1483111822
Short name T268
Test name
Test status
Simulation time 814221922 ps
CPU time 29.31 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 248748 kb
Host smart-9f7b41b0-1c93-446e-9544-860b7f6504e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
11822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1483111822
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1854709711
Short name T680
Test name
Test status
Simulation time 283350530 ps
CPU time 9.61 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 04:48:26 PM PDT 24
Peak memory 255232 kb
Host smart-f98d391c-64f2-4991-b7a7-5c69e814d8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
09711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1854709711
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2077518369
Short name T93
Test name
Test status
Simulation time 102586659357 ps
CPU time 2020.51 seconds
Started Jul 07 04:48:14 PM PDT 24
Finished Jul 07 05:21:55 PM PDT 24
Peak memory 290288 kb
Host smart-83e80bf8-0ef4-460f-9c6f-87831093c151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077518369 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2077518369
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3783574392
Short name T689
Test name
Test status
Simulation time 36746495984 ps
CPU time 2519.82 seconds
Started Jul 07 04:47:56 PM PDT 24
Finished Jul 07 05:30:02 PM PDT 24
Peak memory 289964 kb
Host smart-1299703e-275d-4368-8adc-b973ac9ea138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783574392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3783574392
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1499701394
Short name T461
Test name
Test status
Simulation time 1728696545 ps
CPU time 155.44 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:51:02 PM PDT 24
Peak memory 256620 kb
Host smart-5b59bc95-3466-429c-b01e-14075b81b49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14997
01394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1499701394
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4069248757
Short name T552
Test name
Test status
Simulation time 242193346 ps
CPU time 15.42 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:48:22 PM PDT 24
Peak memory 248780 kb
Host smart-42d4b986-b8a1-4543-ad80-910d3bf1d9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40692
48757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4069248757
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3004020197
Short name T668
Test name
Test status
Simulation time 57199056888 ps
CPU time 1934.4 seconds
Started Jul 07 04:48:04 PM PDT 24
Finished Jul 07 05:20:19 PM PDT 24
Peak memory 284276 kb
Host smart-2d1eaf5d-f237-459a-b406-1bbc2a1f19aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004020197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3004020197
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3886552123
Short name T685
Test name
Test status
Simulation time 26581592252 ps
CPU time 1599.05 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 05:14:58 PM PDT 24
Peak memory 282472 kb
Host smart-606b29c8-cf41-4794-a07e-a02c1b43f108
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886552123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3886552123
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.114336996
Short name T313
Test name
Test status
Simulation time 6787413591 ps
CPU time 263.69 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 04:52:40 PM PDT 24
Peak memory 249076 kb
Host smart-ee615f2c-37af-4494-8199-6ad8321be6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114336996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.114336996
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.816272269
Short name T28
Test name
Test status
Simulation time 2061519618 ps
CPU time 13.18 seconds
Started Jul 07 04:48:26 PM PDT 24
Finished Jul 07 04:48:40 PM PDT 24
Peak memory 257216 kb
Host smart-92f8fe69-1673-4963-baff-bef0e64976c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81627
2269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.816272269
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.595883662
Short name T559
Test name
Test status
Simulation time 860283647 ps
CPU time 21.65 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 04:48:29 PM PDT 24
Peak memory 249144 kb
Host smart-8e8f6d91-a307-4c47-adf3-f5f737700fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59588
3662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.595883662
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3595062115
Short name T259
Test name
Test status
Simulation time 804726013 ps
CPU time 24.87 seconds
Started Jul 07 04:48:30 PM PDT 24
Finished Jul 07 04:48:55 PM PDT 24
Peak memory 256976 kb
Host smart-68b63882-7f71-489e-9f39-be0062d9c0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
62115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3595062115
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.645007164
Short name T690
Test name
Test status
Simulation time 3584703862 ps
CPU time 47.97 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 256472 kb
Host smart-b7912587-1ad3-41a9-9e53-9685c348f3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64500
7164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.645007164
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3555763947
Short name T51
Test name
Test status
Simulation time 9950780500 ps
CPU time 545.29 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 04:57:22 PM PDT 24
Peak memory 257420 kb
Host smart-7184ec82-b44a-4e5a-8c12-91149b7afe34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555763947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3555763947
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.562648628
Short name T504
Test name
Test status
Simulation time 41425394436 ps
CPU time 4078.77 seconds
Started Jul 07 04:48:14 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 355296 kb
Host smart-a0abcf2f-ee73-484a-b97a-668b95114fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562648628 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.562648628
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2421082411
Short name T46
Test name
Test status
Simulation time 19549578400 ps
CPU time 1029.89 seconds
Started Jul 07 04:48:08 PM PDT 24
Finished Jul 07 05:05:18 PM PDT 24
Peak memory 282716 kb
Host smart-49ed46c3-8112-43b3-b986-43835beae5e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421082411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2421082411
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3065634257
Short name T431
Test name
Test status
Simulation time 3072050040 ps
CPU time 66.31 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 257004 kb
Host smart-1af9621f-60a1-45ca-97ff-a491e1c597d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
34257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3065634257
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4167330724
Short name T386
Test name
Test status
Simulation time 31719999 ps
CPU time 4.19 seconds
Started Jul 07 04:48:10 PM PDT 24
Finished Jul 07 04:48:15 PM PDT 24
Peak memory 249180 kb
Host smart-32727f20-a982-4a36-89ca-f116ebf0d492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
30724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4167330724
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2107900099
Short name T617
Test name
Test status
Simulation time 34758970398 ps
CPU time 359.45 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 04:54:09 PM PDT 24
Peak memory 255632 kb
Host smart-0af7f198-e184-4bda-8fe0-cf00f9dd5a28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107900099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2107900099
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3842540985
Short name T672
Test name
Test status
Simulation time 3061745478 ps
CPU time 30.51 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:48:37 PM PDT 24
Peak memory 256764 kb
Host smart-e1bbbab7-5c53-4774-84fb-b7c831f0f5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38425
40985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3842540985
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4223156312
Short name T540
Test name
Test status
Simulation time 310122259 ps
CPU time 9.08 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 04:48:25 PM PDT 24
Peak memory 257040 kb
Host smart-6ee19c49-146f-4d43-9913-9e5f277a98fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42231
56312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4223156312
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2041795046
Short name T252
Test name
Test status
Simulation time 1154715396 ps
CPU time 43.97 seconds
Started Jul 07 04:48:06 PM PDT 24
Finished Jul 07 04:48:51 PM PDT 24
Peak memory 256536 kb
Host smart-f3a7efb4-ad74-41f5-a407-032d7e02162e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20417
95046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2041795046
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1341678519
Short name T476
Test name
Test status
Simulation time 13353857196 ps
CPU time 39.78 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 04:48:51 PM PDT 24
Peak memory 256428 kb
Host smart-76d85210-e9d5-4f8e-9491-a6043fd545ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
78519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1341678519
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1216743074
Short name T37
Test name
Test status
Simulation time 38316402035 ps
CPU time 2363.54 seconds
Started Jul 07 04:48:09 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 289760 kb
Host smart-eb393a4b-93c8-4b7c-8118-cf6e642cbaed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216743074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1216743074
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1296333172
Short name T277
Test name
Test status
Simulation time 659049337148 ps
CPU time 4597.65 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 06:04:50 PM PDT 24
Peak memory 339080 kb
Host smart-0bbaefe2-428b-4651-b988-f112f9b5fc00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296333172 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1296333172
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.645770334
Short name T441
Test name
Test status
Simulation time 28781923812 ps
CPU time 2055.58 seconds
Started Jul 07 04:48:00 PM PDT 24
Finished Jul 07 05:22:16 PM PDT 24
Peak memory 281520 kb
Host smart-01e2a62e-b769-40d0-b818-7ad6a45bff5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645770334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.645770334
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.224933895
Short name T416
Test name
Test status
Simulation time 1775829415 ps
CPU time 122.16 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 04:50:14 PM PDT 24
Peak memory 257308 kb
Host smart-d2761040-7e72-48ab-a961-d68b3cd6aa7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22493
3895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.224933895
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2744684731
Short name T520
Test name
Test status
Simulation time 1506092458 ps
CPU time 48.93 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 04:49:12 PM PDT 24
Peak memory 256404 kb
Host smart-aa6fb435-9e37-4015-8338-c6b1bab363cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27446
84731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2744684731
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1166301811
Short name T286
Test name
Test status
Simulation time 63826387166 ps
CPU time 1586.45 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 05:14:44 PM PDT 24
Peak memory 286232 kb
Host smart-e54efdb9-d1c0-4460-889a-92cf4d9d683d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166301811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1166301811
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2864044588
Short name T8
Test name
Test status
Simulation time 11219256039 ps
CPU time 1041.11 seconds
Started Jul 07 04:48:01 PM PDT 24
Finished Jul 07 05:05:23 PM PDT 24
Peak memory 273812 kb
Host smart-388fbb96-a09d-4fb7-88a5-737fd0c4ccd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864044588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2864044588
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1471039906
Short name T490
Test name
Test status
Simulation time 162117582 ps
CPU time 16.38 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 04:48:29 PM PDT 24
Peak memory 256688 kb
Host smart-e32a6f02-402e-4bc3-b85a-7ddc5a9cd07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14710
39906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1471039906
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1589904922
Short name T412
Test name
Test status
Simulation time 378901299 ps
CPU time 42.67 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:49:01 PM PDT 24
Peak memory 249052 kb
Host smart-4b958f12-15c4-48a5-9b6f-5a04ae5f1230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15899
04922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1589904922
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1234886567
Short name T456
Test name
Test status
Simulation time 305735517 ps
CPU time 28.77 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 257404 kb
Host smart-a5ccc49b-bd53-46ba-8886-2f6e3816bb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12348
86567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1234886567
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3455534962
Short name T72
Test name
Test status
Simulation time 229899611907 ps
CPU time 3700.31 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 298964 kb
Host smart-4854a6f3-877c-4819-8fce-35ff858c31be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455534962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3455534962
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4019473246
Short name T40
Test name
Test status
Simulation time 52838715302 ps
CPU time 4641.69 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 06:05:44 PM PDT 24
Peak memory 355212 kb
Host smart-272436d8-d7fe-4aff-b1a2-c5901f6b0bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019473246 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4019473246
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1496690716
Short name T38
Test name
Test status
Simulation time 127514341565 ps
CPU time 2183.03 seconds
Started Jul 07 04:48:14 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 283276 kb
Host smart-45648ed1-6f15-4dc4-ac08-7d3235d871bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496690716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1496690716
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1220217259
Short name T674
Test name
Test status
Simulation time 2243752810 ps
CPU time 52.56 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 257384 kb
Host smart-9eb58f54-4f2e-43dd-8c2d-2b24e554b1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12202
17259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1220217259
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.882272860
Short name T598
Test name
Test status
Simulation time 1388772336 ps
CPU time 23.33 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 04:48:35 PM PDT 24
Peak memory 248604 kb
Host smart-679a51f0-5346-4f4b-a746-3c760b22d3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88227
2860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.882272860
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3512934087
Short name T330
Test name
Test status
Simulation time 91953868277 ps
CPU time 1432.98 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 05:12:05 PM PDT 24
Peak memory 273764 kb
Host smart-eba7ee2b-5c88-4050-a0ab-d742653d4390
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512934087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3512934087
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.737522436
Short name T378
Test name
Test status
Simulation time 10441369211 ps
CPU time 983.02 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 05:04:39 PM PDT 24
Peak memory 287524 kb
Host smart-6ec7b21d-582b-424c-ab7d-1f60ae11dd30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737522436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.737522436
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.379736520
Short name T12
Test name
Test status
Simulation time 7733958084 ps
CPU time 334.27 seconds
Started Jul 07 04:48:08 PM PDT 24
Finished Jul 07 04:53:42 PM PDT 24
Peak memory 249668 kb
Host smart-0f82efc8-da03-43d2-9f6f-46e133f8f4a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379736520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.379736520
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3802697181
Short name T703
Test name
Test status
Simulation time 927705981 ps
CPU time 57.76 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 256568 kb
Host smart-9e69dd67-7f92-4ba0-b0d4-019e188f4470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38026
97181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3802697181
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2419161358
Short name T29
Test name
Test status
Simulation time 583794964 ps
CPU time 9.14 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:48:31 PM PDT 24
Peak memory 248656 kb
Host smart-f26eeb29-6bc4-4d91-84e7-38c282abd5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24191
61358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2419161358
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2387224968
Short name T613
Test name
Test status
Simulation time 45061571 ps
CPU time 6.94 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 04:48:23 PM PDT 24
Peak memory 253412 kb
Host smart-0f502614-b772-4ad7-979c-aa4394ebffe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23872
24968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2387224968
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2774687046
Short name T380
Test name
Test status
Simulation time 99617323 ps
CPU time 7.18 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 04:48:44 PM PDT 24
Peak memory 252232 kb
Host smart-5c838818-1bbe-439d-a6d5-2721e84286af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27746
87046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2774687046
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2324903728
Short name T241
Test name
Test status
Simulation time 160733948729 ps
CPU time 2712.73 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 289584 kb
Host smart-af9d48ea-1d84-45f6-9a01-9fd23eaa47e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324903728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2324903728
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.589325304
Short name T76
Test name
Test status
Simulation time 39359339568 ps
CPU time 2439 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 290388 kb
Host smart-e4a988c5-206d-4b6c-a0ab-0fde151b5f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589325304 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.589325304
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2917031106
Short name T86
Test name
Test status
Simulation time 18286058093 ps
CPU time 842.99 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 05:02:16 PM PDT 24
Peak memory 273672 kb
Host smart-9b4961bd-65b4-4ff1-96dd-b24cfa913beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917031106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2917031106
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2559188957
Short name T392
Test name
Test status
Simulation time 7567361861 ps
CPU time 145.39 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:50:48 PM PDT 24
Peak memory 257388 kb
Host smart-22635c1e-35ac-4381-83f1-10a224a9f4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
88957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2559188957
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3274215259
Short name T607
Test name
Test status
Simulation time 4596390484 ps
CPU time 28.23 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:48:49 PM PDT 24
Peak memory 257192 kb
Host smart-1c0f06aa-8a7a-4198-bcfb-596ea567e0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32742
15259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3274215259
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1913731207
Short name T314
Test name
Test status
Simulation time 6956951802 ps
CPU time 707.54 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 04:59:55 PM PDT 24
Peak memory 273116 kb
Host smart-0b35d653-9634-439e-8f73-1143b6aa618c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913731207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1913731207
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3236516244
Short name T662
Test name
Test status
Simulation time 122884628080 ps
CPU time 2007.42 seconds
Started Jul 07 04:48:19 PM PDT 24
Finished Jul 07 05:21:47 PM PDT 24
Peak memory 284876 kb
Host smart-fe1d2cca-40f0-46b3-b0bc-9824c3e5c887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236516244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3236516244
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.139083054
Short name T299
Test name
Test status
Simulation time 15189366811 ps
CPU time 335.15 seconds
Started Jul 07 04:48:19 PM PDT 24
Finished Jul 07 04:53:55 PM PDT 24
Peak memory 249256 kb
Host smart-8913dc71-50bd-4e0b-84be-a7f7853c1811
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139083054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.139083054
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.331136319
Short name T395
Test name
Test status
Simulation time 27596725 ps
CPU time 4.34 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:48:28 PM PDT 24
Peak memory 249112 kb
Host smart-338c4cb9-fb2c-45ab-a9b4-de8f4847d960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33113
6319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.331136319
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4279965320
Short name T3
Test name
Test status
Simulation time 254112645 ps
CPU time 17.87 seconds
Started Jul 07 04:48:08 PM PDT 24
Finished Jul 07 04:48:26 PM PDT 24
Peak memory 248552 kb
Host smart-9274f92a-46bf-4b90-87af-62d81514d83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
65320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4279965320
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2464025432
Short name T555
Test name
Test status
Simulation time 983959085 ps
CPU time 19.06 seconds
Started Jul 07 04:48:19 PM PDT 24
Finished Jul 07 04:48:38 PM PDT 24
Peak memory 256708 kb
Host smart-74649cee-8f4f-48ca-ac87-653da7b93078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24640
25432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2464025432
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1363528914
Short name T433
Test name
Test status
Simulation time 274047208 ps
CPU time 24.38 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:48:43 PM PDT 24
Peak memory 257276 kb
Host smart-fbb79cc0-4ffb-478a-a3aa-1826478fd221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13635
28914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1363528914
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1597757517
Short name T83
Test name
Test status
Simulation time 68215071563 ps
CPU time 3856.87 seconds
Started Jul 07 04:48:07 PM PDT 24
Finished Jul 07 05:52:24 PM PDT 24
Peak memory 302124 kb
Host smart-944e538c-26cb-49ff-9061-5ec3ca52ca4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597757517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1597757517
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2102085419
Short name T92
Test name
Test status
Simulation time 12106376284 ps
CPU time 1087.76 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 05:06:21 PM PDT 24
Peak memory 289980 kb
Host smart-48fedb57-2b73-4c02-a6b5-8c69c0a81d14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102085419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2102085419
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2244589436
Short name T664
Test name
Test status
Simulation time 843089837 ps
CPU time 51.09 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 256876 kb
Host smart-843e2c03-e4c5-4aaf-bf1d-051434157217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445
89436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2244589436
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3996353654
Short name T463
Test name
Test status
Simulation time 599668573 ps
CPU time 21.12 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 04:48:36 PM PDT 24
Peak memory 248524 kb
Host smart-cc8a7d2d-676c-475b-bb2f-62673c959c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
53654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3996353654
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4064230136
Short name T321
Test name
Test status
Simulation time 225885026515 ps
CPU time 1003.07 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 05:04:54 PM PDT 24
Peak memory 273032 kb
Host smart-3eb7a790-54a4-458e-a6e4-487096a98bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064230136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4064230136
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1935713556
Short name T594
Test name
Test status
Simulation time 42236555926 ps
CPU time 1312.43 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 05:10:09 PM PDT 24
Peak memory 273512 kb
Host smart-7dc32b1e-907b-44e8-a154-11b7daa7aed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935713556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1935713556
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1662523972
Short name T177
Test name
Test status
Simulation time 7293343450 ps
CPU time 291.48 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:53:10 PM PDT 24
Peak memory 248932 kb
Host smart-430e0a80-5add-481b-acc1-b9547a29ce46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662523972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1662523972
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3515842448
Short name T23
Test name
Test status
Simulation time 228350622 ps
CPU time 9.32 seconds
Started Jul 07 04:48:26 PM PDT 24
Finished Jul 07 04:48:36 PM PDT 24
Peak memory 257248 kb
Host smart-f35ca748-fdf3-49bd-91cf-56aea268dd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35158
42448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3515842448
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4041833231
Short name T573
Test name
Test status
Simulation time 382474560 ps
CPU time 8.56 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 04:48:38 PM PDT 24
Peak memory 248644 kb
Host smart-b8197557-e481-4eac-8b10-67163fe3bb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
33231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4041833231
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1437831054
Short name T251
Test name
Test status
Simulation time 550808203 ps
CPU time 27.67 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 04:48:45 PM PDT 24
Peak memory 257028 kb
Host smart-a90f4c77-5d39-444f-afa8-7f002c4c867d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14378
31054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1437831054
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1593504410
Short name T686
Test name
Test status
Simulation time 3968291993 ps
CPU time 55.79 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:49:15 PM PDT 24
Peak memory 257016 kb
Host smart-32de58f0-0cea-4848-80ba-034a8acd9a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
04410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1593504410
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3066234567
Short name T261
Test name
Test status
Simulation time 153326608577 ps
CPU time 4097.19 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 05:56:30 PM PDT 24
Peak memory 297876 kb
Host smart-6214ddbc-f7bc-4894-90fa-79ce79c8dfbc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066234567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3066234567
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1991779062
Short name T694
Test name
Test status
Simulation time 303012048258 ps
CPU time 1643.33 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 05:15:57 PM PDT 24
Peak memory 269696 kb
Host smart-ab646d32-04f3-4e69-b0d8-24cd40c3f72b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991779062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1991779062
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1339885790
Short name T273
Test name
Test status
Simulation time 7028455900 ps
CPU time 110.41 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:50:13 PM PDT 24
Peak memory 257040 kb
Host smart-7d8a3a3f-ecb8-4c26-ae10-9ec5c7bc1fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398
85790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1339885790
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3650238428
Short name T485
Test name
Test status
Simulation time 1198283373 ps
CPU time 20.15 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 248940 kb
Host smart-1a8ad3f1-bc7f-4699-b028-22154bf14e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
38428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3650238428
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1460597307
Short name T19
Test name
Test status
Simulation time 11648006644 ps
CPU time 966.19 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 05:04:29 PM PDT 24
Peak memory 273684 kb
Host smart-f27f122c-1e29-4b0d-893f-585cbc8b0f26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460597307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1460597307
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2795290159
Short name T628
Test name
Test status
Simulation time 28388992970 ps
CPU time 1567.16 seconds
Started Jul 07 04:48:19 PM PDT 24
Finished Jul 07 05:14:27 PM PDT 24
Peak memory 273848 kb
Host smart-f5434f8f-723d-4a5d-a33d-210493cf951a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795290159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2795290159
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1658808880
Short name T542
Test name
Test status
Simulation time 6798419633 ps
CPU time 251.33 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 248104 kb
Host smart-b97e366a-2225-4457-af34-300405076c49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658808880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1658808880
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1483162447
Short name T488
Test name
Test status
Simulation time 801909544 ps
CPU time 62.11 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 249140 kb
Host smart-cc3cfd02-5961-4ae5-a098-7c141534efd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
62447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1483162447
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3628295287
Short name T387
Test name
Test status
Simulation time 527764139 ps
CPU time 33.28 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:49:01 PM PDT 24
Peak memory 257260 kb
Host smart-86c599ef-b5ae-4306-a579-94da4ea45ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
95287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3628295287
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1308605853
Short name T31
Test name
Test status
Simulation time 698633745 ps
CPU time 25.64 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:48:53 PM PDT 24
Peak memory 256656 kb
Host smart-1d40bf06-9566-404f-898e-e5c0697c07b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
05853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1308605853
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3506354028
Short name T358
Test name
Test status
Simulation time 2637645172 ps
CPU time 51.56 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:49:12 PM PDT 24
Peak memory 257136 kb
Host smart-8e81481e-3011-49ab-85ad-6ac3f8c58ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
54028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3506354028
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1095586422
Short name T232
Test name
Test status
Simulation time 142613122424 ps
CPU time 7065.77 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 06:46:11 PM PDT 24
Peak memory 355008 kb
Host smart-39842291-db51-4dde-918a-28644c2ad655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095586422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1095586422
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.669815739
Short name T603
Test name
Test status
Simulation time 130669383848 ps
CPU time 1619.32 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 05:15:15 PM PDT 24
Peak memory 273560 kb
Host smart-0d474268-ac9f-44ec-b4fd-07c6559ce2e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669815739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.669815739
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1210795145
Short name T627
Test name
Test status
Simulation time 909078423 ps
CPU time 53.61 seconds
Started Jul 07 04:48:31 PM PDT 24
Finished Jul 07 04:49:25 PM PDT 24
Peak memory 256800 kb
Host smart-4f5b001d-7309-434f-891d-899bfb0d4c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
95145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1210795145
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2258142883
Short name T531
Test name
Test status
Simulation time 1261860851 ps
CPU time 42.48 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 256060 kb
Host smart-826456b7-6b54-4ce2-ac80-fbb73c62482c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22581
42883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2258142883
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1718445941
Short name T325
Test name
Test status
Simulation time 54635396570 ps
CPU time 1677.87 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:16:19 PM PDT 24
Peak memory 273812 kb
Host smart-9c4f4c31-8342-4e29-80d5-28bc627063d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718445941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1718445941
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2753577947
Short name T612
Test name
Test status
Simulation time 51670747034 ps
CPU time 558.17 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:57:44 PM PDT 24
Peak memory 249340 kb
Host smart-6412da96-10ac-4986-9cd6-8d906f91840f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753577947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2753577947
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3100669282
Short name T500
Test name
Test status
Simulation time 335109320 ps
CPU time 30.21 seconds
Started Jul 07 04:48:29 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 256524 kb
Host smart-dd06a06d-252e-4462-94c8-1d09af46d24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006
69282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3100669282
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.456040723
Short name T100
Test name
Test status
Simulation time 463114794 ps
CPU time 9.24 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:48:29 PM PDT 24
Peak memory 249208 kb
Host smart-d51caca2-d39e-427d-aed2-8288c0a87495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45604
0723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.456040723
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4006848157
Short name T65
Test name
Test status
Simulation time 602254566 ps
CPU time 19.32 seconds
Started Jul 07 04:48:29 PM PDT 24
Finished Jul 07 04:48:49 PM PDT 24
Peak memory 256016 kb
Host smart-16f12f98-c71c-4f0b-9940-8d93885d18bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40068
48157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4006848157
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.869842811
Short name T576
Test name
Test status
Simulation time 1094445936 ps
CPU time 66.84 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:49:33 PM PDT 24
Peak memory 256456 kb
Host smart-d5e90ac7-e072-4e30-8f8b-6004de493303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86984
2811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.869842811
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.591105560
Short name T590
Test name
Test status
Simulation time 11933014752 ps
CPU time 1072.99 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:06:13 PM PDT 24
Peak memory 282836 kb
Host smart-7c45ed05-9ce5-41c0-bdc3-34ac6f3e50a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591105560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.591105560
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1220751097
Short name T194
Test name
Test status
Simulation time 51160752 ps
CPU time 4.35 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 04:47:34 PM PDT 24
Peak memory 249408 kb
Host smart-b96e3458-14ea-4ee1-995c-ca6748113738
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1220751097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1220751097
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3198155950
Short name T84
Test name
Test status
Simulation time 14608887784 ps
CPU time 806.34 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 05:01:02 PM PDT 24
Peak memory 273828 kb
Host smart-7b990046-b9ce-43d7-81f0-aac0f3f31630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198155950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3198155950
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3122613503
Short name T658
Test name
Test status
Simulation time 176850893 ps
CPU time 11.09 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:47:45 PM PDT 24
Peak memory 249156 kb
Host smart-0273d0e5-b378-4bf6-ac6f-50328e70714d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3122613503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3122613503
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3386810644
Short name T473
Test name
Test status
Simulation time 8207514362 ps
CPU time 130.53 seconds
Started Jul 07 04:47:26 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 257068 kb
Host smart-6757a6f9-ca9d-4cc2-93d4-efcb02c13787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33868
10644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3386810644
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1076426043
Short name T74
Test name
Test status
Simulation time 635627210 ps
CPU time 14.6 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:47:48 PM PDT 24
Peak memory 249076 kb
Host smart-d4714d7d-87f5-4fb7-bf08-f8c9ca120a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10764
26043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1076426043
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3642989173
Short name T334
Test name
Test status
Simulation time 179668402312 ps
CPU time 2755.52 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 285500 kb
Host smart-bafc5c80-996e-45cb-92b5-b5b2f0bdb785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642989173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3642989173
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3941716761
Short name T366
Test name
Test status
Simulation time 1769506340 ps
CPU time 23.89 seconds
Started Jul 07 04:47:25 PM PDT 24
Finished Jul 07 04:47:50 PM PDT 24
Peak memory 249168 kb
Host smart-4939990d-9849-47c8-aeec-1c48cf8ea056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39417
16761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3941716761
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4189957062
Short name T506
Test name
Test status
Simulation time 1178019382 ps
CPU time 12.7 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:47:40 PM PDT 24
Peak memory 255116 kb
Host smart-839b432e-fbec-49aa-972d-0c72b653cf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41899
57062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4189957062
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3402656088
Short name T33
Test name
Test status
Simulation time 3099027191 ps
CPU time 20.35 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 271568 kb
Host smart-9c5c4f1d-494f-4d7e-ad81-5e207d15e2d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3402656088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3402656088
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2696899341
Short name T611
Test name
Test status
Simulation time 2153123842 ps
CPU time 33.72 seconds
Started Jul 07 04:47:27 PM PDT 24
Finished Jul 07 04:48:02 PM PDT 24
Peak memory 257372 kb
Host smart-524603b8-8295-413e-82f9-7e36719248ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26968
99341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2696899341
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2863241150
Short name T77
Test name
Test status
Simulation time 33647653377 ps
CPU time 1598.11 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 05:14:06 PM PDT 24
Peak memory 289860 kb
Host smart-fb89de9a-e5d6-4d9a-9d7e-c083597388f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863241150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2863241150
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3569752929
Short name T231
Test name
Test status
Simulation time 47724124367 ps
CPU time 3290.5 seconds
Started Jul 07 04:47:37 PM PDT 24
Finished Jul 07 05:42:28 PM PDT 24
Peak memory 306168 kb
Host smart-251c66d9-1bbc-4dab-ba92-c1f15966b55e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569752929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3569752929
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.964097975
Short name T516
Test name
Test status
Simulation time 226726339129 ps
CPU time 2587.18 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 05:31:31 PM PDT 24
Peak memory 282064 kb
Host smart-62edc5bb-6eeb-4110-84f7-6b58ff293398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964097975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.964097975
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1370537298
Short name T458
Test name
Test status
Simulation time 205710383 ps
CPU time 12.44 seconds
Started Jul 07 04:48:19 PM PDT 24
Finished Jul 07 04:48:32 PM PDT 24
Peak memory 256588 kb
Host smart-03728653-a6d1-4800-b480-0bf0f0351618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13705
37298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1370537298
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3733376562
Short name T643
Test name
Test status
Simulation time 807209325 ps
CPU time 15.5 seconds
Started Jul 07 04:48:11 PM PDT 24
Finished Jul 07 04:48:27 PM PDT 24
Peak memory 256488 kb
Host smart-b1ecb068-7502-4324-bad9-fa535fcb5620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37333
76562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3733376562
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1191566078
Short name T335
Test name
Test status
Simulation time 34894309815 ps
CPU time 2422.65 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 282476 kb
Host smart-3b8e3af3-4678-4cbc-a432-183b46b07833
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191566078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1191566078
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1849569875
Short name T565
Test name
Test status
Simulation time 45538682136 ps
CPU time 2369.43 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 282720 kb
Host smart-e4ed98df-0898-4e34-936e-2ecd81547628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849569875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1849569875
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2918909009
Short name T682
Test name
Test status
Simulation time 11989943532 ps
CPU time 252.27 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:52:34 PM PDT 24
Peak memory 257208 kb
Host smart-73e96355-9e70-4dad-b570-49f781ef730b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918909009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2918909009
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2975900703
Short name T633
Test name
Test status
Simulation time 1191530930 ps
CPU time 31.74 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:48:54 PM PDT 24
Peak memory 249080 kb
Host smart-1c2b5817-3706-402a-b0ba-0f23f0715d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759
00703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2975900703
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4269577812
Short name T389
Test name
Test status
Simulation time 3937373793 ps
CPU time 63.32 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 04:49:20 PM PDT 24
Peak memory 249436 kb
Host smart-768f562d-c84a-45fc-ab01-1eb6ccd21f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
77812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4269577812
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3940921404
Short name T234
Test name
Test status
Simulation time 3643185653 ps
CPU time 44.73 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:49:12 PM PDT 24
Peak memory 249104 kb
Host smart-6b3f9326-7f40-4188-968e-830f7ab12aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
21404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3940921404
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3367671450
Short name T695
Test name
Test status
Simulation time 165100610 ps
CPU time 13.63 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 04:48:37 PM PDT 24
Peak memory 256300 kb
Host smart-e80784eb-f012-4dc1-aec9-cbd7e3282257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33676
71450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3367671450
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3660888776
Short name T211
Test name
Test status
Simulation time 14165290376 ps
CPU time 474.56 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:56:27 PM PDT 24
Peak memory 257344 kb
Host smart-4aa5b0b8-d6ca-4bfc-8418-8b9ae654306f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660888776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3660888776
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3160752298
Short name T292
Test name
Test status
Simulation time 30438933536 ps
CPU time 1833.53 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 05:18:56 PM PDT 24
Peak memory 289388 kb
Host smart-56d96916-1848-4877-b595-e0f0e0507c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160752298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3160752298
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2602407587
Short name T230
Test name
Test status
Simulation time 3284525616 ps
CPU time 204.58 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:51:43 PM PDT 24
Peak memory 251308 kb
Host smart-22992acb-08d6-43ed-8deb-9003b954e1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
07587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2602407587
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3725850925
Short name T514
Test name
Test status
Simulation time 4153991307 ps
CPU time 70.09 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 04:49:28 PM PDT 24
Peak memory 257024 kb
Host smart-ca361f12-cba0-472d-8dc7-5dc7464b087c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
50925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3725850925
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.116275916
Short name T326
Test name
Test status
Simulation time 8237392512 ps
CPU time 688.8 seconds
Started Jul 07 04:48:13 PM PDT 24
Finished Jul 07 04:59:42 PM PDT 24
Peak memory 273724 kb
Host smart-b87456c0-76fa-45e8-9b8b-d29d5ed6bd0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116275916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.116275916
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3983041662
Short name T88
Test name
Test status
Simulation time 42316943736 ps
CPU time 1463.75 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 05:12:50 PM PDT 24
Peak memory 273700 kb
Host smart-4860598c-6596-4a73-b2d7-0f726c3ebe48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983041662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3983041662
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.43223776
Short name T294
Test name
Test status
Simulation time 38204206700 ps
CPU time 464.62 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 04:55:57 PM PDT 24
Peak memory 255852 kb
Host smart-60c694b5-0e6d-44e3-9cd4-d3b1e3e2e8e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43223776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.43223776
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1041229154
Short name T564
Test name
Test status
Simulation time 995555553 ps
CPU time 53.41 seconds
Started Jul 07 04:48:12 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 256852 kb
Host smart-9316a909-4047-4e82-993f-c272ff74895c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
29154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1041229154
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3555130864
Short name T442
Test name
Test status
Simulation time 170593003 ps
CPU time 19.29 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 257312 kb
Host smart-9d009211-d7b4-4ecd-9b6d-8a3b5e1ccb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
30864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3555130864
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2274201469
Short name T683
Test name
Test status
Simulation time 357222710 ps
CPU time 28.13 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 255212 kb
Host smart-f4e47bf7-906c-40da-891e-5a6fa7fcecce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22742
01469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2274201469
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1162824428
Short name T436
Test name
Test status
Simulation time 1019220377 ps
CPU time 60.12 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 257256 kb
Host smart-962c3264-8dff-461c-9348-d6d7b2b6afda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628
24428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1162824428
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.329607481
Short name T508
Test name
Test status
Simulation time 17904255334 ps
CPU time 1690.66 seconds
Started Jul 07 04:48:31 PM PDT 24
Finished Jul 07 05:16:42 PM PDT 24
Peak memory 289864 kb
Host smart-f99fff1b-6a1c-462b-9b92-0070c0968a39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329607481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.329607481
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2926867967
Short name T546
Test name
Test status
Simulation time 64913514932 ps
CPU time 1613.99 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 05:15:19 PM PDT 24
Peak memory 289400 kb
Host smart-aa1be7c2-c424-41a9-8bf7-55ecd8e9b832
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926867967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2926867967
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1203218501
Short name T362
Test name
Test status
Simulation time 2224006881 ps
CPU time 94.04 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 04:50:10 PM PDT 24
Peak memory 251428 kb
Host smart-ffec7aa3-dee6-478e-957c-f160621969e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
18501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1203218501
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3695471719
Short name T406
Test name
Test status
Simulation time 1318472905 ps
CPU time 36.87 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 256396 kb
Host smart-37b0f81d-a2ae-41c5-8cba-b75d0bfff906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
71719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3695471719
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.620919976
Short name T264
Test name
Test status
Simulation time 88341611553 ps
CPU time 1720.53 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 05:17:03 PM PDT 24
Peak memory 289588 kb
Host smart-55f316df-29d1-41d0-8eb7-b4d1234c9dd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620919976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.620919976
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3493975242
Short name T407
Test name
Test status
Simulation time 27040368275 ps
CPU time 601.52 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:58:23 PM PDT 24
Peak memory 273376 kb
Host smart-5764f10d-5094-43d3-8539-182eb1bf33a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493975242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3493975242
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.880647891
Short name T318
Test name
Test status
Simulation time 40102782249 ps
CPU time 426.73 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 04:55:35 PM PDT 24
Peak memory 248104 kb
Host smart-dfe4b75a-6885-445f-abaa-d629f96c009e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880647891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.880647891
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.262364771
Short name T280
Test name
Test status
Simulation time 384187283 ps
CPU time 38.26 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 256636 kb
Host smart-b43fd477-a999-44b2-8466-b8c94754b98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26236
4771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.262364771
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2542693370
Short name T256
Test name
Test status
Simulation time 4569323310 ps
CPU time 78.44 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:49:51 PM PDT 24
Peak memory 256608 kb
Host smart-ff396866-6332-4b98-942f-2039cbdedcc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25426
93370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2542693370
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.564420511
Short name T391
Test name
Test status
Simulation time 63055513 ps
CPU time 2.84 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:48:38 PM PDT 24
Peak memory 240432 kb
Host smart-f9fc217b-653b-4efb-9b97-e8685b9dd638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56442
0511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.564420511
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.340149424
Short name T215
Test name
Test status
Simulation time 1520991738 ps
CPU time 14.68 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 04:48:38 PM PDT 24
Peak memory 257248 kb
Host smart-66476f27-b5a9-4e38-a3c3-abacf7143aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34014
9424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.340149424
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.393232299
Short name T599
Test name
Test status
Simulation time 49686124710 ps
CPU time 1308.51 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 05:10:17 PM PDT 24
Peak memory 286084 kb
Host smart-02018e91-1047-48f3-b148-f2e16fa10d90
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393232299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.393232299
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1371886727
Short name T396
Test name
Test status
Simulation time 70354513596 ps
CPU time 2072.87 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 288892 kb
Host smart-3e9d80df-cde4-4938-a06f-e35286534a8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371886727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1371886727
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1978658553
Short name T562
Test name
Test status
Simulation time 3992027753 ps
CPU time 94.18 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 04:49:57 PM PDT 24
Peak memory 256620 kb
Host smart-4ff14988-70c5-4953-bb74-9053a3f098e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
58553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1978658553
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.36033188
Short name T650
Test name
Test status
Simulation time 866191090 ps
CPU time 32.71 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 04:49:02 PM PDT 24
Peak memory 248620 kb
Host smart-4ff4d1ef-47e7-4ab1-b83d-06ba6ad448ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36033
188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.36033188
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1660784860
Short name T592
Test name
Test status
Simulation time 26618290136 ps
CPU time 872.41 seconds
Started Jul 07 04:48:30 PM PDT 24
Finished Jul 07 05:03:03 PM PDT 24
Peak memory 273692 kb
Host smart-3824e31a-1590-4a8c-a49c-a8e3d13b82a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660784860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1660784860
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2071395774
Short name T701
Test name
Test status
Simulation time 103639587610 ps
CPU time 2765.31 seconds
Started Jul 07 04:48:30 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 289600 kb
Host smart-9b862540-f898-4c1d-a2c1-e3363602a3cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071395774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2071395774
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.846879461
Short name T302
Test name
Test status
Simulation time 27118854088 ps
CPU time 194.56 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:51:36 PM PDT 24
Peak memory 249252 kb
Host smart-b6acfb3a-7e34-40fa-8d81-348d30a43b86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846879461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.846879461
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3551853972
Short name T545
Test name
Test status
Simulation time 376583417 ps
CPU time 7.66 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:48:28 PM PDT 24
Peak memory 252216 kb
Host smart-ac287767-dc48-456b-9b54-3133d8733756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
53972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3551853972
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2159101332
Short name T569
Test name
Test status
Simulation time 824074313 ps
CPU time 57.91 seconds
Started Jul 07 04:48:16 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 256268 kb
Host smart-7d10eb87-0233-4bae-a988-d8babe8bbde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
01332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2159101332
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3566947624
Short name T255
Test name
Test status
Simulation time 553437980 ps
CPU time 38.51 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 04:48:53 PM PDT 24
Peak memory 257264 kb
Host smart-31332579-a540-4a2b-8fef-ff54ecbed44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35669
47624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3566947624
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4198725188
Short name T373
Test name
Test status
Simulation time 767011959 ps
CPU time 51.04 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 257144 kb
Host smart-d6ee9bed-f0f3-442e-b42d-7aa5f4ded226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
25188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4198725188
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.206911126
Short name T106
Test name
Test status
Simulation time 18723632035 ps
CPU time 312.59 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 04:53:31 PM PDT 24
Peak memory 257416 kb
Host smart-6de519ae-5850-47f6-95dd-a0d9ef4932ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206911126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.206911126
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3774810323
Short name T586
Test name
Test status
Simulation time 325689209059 ps
CPU time 1387.54 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 05:11:34 PM PDT 24
Peak memory 273772 kb
Host smart-661e7520-e63f-442e-a5ec-f0805c5c7ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774810323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3774810323
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3797279625
Short name T383
Test name
Test status
Simulation time 1683465440 ps
CPU time 135.59 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:50:35 PM PDT 24
Peak memory 256828 kb
Host smart-62aaa886-4979-4872-8bbe-1fd5b1c3b13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37972
79625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3797279625
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2639043665
Short name T651
Test name
Test status
Simulation time 16605748390 ps
CPU time 55.15 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 249320 kb
Host smart-bc15ee0e-72a6-477a-85af-57077fac8d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
43665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2639043665
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1127311866
Short name T283
Test name
Test status
Simulation time 84069735865 ps
CPU time 1295.78 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 05:10:05 PM PDT 24
Peak memory 265668 kb
Host smart-7095b547-a170-4833-9539-5592d3c345f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127311866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1127311866
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3923749965
Short name T510
Test name
Test status
Simulation time 9198945663 ps
CPU time 714.25 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 05:00:29 PM PDT 24
Peak memory 273356 kb
Host smart-bed1cae6-7e2c-4493-9f9a-15510c8e2bfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923749965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3923749965
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3972446940
Short name T435
Test name
Test status
Simulation time 1871751038 ps
CPU time 36.16 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:49:02 PM PDT 24
Peak memory 256768 kb
Host smart-e1a2fbba-8190-431d-93fc-5c8e31445083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39724
46940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3972446940
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.856116666
Short name T220
Test name
Test status
Simulation time 623617772 ps
CPU time 17.64 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 04:48:47 PM PDT 24
Peak memory 257104 kb
Host smart-d170a392-9538-4bfa-ac39-25527b7a4ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85611
6666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.856116666
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4243987473
Short name T393
Test name
Test status
Simulation time 61595648 ps
CPU time 4.6 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:48:39 PM PDT 24
Peak memory 240856 kb
Host smart-6227a8b9-f17b-422d-a5ca-6deda34572d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42439
87473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4243987473
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2994233723
Short name T483
Test name
Test status
Simulation time 258520480 ps
CPU time 10.04 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:48:36 PM PDT 24
Peak memory 255684 kb
Host smart-9fa27a44-6bfa-4d90-b9e3-b106eadb596a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29942
33723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2994233723
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1936757375
Short name T566
Test name
Test status
Simulation time 48444121036 ps
CPU time 1246.57 seconds
Started Jul 07 04:48:17 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 289724 kb
Host smart-6e977011-a681-413a-9738-cba31e1e1621
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936757375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1936757375
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2879895449
Short name T602
Test name
Test status
Simulation time 53735807104 ps
CPU time 5621.25 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 06:22:04 PM PDT 24
Peak memory 353468 kb
Host smart-aa053620-15d0-4239-a8d8-40c89d3c664a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879895449 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2879895449
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2148873922
Short name T608
Test name
Test status
Simulation time 29988647360 ps
CPU time 1335.35 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:10:36 PM PDT 24
Peak memory 289756 kb
Host smart-65b63ccc-7aad-4409-8969-f4551574b5e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148873922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2148873922
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2493409937
Short name T496
Test name
Test status
Simulation time 15310170890 ps
CPU time 233.76 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 04:52:19 PM PDT 24
Peak memory 257004 kb
Host smart-b9f6707d-f6fe-4b4f-8a81-8ad123595d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934
09937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2493409937
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1077209998
Short name T481
Test name
Test status
Simulation time 722775021 ps
CPU time 47.17 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 249072 kb
Host smart-147160f9-4277-4589-babb-8a713dafaa77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10772
09998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1077209998
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1059749855
Short name T618
Test name
Test status
Simulation time 9696248628 ps
CPU time 875.02 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:02:56 PM PDT 24
Peak memory 273064 kb
Host smart-17a46381-0adc-4c8f-9c8c-f888e5546d5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059749855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1059749855
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.764382938
Short name T2
Test name
Test status
Simulation time 59996726259 ps
CPU time 1296.6 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 05:10:03 PM PDT 24
Peak memory 290080 kb
Host smart-429566f7-8a12-487f-97f6-32490c3eb912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764382938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.764382938
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1723575194
Short name T308
Test name
Test status
Simulation time 183750365798 ps
CPU time 361.14 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:54:28 PM PDT 24
Peak memory 255576 kb
Host smart-fd5503b4-df4c-4e35-aae5-5b909d9f707c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723575194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1723575194
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2420390892
Short name T492
Test name
Test status
Simulation time 396265777 ps
CPU time 18.93 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:48:53 PM PDT 24
Peak memory 249080 kb
Host smart-7ffad457-2f26-42cc-ba10-cd742b0f4858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
90892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2420390892
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.996810620
Short name T49
Test name
Test status
Simulation time 5914643198 ps
CPU time 69.67 seconds
Started Jul 07 04:48:15 PM PDT 24
Finished Jul 07 04:49:25 PM PDT 24
Peak memory 248996 kb
Host smart-ded0c0c9-672f-4271-a94a-f5aec4d273f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99681
0620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.996810620
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1725185033
Short name T21
Test name
Test status
Simulation time 1741004839 ps
CPU time 40.15 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:49:15 PM PDT 24
Peak memory 257072 kb
Host smart-d8c6078c-d694-476c-8ae6-515ecb6db37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17251
85033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1725185033
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2146351314
Short name T447
Test name
Test status
Simulation time 743142672 ps
CPU time 19.06 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 257236 kb
Host smart-4ba64081-cd40-4f7c-9c25-4040ad69b767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21463
51314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2146351314
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3916411033
Short name T587
Test name
Test status
Simulation time 754293433 ps
CPU time 92.67 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:50:06 PM PDT 24
Peak memory 257296 kb
Host smart-f89f2580-ad86-4454-9059-8fbc81f147c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916411033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3916411033
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3409779231
Short name T82
Test name
Test status
Simulation time 36203804826 ps
CPU time 3567.7 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 05:47:52 PM PDT 24
Peak memory 338120 kb
Host smart-f96c9f6c-ddc2-4565-bb47-7061bed1fcd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409779231 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3409779231
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4022978670
Short name T105
Test name
Test status
Simulation time 97656375631 ps
CPU time 1598.57 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 05:15:03 PM PDT 24
Peak memory 273660 kb
Host smart-cb721d00-8a88-4f8d-962e-b7eaace60312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022978670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4022978670
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1339346831
Short name T54
Test name
Test status
Simulation time 2890149396 ps
CPU time 64.9 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 257428 kb
Host smart-0e37e593-0850-4c7c-a630-1b72cbb17af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13393
46831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1339346831
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1762259179
Short name T533
Test name
Test status
Simulation time 1816185428 ps
CPU time 34.82 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 04:49:03 PM PDT 24
Peak memory 248660 kb
Host smart-75662b70-1452-4b9e-ad59-9e6aa5e17d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17622
59179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1762259179
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1282942393
Short name T489
Test name
Test status
Simulation time 55333292859 ps
CPU time 1060.57 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 05:06:05 PM PDT 24
Peak memory 273796 kb
Host smart-7a91820a-a21f-48f8-93ee-df130314c967
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282942393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1282942393
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1112134891
Short name T474
Test name
Test status
Simulation time 5338231188 ps
CPU time 619.92 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 04:58:58 PM PDT 24
Peak memory 273528 kb
Host smart-53259f2d-07f0-405d-ae11-d88f37d06dc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112134891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1112134891
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3778170064
Short name T180
Test name
Test status
Simulation time 16086721262 ps
CPU time 656.21 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:59:20 PM PDT 24
Peak memory 249048 kb
Host smart-c3794b35-4c62-4e38-a462-ad85e117aaa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778170064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3778170064
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4206797837
Short name T479
Test name
Test status
Simulation time 998615880 ps
CPU time 21.33 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:48:46 PM PDT 24
Peak memory 256644 kb
Host smart-137fa4c0-bf85-4651-a394-157d6f106429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
97837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4206797837
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.886914445
Short name T265
Test name
Test status
Simulation time 486206609 ps
CPU time 25.78 seconds
Started Jul 07 04:48:21 PM PDT 24
Finished Jul 07 04:48:47 PM PDT 24
Peak memory 256276 kb
Host smart-ac20c94f-a849-44f1-a576-64b6c9d3579a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88691
4445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.886914445
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1550380611
Short name T253
Test name
Test status
Simulation time 167145890 ps
CPU time 21.49 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:48:40 PM PDT 24
Peak memory 256812 kb
Host smart-d3aabf1c-20de-4bad-aee7-b88a7354d961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15503
80611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1550380611
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.357241664
Short name T385
Test name
Test status
Simulation time 1598909279 ps
CPU time 20.45 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 255904 kb
Host smart-c03c8082-a67f-4641-8a33-36966e0f496f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35724
1664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.357241664
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1241617222
Short name T609
Test name
Test status
Simulation time 52441292333 ps
CPU time 1466.56 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 05:12:52 PM PDT 24
Peak memory 290216 kb
Host smart-d3fd1436-5b66-4f03-9421-988afcdca816
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241617222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1241617222
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.4105685216
Short name T98
Test name
Test status
Simulation time 103643149674 ps
CPU time 1985.05 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 282160 kb
Host smart-2cc367b5-a870-482a-b4a6-427df7f86931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105685216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.4105685216
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1927900868
Short name T512
Test name
Test status
Simulation time 7658175655 ps
CPU time 757.32 seconds
Started Jul 07 04:48:29 PM PDT 24
Finished Jul 07 05:01:07 PM PDT 24
Peak memory 265584 kb
Host smart-27b7333f-cf3b-4c81-9756-df1f97595922
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927900868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1927900868
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2445518475
Short name T213
Test name
Test status
Simulation time 4298684622 ps
CPU time 264.95 seconds
Started Jul 07 04:48:26 PM PDT 24
Finished Jul 07 04:52:52 PM PDT 24
Peak memory 257444 kb
Host smart-a254c40b-cc88-42da-b05e-eda5f156e1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
18475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2445518475
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1510028907
Short name T64
Test name
Test status
Simulation time 1134708479 ps
CPU time 30.05 seconds
Started Jul 07 04:48:30 PM PDT 24
Finished Jul 07 04:49:01 PM PDT 24
Peak memory 256776 kb
Host smart-8382e239-e5c8-4205-ba8b-2961f19abbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15100
28907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1510028907
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1611694381
Short name T339
Test name
Test status
Simulation time 12935874023 ps
CPU time 1228.02 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 05:08:52 PM PDT 24
Peak memory 273736 kb
Host smart-42050cee-6f75-4456-9801-96227b88e27c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611694381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1611694381
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3948480229
Short name T649
Test name
Test status
Simulation time 143821769850 ps
CPU time 2115.81 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 282912 kb
Host smart-e3503cec-dc9c-4e5f-801c-e6f5b77efaf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948480229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3948480229
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1461286668
Short name T289
Test name
Test status
Simulation time 11046800889 ps
CPU time 452.01 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:55:57 PM PDT 24
Peak memory 249076 kb
Host smart-07f65899-3455-4100-befe-d71fb4ad41e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461286668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1461286668
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.171012928
Short name T477
Test name
Test status
Simulation time 129982864 ps
CPU time 8.08 seconds
Started Jul 07 04:48:20 PM PDT 24
Finished Jul 07 04:48:29 PM PDT 24
Peak memory 249064 kb
Host smart-a336477f-453e-4af7-8eab-adbfcf4b92fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
2928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.171012928
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1421957662
Short name T511
Test name
Test status
Simulation time 48121225 ps
CPU time 7.78 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 04:48:33 PM PDT 24
Peak memory 240432 kb
Host smart-3d207d6b-60de-40f6-8d5c-26d7791ab60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
57662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1421957662
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.967777365
Short name T632
Test name
Test status
Simulation time 248345297 ps
CPU time 18.64 seconds
Started Jul 07 04:48:29 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 256584 kb
Host smart-b723e8c7-f240-410a-816b-199ec90793f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96777
7365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.967777365
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2723292871
Short name T53
Test name
Test status
Simulation time 65767676 ps
CPU time 7.27 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 04:48:33 PM PDT 24
Peak memory 249052 kb
Host smart-846196a0-b001-47c8-a79b-d55dfb199b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27232
92871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2723292871
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1851720623
Short name T631
Test name
Test status
Simulation time 12135799963 ps
CPU time 1032.89 seconds
Started Jul 07 04:48:31 PM PDT 24
Finished Jul 07 05:05:45 PM PDT 24
Peak memory 289560 kb
Host smart-32b7fa9f-4a3e-4851-8e4b-b5c371aefe0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851720623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1851720623
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2697377181
Short name T596
Test name
Test status
Simulation time 60753298875 ps
CPU time 809.28 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 05:02:06 PM PDT 24
Peak memory 272836 kb
Host smart-94a94bc2-63ba-4c33-878b-7753b3545b74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697377181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2697377181
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.133332831
Short name T55
Test name
Test status
Simulation time 17535906227 ps
CPU time 241.76 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:52:35 PM PDT 24
Peak memory 256976 kb
Host smart-364c240d-b5b1-4d76-be7f-80b15e41e9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
2831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.133332831
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1765047590
Short name T462
Test name
Test status
Simulation time 1272457770 ps
CPU time 13.33 seconds
Started Jul 07 04:48:31 PM PDT 24
Finished Jul 07 04:48:44 PM PDT 24
Peak memory 249124 kb
Host smart-d8c2876a-c187-40d6-9e5a-d6458f75f36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17650
47590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1765047590
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2402478635
Short name T352
Test name
Test status
Simulation time 92204808421 ps
CPU time 1308.58 seconds
Started Jul 07 04:48:25 PM PDT 24
Finished Jul 07 05:10:15 PM PDT 24
Peak memory 273764 kb
Host smart-c29229ae-f184-44e6-8ae9-5126928e167e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402478635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2402478635
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2940220279
Short name T637
Test name
Test status
Simulation time 10940967585 ps
CPU time 439.58 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:55:55 PM PDT 24
Peak memory 249664 kb
Host smart-5133e056-9ff4-4115-b6c7-47d61fefaf82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940220279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2940220279
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.936288848
Short name T528
Test name
Test status
Simulation time 351943331 ps
CPU time 8.4 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 249120 kb
Host smart-93383614-1e64-4ff7-b976-1a4585d387ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93628
8848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.936288848
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.965422920
Short name T85
Test name
Test status
Simulation time 271185933 ps
CPU time 16.49 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 255636 kb
Host smart-aa87c42a-8baf-4423-8a83-df6938595885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96542
2920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.965422920
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4001101509
Short name T450
Test name
Test status
Simulation time 2212016473 ps
CPU time 41.43 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 248480 kb
Host smart-50f1c406-6192-4431-92cf-677d6e4eb1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
01509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4001101509
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2987798450
Short name T629
Test name
Test status
Simulation time 1000214098 ps
CPU time 21.55 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 04:48:49 PM PDT 24
Peak memory 256496 kb
Host smart-9da5e982-b9ff-4f5a-b3f6-a2f2a9b8f09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29877
98450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2987798450
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3959026128
Short name T249
Test name
Test status
Simulation time 83668663263 ps
CPU time 2185.65 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 289044 kb
Host smart-9a5c960f-4522-4204-8def-ef2235da0c63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959026128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3959026128
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2727205390
Short name T81
Test name
Test status
Simulation time 129841987612 ps
CPU time 5137.79 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 06:14:03 PM PDT 24
Peak memory 322792 kb
Host smart-84054f35-004e-412b-a980-34a5258a2242
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727205390 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2727205390
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2161831008
Short name T112
Test name
Test status
Simulation time 52250045608 ps
CPU time 1187.05 seconds
Started Jul 07 04:48:29 PM PDT 24
Finished Jul 07 05:08:17 PM PDT 24
Peak memory 273516 kb
Host smart-f5bb3354-cd62-4055-bcca-b2efcc843c53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161831008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2161831008
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1632187781
Short name T443
Test name
Test status
Simulation time 16724397439 ps
CPU time 79.55 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:49:44 PM PDT 24
Peak memory 257440 kb
Host smart-ef07d497-fa37-4fd6-8a82-5569c9676af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16321
87781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1632187781
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1371834425
Short name T468
Test name
Test status
Simulation time 604195695 ps
CPU time 40.16 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 248692 kb
Host smart-f83be273-fa31-42ca-88c8-3ec9e63c0afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13718
34425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1371834425
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3876673874
Short name T271
Test name
Test status
Simulation time 12468595229 ps
CPU time 1045.21 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 05:05:50 PM PDT 24
Peak memory 284980 kb
Host smart-13bcecaf-3b98-4ad7-9e0f-62252411a0fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876673874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3876673874
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3827723661
Short name T551
Test name
Test status
Simulation time 96842111915 ps
CPU time 1408.81 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 05:11:55 PM PDT 24
Peak memory 273740 kb
Host smart-59a8a3cb-4d3b-4c63-8a88-663d15203dab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827723661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3827723661
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1490549055
Short name T290
Test name
Test status
Simulation time 8374178951 ps
CPU time 338.78 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:54:03 PM PDT 24
Peak memory 248140 kb
Host smart-20f4c75e-c70e-4a10-bfee-861623fce898
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490549055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1490549055
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.721214602
Short name T652
Test name
Test status
Simulation time 124208328 ps
CPU time 5.07 seconds
Started Jul 07 04:48:18 PM PDT 24
Finished Jul 07 04:48:24 PM PDT 24
Peak memory 240884 kb
Host smart-ea048f17-54c3-4f7e-bc9f-22a05480e305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72121
4602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.721214602
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1611646732
Short name T110
Test name
Test status
Simulation time 757444359 ps
CPU time 32.21 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 248332 kb
Host smart-9ae9c2dc-58dd-4ee5-af20-cf9be8208c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16116
46732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1611646732
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2114259962
Short name T465
Test name
Test status
Simulation time 997970388 ps
CPU time 38.81 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 256936 kb
Host smart-5ac957c7-df40-4b7f-b257-50bc65e6155e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21142
59962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2114259962
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.80940025
Short name T639
Test name
Test status
Simulation time 810817426 ps
CPU time 51.22 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 04:49:27 PM PDT 24
Peak memory 256988 kb
Host smart-2bde2688-5a07-41c8-a4bc-4c7feaaffe53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80940
025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.80940025
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2754492493
Short name T404
Test name
Test status
Simulation time 10495128848 ps
CPU time 857.69 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 05:02:47 PM PDT 24
Peak memory 283808 kb
Host smart-d1998616-1076-4362-908d-9884e57e36f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754492493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2754492493
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3313720075
Short name T104
Test name
Test status
Simulation time 50070958 ps
CPU time 2.73 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:47:37 PM PDT 24
Peak memory 249368 kb
Host smart-09637acb-a5c6-426f-afbe-4f1e5532555a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3313720075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3313720075
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.498295818
Short name T384
Test name
Test status
Simulation time 13129493964 ps
CPU time 1257.04 seconds
Started Jul 07 04:47:29 PM PDT 24
Finished Jul 07 05:08:27 PM PDT 24
Peak memory 287880 kb
Host smart-d50393f5-05b7-454b-a338-85d71b923641
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498295818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.498295818
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.447101025
Short name T494
Test name
Test status
Simulation time 2379905475 ps
CPU time 40.24 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:48:11 PM PDT 24
Peak memory 249244 kb
Host smart-bc873773-38c8-41e7-a592-cf64351eaffe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=447101025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.447101025
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.768252251
Short name T524
Test name
Test status
Simulation time 25576768822 ps
CPU time 127.5 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 250296 kb
Host smart-81cd91ee-66fe-4bd5-bc48-ba09f461e357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76825
2251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.768252251
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3353523966
Short name T469
Test name
Test status
Simulation time 194471736 ps
CPU time 4.72 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:47:36 PM PDT 24
Peak memory 249504 kb
Host smart-d1e99eb3-37ca-4a76-8e1b-d78f53f94d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33535
23966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3353523966
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1443821582
Short name T324
Test name
Test status
Simulation time 165148423086 ps
CPU time 1549.31 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 05:13:21 PM PDT 24
Peak memory 273064 kb
Host smart-77a37430-1d26-4360-98a9-11642117dcd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443821582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1443821582
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3146948009
Short name T99
Test name
Test status
Simulation time 6444822782 ps
CPU time 700.52 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 04:59:13 PM PDT 24
Peak memory 273812 kb
Host smart-d2b080c6-10f5-44c6-a061-47f1b6237d45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146948009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3146948009
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3746827776
Short name T184
Test name
Test status
Simulation time 43683042723 ps
CPU time 423.91 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 04:54:40 PM PDT 24
Peak memory 249224 kb
Host smart-31297a29-08c6-4fa4-88c8-78628cbcba7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746827776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3746827776
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3466111337
Short name T585
Test name
Test status
Simulation time 288581051 ps
CPU time 24.19 seconds
Started Jul 07 04:47:28 PM PDT 24
Finished Jul 07 04:47:53 PM PDT 24
Peak memory 256572 kb
Host smart-cfcb791b-4893-40e2-a21e-6edab8b4efc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34661
11337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3466111337
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2021635266
Short name T274
Test name
Test status
Simulation time 888476700 ps
CPU time 25.06 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:47:57 PM PDT 24
Peak memory 248660 kb
Host smart-13df7aeb-ce85-40f2-b14e-d93fb976ee98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20216
35266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2021635266
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2698452046
Short name T15
Test name
Test status
Simulation time 561696789 ps
CPU time 25.09 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 04:47:57 PM PDT 24
Peak memory 275028 kb
Host smart-9b8ea252-483f-444b-b053-30429920c671
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2698452046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2698452046
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2317903132
Short name T97
Test name
Test status
Simulation time 310316425 ps
CPU time 31.16 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:48:05 PM PDT 24
Peak memory 256836 kb
Host smart-882f0c6e-2194-4b71-994b-ff46951a0d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23179
03132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2317903132
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1102492501
Short name T696
Test name
Test status
Simulation time 1058148696 ps
CPU time 23.56 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 04:47:56 PM PDT 24
Peak memory 257388 kb
Host smart-abaaa6ca-50d4-4c3a-b2a9-9a206aa280b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11024
92501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1102492501
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1978704719
Short name T62
Test name
Test status
Simulation time 74441347512 ps
CPU time 2199.58 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 284072 kb
Host smart-12e71a6a-f9d0-417a-9d58-b7069a4df1db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978704719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1978704719
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4015128094
Short name T109
Test name
Test status
Simulation time 199792736860 ps
CPU time 1699.9 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 05:15:53 PM PDT 24
Peak memory 290324 kb
Host smart-a47f7590-66de-4fed-b2de-9332266c7a58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015128094 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4015128094
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2093027706
Short name T181
Test name
Test status
Simulation time 42715103414 ps
CPU time 2477.7 seconds
Started Jul 07 04:48:40 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 284796 kb
Host smart-12a35128-438b-4a8a-b87d-3ba8bb4d6d66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093027706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2093027706
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2651568025
Short name T647
Test name
Test status
Simulation time 3744619843 ps
CPU time 82.11 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:49:56 PM PDT 24
Peak memory 256560 kb
Host smart-d2c71ad7-de06-42b4-a4bf-2c5c26948ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26515
68025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2651568025
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2904605877
Short name T67
Test name
Test status
Simulation time 163978471 ps
CPU time 4.59 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:48:40 PM PDT 24
Peak memory 249176 kb
Host smart-09842391-e449-458a-b401-623912f5433c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29046
05877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2904605877
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4143023500
Short name T300
Test name
Test status
Simulation time 40399673885 ps
CPU time 2226.46 seconds
Started Jul 07 04:48:22 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 282040 kb
Host smart-2379e1c3-ca89-47e7-8895-c1bc71b81f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143023500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4143023500
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3235522745
Short name T356
Test name
Test status
Simulation time 183060653828 ps
CPU time 2654.4 seconds
Started Jul 07 04:48:27 PM PDT 24
Finished Jul 07 05:32:42 PM PDT 24
Peak memory 289928 kb
Host smart-9083517a-af00-4754-9674-4bb26db29d8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235522745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3235522745
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1118228753
Short name T641
Test name
Test status
Simulation time 13809224486 ps
CPU time 539.46 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 04:57:36 PM PDT 24
Peak memory 255624 kb
Host smart-752e0a5e-da94-466a-9935-6310d1fc0046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118228753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1118228753
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.701272838
Short name T36
Test name
Test status
Simulation time 3664583537 ps
CPU time 64.1 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:49:38 PM PDT 24
Peak memory 257104 kb
Host smart-5b3729a4-8f9c-4ae5-9691-c7b6670d0bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70127
2838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.701272838
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3400077493
Short name T409
Test name
Test status
Simulation time 2191058950 ps
CPU time 7.59 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:48:43 PM PDT 24
Peak memory 251928 kb
Host smart-74fa5c9f-432a-4f42-ac6e-580dc7d797ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34000
77493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3400077493
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1937542273
Short name T254
Test name
Test status
Simulation time 3883446324 ps
CPU time 64.58 seconds
Started Jul 07 04:48:39 PM PDT 24
Finished Jul 07 04:49:43 PM PDT 24
Peak memory 256776 kb
Host smart-7b576d50-29b9-4a6b-a21b-a90f28298eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19375
42273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1937542273
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3962433204
Short name T522
Test name
Test status
Simulation time 944969464 ps
CPU time 19.07 seconds
Started Jul 07 04:48:24 PM PDT 24
Finished Jul 07 04:48:44 PM PDT 24
Peak memory 257248 kb
Host smart-362f6fe6-936d-4e88-8ec1-75d598160ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39624
33204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3962433204
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1803217484
Short name T671
Test name
Test status
Simulation time 147533300614 ps
CPU time 2034.3 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 290268 kb
Host smart-76eee890-f4ef-48f3-97a7-f52d88d375f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803217484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1803217484
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.334266372
Short name T175
Test name
Test status
Simulation time 350703498096 ps
CPU time 1228.85 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 283292 kb
Host smart-321e7879-dd0f-44a3-bcbf-2d22702ddeaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334266372 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.334266372
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3894895477
Short name T9
Test name
Test status
Simulation time 182549317900 ps
CPU time 2692.49 seconds
Started Jul 07 04:48:26 PM PDT 24
Finished Jul 07 05:33:20 PM PDT 24
Peak memory 286688 kb
Host smart-0894db43-7f12-4148-ada2-b1303474065e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894895477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3894895477
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2841705972
Short name T471
Test name
Test status
Simulation time 913764659 ps
CPU time 98.25 seconds
Started Jul 07 04:48:29 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 257252 kb
Host smart-c5b4d771-9716-4363-a2a0-bba2bcf21e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28417
05972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2841705972
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1201788075
Short name T365
Test name
Test status
Simulation time 360788804 ps
CPU time 22.22 seconds
Started Jul 07 04:48:37 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 249080 kb
Host smart-cb96dd88-1d7d-4dbb-9d8f-d1265f7d81d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017
88075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1201788075
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2918432416
Short name T560
Test name
Test status
Simulation time 66165628807 ps
CPU time 1126.21 seconds
Started Jul 07 04:48:39 PM PDT 24
Finished Jul 07 05:07:25 PM PDT 24
Peak memory 273744 kb
Host smart-06180241-fec8-4d7a-8990-9305c85d65e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918432416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2918432416
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.4206103156
Short name T224
Test name
Test status
Simulation time 60358952076 ps
CPU time 1822.04 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 05:18:55 PM PDT 24
Peak memory 268740 kb
Host smart-f065fcac-5596-4ef8-867d-a9ea656ee8e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206103156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.4206103156
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.345135589
Short name T539
Test name
Test status
Simulation time 196621493 ps
CPU time 16.29 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 256516 kb
Host smart-ad830a89-d377-4dfd-828b-7783e8271787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34513
5589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.345135589
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1578741959
Short name T353
Test name
Test status
Simulation time 116708724 ps
CPU time 4.69 seconds
Started Jul 07 04:48:23 PM PDT 24
Finished Jul 07 04:48:29 PM PDT 24
Peak memory 240480 kb
Host smart-331592b8-7f7b-4eee-92aa-b79c4ba96de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
41959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1578741959
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1707488669
Short name T418
Test name
Test status
Simulation time 108692592 ps
CPU time 4.96 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 240472 kb
Host smart-66b3cb4d-c124-4aaa-97d0-62c8ffe1b635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074
88669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1707488669
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3337293830
Short name T440
Test name
Test status
Simulation time 88005474 ps
CPU time 9.72 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:48:45 PM PDT 24
Peak memory 255464 kb
Host smart-adcf2fee-b629-4d15-a378-e4fa7e3bc971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33372
93830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3337293830
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1493375556
Short name T176
Test name
Test status
Simulation time 82551475282 ps
CPU time 7109.59 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 06:47:02 PM PDT 24
Peak memory 364004 kb
Host smart-2a2e04dc-520c-4e1e-81b5-12d7c5014032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493375556 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1493375556
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.184554645
Short name T517
Test name
Test status
Simulation time 414099155374 ps
CPU time 3178.53 seconds
Started Jul 07 04:48:37 PM PDT 24
Finished Jul 07 05:41:37 PM PDT 24
Peak memory 289744 kb
Host smart-20e1f93b-0a38-4915-88ce-9354f9abd3dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184554645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.184554645
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.113350688
Short name T415
Test name
Test status
Simulation time 30869232656 ps
CPU time 199.94 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:51:55 PM PDT 24
Peak memory 257456 kb
Host smart-9ead5bfe-24c7-41b5-a5a3-5c75abbb8d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
0688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.113350688
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3027090342
Short name T453
Test name
Test status
Simulation time 82341163 ps
CPU time 7.81 seconds
Started Jul 07 04:48:41 PM PDT 24
Finished Jul 07 04:48:49 PM PDT 24
Peak memory 251636 kb
Host smart-598e05d3-db4d-4309-a9db-c0db46f2253e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30270
90342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3027090342
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2631702771
Short name T341
Test name
Test status
Simulation time 16130899132 ps
CPU time 1409.82 seconds
Started Jul 07 04:48:37 PM PDT 24
Finished Jul 07 05:12:08 PM PDT 24
Peak memory 290120 kb
Host smart-726300df-1804-4a54-bc84-ff7db046336c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631702771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2631702771
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4157769076
Short name T401
Test name
Test status
Simulation time 79319853178 ps
CPU time 2286.61 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 283980 kb
Host smart-1a365672-caad-42de-ae3e-569958b97cee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157769076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4157769076
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4007862723
Short name T310
Test name
Test status
Simulation time 83130691011 ps
CPU time 420.94 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:55:36 PM PDT 24
Peak memory 249200 kb
Host smart-8dbac7bc-9aad-4b79-b744-f929f86dc948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007862723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4007862723
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4150167644
Short name T413
Test name
Test status
Simulation time 2019300403 ps
CPU time 34.13 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 249120 kb
Host smart-b99e6d3e-2b76-42c5-bb80-fac3df3c0ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41501
67644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4150167644
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4184707345
Short name T673
Test name
Test status
Simulation time 411097756 ps
CPU time 20.48 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 04:48:54 PM PDT 24
Peak memory 248848 kb
Host smart-f7b96428-58a5-4b93-bd33-ea86922db280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
07345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4184707345
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2981888443
Short name T248
Test name
Test status
Simulation time 440819479 ps
CPU time 18.6 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 248624 kb
Host smart-34b5f1e5-6660-4767-be52-67db14ee97e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29818
88443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2981888443
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2824922505
Short name T513
Test name
Test status
Simulation time 5440956379 ps
CPU time 51.72 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:49:24 PM PDT 24
Peak memory 256776 kb
Host smart-e95b250c-f181-4526-b142-b87eb5f9c5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
22505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2824922505
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4183362117
Short name T705
Test name
Test status
Simulation time 21227287276 ps
CPU time 1234.01 seconds
Started Jul 07 04:48:28 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 273384 kb
Host smart-4b00c27c-c402-4770-b8a8-ae1ed3723f53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183362117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4183362117
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1326373040
Short name T258
Test name
Test status
Simulation time 135420378689 ps
CPU time 8052.73 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 07:02:50 PM PDT 24
Peak memory 339260 kb
Host smart-3011a3b4-2c7c-4e06-a568-9978a5482bca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326373040 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1326373040
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2505728554
Short name T369
Test name
Test status
Simulation time 153398945449 ps
CPU time 1887.02 seconds
Started Jul 07 04:48:33 PM PDT 24
Finished Jul 07 05:20:01 PM PDT 24
Peak memory 287144 kb
Host smart-b0a2ba58-2bf5-4afe-abcc-15040717972a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505728554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2505728554
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1008611935
Short name T606
Test name
Test status
Simulation time 463395104 ps
CPU time 32.94 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 256552 kb
Host smart-d7371c08-41ae-454a-8d8c-495d9fbd8fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
11935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1008611935
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.356316863
Short name T257
Test name
Test status
Simulation time 18835118631 ps
CPU time 55.32 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 04:49:33 PM PDT 24
Peak memory 256188 kb
Host smart-46056f09-918e-4256-93d0-b8af1d4beab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35631
6863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.356316863
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.4195811825
Short name T329
Test name
Test status
Simulation time 72645704637 ps
CPU time 1675.4 seconds
Started Jul 07 04:48:41 PM PDT 24
Finished Jul 07 05:16:37 PM PDT 24
Peak memory 273208 kb
Host smart-b0d108fd-6472-4c8b-90ba-dad9cc1c61ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195811825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.4195811825
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4040056031
Short name T402
Test name
Test status
Simulation time 51822951962 ps
CPU time 1318.57 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 05:10:34 PM PDT 24
Peak memory 283060 kb
Host smart-895b7510-4fec-4955-8509-6dc05cc67a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040056031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4040056031
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1775069045
Short name T688
Test name
Test status
Simulation time 9055847678 ps
CPU time 341.96 seconds
Started Jul 07 04:48:42 PM PDT 24
Finished Jul 07 04:54:24 PM PDT 24
Peak memory 248104 kb
Host smart-666148e8-7e28-479c-ba31-ab624399187d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775069045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1775069045
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.279235395
Short name T429
Test name
Test status
Simulation time 3392599687 ps
CPU time 59.76 seconds
Started Jul 07 04:48:34 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 256564 kb
Host smart-0bbe776f-105c-4ccb-9b7f-e127745f6f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
5395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.279235395
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1861858893
Short name T102
Test name
Test status
Simulation time 4226859050 ps
CPU time 52.65 seconds
Started Jul 07 04:48:41 PM PDT 24
Finished Jul 07 04:49:34 PM PDT 24
Peak memory 256528 kb
Host smart-c9e9194b-dde1-4421-8397-554d92ede85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18618
58893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1861858893
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1138527479
Short name T536
Test name
Test status
Simulation time 1159017210 ps
CPU time 32.32 seconds
Started Jul 07 04:48:37 PM PDT 24
Finished Jul 07 04:49:10 PM PDT 24
Peak memory 256716 kb
Host smart-e21ca0f2-cc4d-42ad-a7c1-ad7c622e3990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
27479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1138527479
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.337613918
Short name T58
Test name
Test status
Simulation time 1088220171 ps
CPU time 33.65 seconds
Started Jul 07 04:48:31 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 257256 kb
Host smart-0db3d9c5-bde7-4403-99db-ba3f3bf10caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33761
3918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.337613918
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2802302657
Short name T47
Test name
Test status
Simulation time 26597222839 ps
CPU time 1189.93 seconds
Started Jul 07 04:48:36 PM PDT 24
Finished Jul 07 05:08:27 PM PDT 24
Peak memory 290008 kb
Host smart-cb334230-f84f-4234-b514-ebbe5d0aee88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802302657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2802302657
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.4014256468
Short name T35
Test name
Test status
Simulation time 1515675899 ps
CPU time 125.79 seconds
Started Jul 07 04:48:39 PM PDT 24
Finished Jul 07 04:50:46 PM PDT 24
Peak memory 257344 kb
Host smart-8f3404f5-3f0b-43fb-afd9-7adbc2b8528d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40142
56468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4014256468
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3359470420
Short name T678
Test name
Test status
Simulation time 1037342068 ps
CPU time 8.56 seconds
Started Jul 07 04:48:40 PM PDT 24
Finished Jul 07 04:48:49 PM PDT 24
Peak memory 248368 kb
Host smart-b3646a77-2ff4-4003-9794-ec8f5ea3a176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33594
70420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3359470420
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1327316514
Short name T605
Test name
Test status
Simulation time 82338969158 ps
CPU time 2194.17 seconds
Started Jul 07 04:48:38 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 273220 kb
Host smart-feabfd26-ab80-40ab-ba13-bf4d4435e78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327316514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1327316514
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1994819381
Short name T567
Test name
Test status
Simulation time 13754826611 ps
CPU time 1170.18 seconds
Started Jul 07 04:48:42 PM PDT 24
Finished Jul 07 05:08:13 PM PDT 24
Peak memory 285244 kb
Host smart-d9bde83a-6a5f-44f6-97f8-2b2d17518a10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994819381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1994819381
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.688301164
Short name T659
Test name
Test status
Simulation time 10927483921 ps
CPU time 111.12 seconds
Started Jul 07 04:48:43 PM PDT 24
Finished Jul 07 04:50:34 PM PDT 24
Peak memory 255176 kb
Host smart-10fedd09-6c72-4ff2-8fbb-de65472c0dba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688301164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.688301164
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1806508501
Short name T437
Test name
Test status
Simulation time 997666642 ps
CPU time 15.44 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:48:48 PM PDT 24
Peak memory 249160 kb
Host smart-503fd938-7457-4147-9215-807c55c954bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18065
08501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1806508501
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3321015837
Short name T66
Test name
Test status
Simulation time 443608979 ps
CPU time 39.3 seconds
Started Jul 07 04:48:32 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 256444 kb
Host smart-d00237da-935d-49f8-8459-f08d1363fccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
15837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3321015837
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.470972080
Short name T240
Test name
Test status
Simulation time 3951161868 ps
CPU time 48.74 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 249180 kb
Host smart-13e4e5db-d9b6-4ef2-8d32-2f1924c6c52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47097
2080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.470972080
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2474461474
Short name T499
Test name
Test status
Simulation time 291372447 ps
CPU time 14.15 seconds
Started Jul 07 04:48:38 PM PDT 24
Finished Jul 07 04:48:53 PM PDT 24
Peak memory 256652 kb
Host smart-900ac817-b77e-4ad1-afdd-3cdf6e2de437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24744
61474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2474461474
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2728453569
Short name T621
Test name
Test status
Simulation time 8168358631 ps
CPU time 334.25 seconds
Started Jul 07 04:48:35 PM PDT 24
Finished Jul 07 04:54:11 PM PDT 24
Peak memory 257288 kb
Host smart-ac5a3223-8f5b-4547-8912-4fa38e8447b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728453569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2728453569
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3940081177
Short name T94
Test name
Test status
Simulation time 369979848048 ps
CPU time 1777.16 seconds
Started Jul 07 04:48:47 PM PDT 24
Finished Jul 07 05:18:24 PM PDT 24
Peak memory 267740 kb
Host smart-63bb8355-f6c7-41a7-a949-2673bb26ea22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940081177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3940081177
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4024244307
Short name T270
Test name
Test status
Simulation time 420104083 ps
CPU time 40.52 seconds
Started Jul 07 04:48:54 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 256788 kb
Host smart-4d675592-5524-4f38-83e4-938ec860159d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40242
44307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4024244307
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.342299817
Short name T675
Test name
Test status
Simulation time 1623396697 ps
CPU time 47.63 seconds
Started Jul 07 04:48:41 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 249720 kb
Host smart-f4830b0c-7478-4d82-9b73-d387926c72b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34229
9817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.342299817
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3258177590
Short name T535
Test name
Test status
Simulation time 41025331685 ps
CPU time 1488.22 seconds
Started Jul 07 04:48:47 PM PDT 24
Finished Jul 07 05:13:35 PM PDT 24
Peak memory 289576 kb
Host smart-30b67ed8-93e2-4f7e-863a-2555cc910e1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258177590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3258177590
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2375103839
Short name T307
Test name
Test status
Simulation time 17629172122 ps
CPU time 204.46 seconds
Started Jul 07 04:48:42 PM PDT 24
Finished Jul 07 04:52:07 PM PDT 24
Peak memory 248396 kb
Host smart-6fc81b68-72d4-4bac-ab95-4e00ab5f37cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375103839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2375103839
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1926302838
Short name T34
Test name
Test status
Simulation time 2369014696 ps
CPU time 55.61 seconds
Started Jul 07 04:48:42 PM PDT 24
Finished Jul 07 04:49:38 PM PDT 24
Peak memory 256544 kb
Host smart-59bb1f31-def0-4a86-bfbe-9f9988d8c242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263
02838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1926302838
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3259879150
Short name T636
Test name
Test status
Simulation time 2013676499 ps
CPU time 32.67 seconds
Started Jul 07 04:48:37 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 248748 kb
Host smart-40c7285f-14bc-4f7c-93e1-f51c0486bfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32598
79150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3259879150
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1434584089
Short name T382
Test name
Test status
Simulation time 948093011 ps
CPU time 39.37 seconds
Started Jul 07 04:48:47 PM PDT 24
Finished Jul 07 04:49:27 PM PDT 24
Peak memory 257180 kb
Host smart-0a0981c8-f0aa-409e-908d-436c1b571e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
84089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1434584089
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1520299616
Short name T411
Test name
Test status
Simulation time 272914737 ps
CPU time 18.38 seconds
Started Jul 07 04:48:41 PM PDT 24
Finished Jul 07 04:49:01 PM PDT 24
Peak memory 255008 kb
Host smart-4805a4bd-ab31-4351-b02b-b69be872b076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15202
99616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1520299616
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3085512097
Short name T523
Test name
Test status
Simulation time 14315945668 ps
CPU time 480.55 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:56:49 PM PDT 24
Peak memory 265660 kb
Host smart-9b3d3125-abd5-4dc4-a5bd-4b0cecbbdd33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085512097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3085512097
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1458445675
Short name T449
Test name
Test status
Simulation time 77258912295 ps
CPU time 1287.57 seconds
Started Jul 07 04:48:44 PM PDT 24
Finished Jul 07 05:10:12 PM PDT 24
Peak memory 273312 kb
Host smart-3d20b111-5dfe-4fd2-8db1-808d644d208c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458445675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1458445675
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.756823758
Short name T354
Test name
Test status
Simulation time 6426146029 ps
CPU time 88.92 seconds
Started Jul 07 04:48:44 PM PDT 24
Finished Jul 07 04:50:13 PM PDT 24
Peak memory 257464 kb
Host smart-4a810296-f0f6-41d1-b948-706d11fc99ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75682
3758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.756823758
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2365141437
Short name T656
Test name
Test status
Simulation time 1235354745 ps
CPU time 22.35 seconds
Started Jul 07 04:48:42 PM PDT 24
Finished Jul 07 04:49:05 PM PDT 24
Peak memory 256412 kb
Host smart-5dd09787-70f6-4322-bfac-5c868053dc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23651
41437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2365141437
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2015538790
Short name T645
Test name
Test status
Simulation time 59490618347 ps
CPU time 1090.09 seconds
Started Jul 07 04:48:43 PM PDT 24
Finished Jul 07 05:06:54 PM PDT 24
Peak memory 281976 kb
Host smart-f9a131fc-54c0-4040-94d8-a32c7e31a002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015538790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2015538790
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1098640882
Short name T223
Test name
Test status
Simulation time 43252974950 ps
CPU time 1010.91 seconds
Started Jul 07 04:48:47 PM PDT 24
Finished Jul 07 05:05:39 PM PDT 24
Peak memory 287176 kb
Host smart-d621f327-6e0e-48d9-a788-0ef2494406c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098640882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1098640882
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3963418381
Short name T312
Test name
Test status
Simulation time 6520259518 ps
CPU time 271.49 seconds
Started Jul 07 04:48:44 PM PDT 24
Finished Jul 07 04:53:15 PM PDT 24
Peak memory 249272 kb
Host smart-8cc9cf73-0f88-4315-8f5b-de1ab453dcc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963418381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3963418381
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4201845650
Short name T444
Test name
Test status
Simulation time 2748735452 ps
CPU time 71.94 seconds
Started Jul 07 04:48:40 PM PDT 24
Finished Jul 07 04:49:52 PM PDT 24
Peak memory 257052 kb
Host smart-83143f9f-1a79-4b83-9826-dda59ff5b6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42018
45650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4201845650
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.759330983
Short name T646
Test name
Test status
Simulation time 169952562 ps
CPU time 22.68 seconds
Started Jul 07 04:48:42 PM PDT 24
Finished Jul 07 04:49:05 PM PDT 24
Peak memory 249152 kb
Host smart-475a93fc-d1b3-4a8e-abb7-cac351210bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75933
0983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.759330983
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2529617508
Short name T233
Test name
Test status
Simulation time 45794503 ps
CPU time 6.34 seconds
Started Jul 07 04:48:45 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 248292 kb
Host smart-58fd0ab7-b2f3-4db2-9cbf-728a7d5e0942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
17508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2529617508
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1671318388
Short name T666
Test name
Test status
Simulation time 242478941 ps
CPU time 10.1 seconds
Started Jul 07 04:48:41 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 257208 kb
Host smart-5af2979c-4523-4519-9f1e-a27289e711b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
18388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1671318388
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4015961621
Short name T486
Test name
Test status
Simulation time 11143029589 ps
CPU time 968.45 seconds
Started Jul 07 04:48:49 PM PDT 24
Finished Jul 07 05:04:58 PM PDT 24
Peak memory 289352 kb
Host smart-628f30f3-2e90-41d4-8f21-88526065a62e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015961621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4015961621
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3166715366
Short name T588
Test name
Test status
Simulation time 44350901190 ps
CPU time 1111.59 seconds
Started Jul 07 04:48:51 PM PDT 24
Finished Jul 07 05:07:23 PM PDT 24
Peak memory 289552 kb
Host smart-c381d841-73a8-46fe-82b7-f4ef4d7a198b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166715366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3166715366
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1938226378
Short name T368
Test name
Test status
Simulation time 3239186075 ps
CPU time 71.35 seconds
Started Jul 07 04:48:44 PM PDT 24
Finished Jul 07 04:49:56 PM PDT 24
Peak memory 257368 kb
Host smart-7e8cf905-b473-448a-bc85-09b276509a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
26378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1938226378
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4172094497
Short name T355
Test name
Test status
Simulation time 98970420 ps
CPU time 4.98 seconds
Started Jul 07 04:48:45 PM PDT 24
Finished Jul 07 04:48:50 PM PDT 24
Peak memory 248688 kb
Host smart-a23b1398-bf79-4fa6-b883-0df3235c9200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
94497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4172094497
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2635155868
Short name T182
Test name
Test status
Simulation time 57335161358 ps
CPU time 3308.1 seconds
Started Jul 07 04:48:47 PM PDT 24
Finished Jul 07 05:43:56 PM PDT 24
Peak memory 290068 kb
Host smart-28a0abb5-436e-402e-bd03-b86fcc1b39f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635155868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2635155868
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2779432867
Short name T635
Test name
Test status
Simulation time 28777138379 ps
CPU time 1235.74 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 282048 kb
Host smart-37e42391-06d7-43e3-97ae-ce99b628b227
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779432867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2779432867
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2346385914
Short name T306
Test name
Test status
Simulation time 1950906992 ps
CPU time 77.83 seconds
Started Jul 07 04:48:50 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 254460 kb
Host smart-d7284b52-5830-4836-9244-9c6a1505ef7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346385914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2346385914
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2131761232
Short name T425
Test name
Test status
Simulation time 381019594 ps
CPU time 33.76 seconds
Started Jul 07 04:48:46 PM PDT 24
Finished Jul 07 04:49:20 PM PDT 24
Peak memory 249164 kb
Host smart-3179c206-4f00-4192-a632-13fcd4f2178d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21317
61232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2131761232
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3689468553
Short name T495
Test name
Test status
Simulation time 470957430 ps
CPU time 5.25 seconds
Started Jul 07 04:48:47 PM PDT 24
Finished Jul 07 04:48:52 PM PDT 24
Peak memory 240492 kb
Host smart-e4110d68-0030-4e31-b872-e778b22459a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
68553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3689468553
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.170515639
Short name T634
Test name
Test status
Simulation time 108051474 ps
CPU time 5.52 seconds
Started Jul 07 04:48:45 PM PDT 24
Finished Jul 07 04:48:51 PM PDT 24
Peak memory 251272 kb
Host smart-5ea2b4b4-3292-4047-9784-73fb5b0783cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17051
5639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.170515639
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.541791630
Short name T377
Test name
Test status
Simulation time 278689430 ps
CPU time 14.86 seconds
Started Jul 07 04:48:45 PM PDT 24
Finished Jul 07 04:49:01 PM PDT 24
Peak memory 249148 kb
Host smart-556fb53f-0ca6-450e-bc19-6cdf84309bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54179
1630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.541791630
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.686946173
Short name T422
Test name
Test status
Simulation time 366959095208 ps
CPU time 2624.42 seconds
Started Jul 07 04:48:50 PM PDT 24
Finished Jul 07 05:32:35 PM PDT 24
Peak memory 284144 kb
Host smart-78852ee1-9253-4772-ad08-16427181c05d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686946173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.686946173
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2814792126
Short name T4
Test name
Test status
Simulation time 56642850544 ps
CPU time 1291.72 seconds
Started Jul 07 04:48:49 PM PDT 24
Finished Jul 07 05:10:21 PM PDT 24
Peak memory 282032 kb
Host smart-da809be7-3473-4672-bf3e-2f906b9b678f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814792126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2814792126
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1964345510
Short name T704
Test name
Test status
Simulation time 500989599 ps
CPU time 53.99 seconds
Started Jul 07 04:48:49 PM PDT 24
Finished Jul 07 04:49:44 PM PDT 24
Peak memory 256624 kb
Host smart-af23690b-c58c-45b1-836b-96218e766a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643
45510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1964345510
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1589889251
Short name T684
Test name
Test status
Simulation time 225702288 ps
CPU time 8.53 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:48:57 PM PDT 24
Peak memory 257272 kb
Host smart-72fc4ff1-56f4-499d-9f3d-0fe4c2411a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15898
89251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1589889251
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2984903800
Short name T263
Test name
Test status
Simulation time 45777530014 ps
CPU time 1272.67 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 05:10:01 PM PDT 24
Peak memory 285520 kb
Host smart-dd363e31-014e-47f7-8f95-dc77b7cd9fc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984903800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2984903800
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.238034082
Short name T267
Test name
Test status
Simulation time 118139941569 ps
CPU time 2067.68 seconds
Started Jul 07 04:48:51 PM PDT 24
Finished Jul 07 05:23:19 PM PDT 24
Peak memory 282708 kb
Host smart-1327ce81-08e4-4a6e-b8b2-557f6cb9dd82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238034082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.238034082
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1691411172
Short name T45
Test name
Test status
Simulation time 562831512 ps
CPU time 10.71 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:48:59 PM PDT 24
Peak memory 256552 kb
Host smart-417e141a-d6c6-4aea-a79f-b564d9ebef53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
11172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1691411172
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2085996314
Short name T426
Test name
Test status
Simulation time 601847584 ps
CPU time 15.71 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:49:04 PM PDT 24
Peak memory 256712 kb
Host smart-be5d56d2-c0fc-487c-af28-7aeeaf3a6ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20859
96314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2085996314
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2721568596
Short name T399
Test name
Test status
Simulation time 1563621676 ps
CPU time 37.01 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:49:26 PM PDT 24
Peak memory 257232 kb
Host smart-0f7767ff-6ffc-42b5-bbaa-fe0707acaa52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27215
68596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2721568596
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.443379739
Short name T572
Test name
Test status
Simulation time 6662544298 ps
CPU time 66.85 seconds
Started Jul 07 04:48:48 PM PDT 24
Finished Jul 07 04:49:55 PM PDT 24
Peak memory 249504 kb
Host smart-e655d54b-72a4-4816-808f-4d9b915f001b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44337
9739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.443379739
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1525206206
Short name T601
Test name
Test status
Simulation time 10674084544 ps
CPU time 1384.82 seconds
Started Jul 07 04:48:55 PM PDT 24
Finished Jul 07 05:12:00 PM PDT 24
Peak memory 289624 kb
Host smart-856d0e6e-a7a4-4b7a-936d-efd5bc57389d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525206206 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1525206206
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.407436737
Short name T615
Test name
Test status
Simulation time 38269547307 ps
CPU time 2321.62 seconds
Started Jul 07 04:48:53 PM PDT 24
Finished Jul 07 05:27:35 PM PDT 24
Peak memory 283428 kb
Host smart-8e19a490-f847-4498-80e9-5afa7f7f7fd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407436737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.407436737
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1940604751
Short name T287
Test name
Test status
Simulation time 6234062294 ps
CPU time 80.7 seconds
Started Jul 07 04:48:54 PM PDT 24
Finished Jul 07 04:50:15 PM PDT 24
Peak memory 256992 kb
Host smart-0b2e1895-2eae-4871-92ed-14017058e45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19406
04751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1940604751
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4057613772
Short name T660
Test name
Test status
Simulation time 1396067620 ps
CPU time 20.54 seconds
Started Jul 07 04:48:52 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 256368 kb
Host smart-11b1bdea-b4d7-4846-b07f-5dec5f4710f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40576
13772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4057613772
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.656091650
Short name T327
Test name
Test status
Simulation time 128708388077 ps
CPU time 1885.99 seconds
Started Jul 07 04:48:52 PM PDT 24
Finished Jul 07 05:20:19 PM PDT 24
Peak memory 273880 kb
Host smart-c99e9067-1b73-4eaf-a50e-23af617f32e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656091650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.656091650
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.198391691
Short name T61
Test name
Test status
Simulation time 104999588725 ps
CPU time 2899.32 seconds
Started Jul 07 04:48:58 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 290024 kb
Host smart-d5976c14-94a0-4793-8ab2-db1af383e027
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198391691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.198391691
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1091582503
Short name T293
Test name
Test status
Simulation time 5101643967 ps
CPU time 215.12 seconds
Started Jul 07 04:48:54 PM PDT 24
Finished Jul 07 04:52:29 PM PDT 24
Peak memory 248400 kb
Host smart-303699fe-82da-4a20-9784-30567f772e94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091582503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1091582503
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.44561854
Short name T571
Test name
Test status
Simulation time 139234336 ps
CPU time 14.58 seconds
Started Jul 07 04:48:53 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 249076 kb
Host smart-3a5ad33f-3a68-48bb-9053-00d124805165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44561
854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.44561854
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3479335510
Short name T6
Test name
Test status
Simulation time 127279628 ps
CPU time 5.61 seconds
Started Jul 07 04:48:51 PM PDT 24
Finished Jul 07 04:48:57 PM PDT 24
Peak memory 240232 kb
Host smart-80278712-5cc5-45cb-aef2-9c47ff98a55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
35510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3479335510
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2070505131
Short name T493
Test name
Test status
Simulation time 8555307056 ps
CPU time 36.92 seconds
Started Jul 07 04:48:54 PM PDT 24
Finished Jul 07 04:49:31 PM PDT 24
Peak memory 257304 kb
Host smart-f7a60d41-8b1c-4342-84a5-32c3bb3ae6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20705
05131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2070505131
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3337575816
Short name T70
Test name
Test status
Simulation time 17069202653 ps
CPU time 417.53 seconds
Started Jul 07 04:49:02 PM PDT 24
Finished Jul 07 04:56:00 PM PDT 24
Peak memory 257424 kb
Host smart-bf625692-1e1c-47b3-8151-8d47739d67c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337575816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3337575816
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.718046202
Short name T681
Test name
Test status
Simulation time 148355872615 ps
CPU time 4032.35 seconds
Started Jul 07 04:48:59 PM PDT 24
Finished Jul 07 05:56:12 PM PDT 24
Peak memory 323144 kb
Host smart-f73c7773-1763-4498-be7a-7febf45c3e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718046202 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.718046202
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1905685861
Short name T204
Test name
Test status
Simulation time 19049337 ps
CPU time 2.92 seconds
Started Jul 07 04:47:34 PM PDT 24
Finished Jul 07 04:47:37 PM PDT 24
Peak memory 249408 kb
Host smart-8fa2cba9-fd77-42ca-b049-dc09778931bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1905685861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1905685861
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3648191676
Short name T626
Test name
Test status
Simulation time 2406691156 ps
CPU time 30.32 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:48:02 PM PDT 24
Peak memory 249236 kb
Host smart-5c62dd5d-5a4d-441f-a5f8-426a2234192f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3648191676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3648191676
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.485657493
Short name T593
Test name
Test status
Simulation time 3753045275 ps
CPU time 52.21 seconds
Started Jul 07 04:47:32 PM PDT 24
Finished Jul 07 04:48:25 PM PDT 24
Peak memory 256836 kb
Host smart-5d537190-9762-4349-a26d-f7cc7f01f523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48565
7493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.485657493
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4181325312
Short name T410
Test name
Test status
Simulation time 727375436 ps
CPU time 46.31 seconds
Started Jul 07 04:47:39 PM PDT 24
Finished Jul 07 04:48:26 PM PDT 24
Peak memory 249580 kb
Host smart-7a41f8af-ec6c-4221-864b-073f10462d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41813
25312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4181325312
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2180043119
Short name T331
Test name
Test status
Simulation time 12661712991 ps
CPU time 653.74 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:58:28 PM PDT 24
Peak memory 273916 kb
Host smart-c0add641-4cb2-4c2b-99ec-89f475472799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180043119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2180043119
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.188475360
Short name T470
Test name
Test status
Simulation time 104879725867 ps
CPU time 2907.65 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 289108 kb
Host smart-28a79563-bfad-4b4e-ba9c-855c6477ab0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188475360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.188475360
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.136900022
Short name T315
Test name
Test status
Simulation time 10111199564 ps
CPU time 382.22 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 04:53:59 PM PDT 24
Peak memory 249236 kb
Host smart-956dddb1-13f5-4d79-ba75-175530ebe23a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136900022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.136900022
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4240948269
Short name T357
Test name
Test status
Simulation time 1622031847 ps
CPU time 29.7 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:48:02 PM PDT 24
Peak memory 249068 kb
Host smart-1c9c2b14-32bb-42d1-9d0f-732c06e07f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
48269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4240948269
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3315686367
Short name T644
Test name
Test status
Simulation time 5395414805 ps
CPU time 24.1 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:47:56 PM PDT 24
Peak memory 256952 kb
Host smart-88602d44-4626-4eee-b666-f1c99b62f633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33156
86367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3315686367
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2097352200
Short name T600
Test name
Test status
Simulation time 14430415869 ps
CPU time 57.01 seconds
Started Jul 07 04:47:31 PM PDT 24
Finished Jul 07 04:48:28 PM PDT 24
Peak memory 249264 kb
Host smart-0cc5c78a-50eb-4bb1-9661-d35471a9ff49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20973
52200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2097352200
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4085929570
Short name T591
Test name
Test status
Simulation time 681660411 ps
CPU time 8.17 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:47:44 PM PDT 24
Peak memory 255328 kb
Host smart-d710e8db-652c-4af1-beab-63f2e25572bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40859
29570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4085929570
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1859347488
Short name T75
Test name
Test status
Simulation time 6045578667 ps
CPU time 343.24 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:53:19 PM PDT 24
Peak memory 257380 kb
Host smart-f696e8c0-e5d3-4738-b339-9cb4ddaf1b5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859347488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1859347488
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3963300005
Short name T199
Test name
Test status
Simulation time 20771041 ps
CPU time 2.87 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:47:38 PM PDT 24
Peak memory 249456 kb
Host smart-725b4f71-5e2a-4d70-ab83-98fa043ec96b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3963300005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3963300005
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2956153107
Short name T111
Test name
Test status
Simulation time 154231914326 ps
CPU time 2117.39 seconds
Started Jul 07 04:47:37 PM PDT 24
Finished Jul 07 05:22:55 PM PDT 24
Peak memory 273844 kb
Host smart-da1ba5c8-f1f3-42ee-86d2-fcf210185b00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956153107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2956153107
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1954318847
Short name T653
Test name
Test status
Simulation time 1675639001 ps
CPU time 33.67 seconds
Started Jul 07 04:47:34 PM PDT 24
Finished Jul 07 04:48:08 PM PDT 24
Peak memory 249068 kb
Host smart-1d19d057-2af4-422c-b8e4-81202576a464
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1954318847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1954318847
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2658720569
Short name T527
Test name
Test status
Simulation time 14291341088 ps
CPU time 200.07 seconds
Started Jul 07 04:47:37 PM PDT 24
Finished Jul 07 04:50:58 PM PDT 24
Peak memory 251376 kb
Host smart-fed4b05e-d1fc-4958-bb45-048218140fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26587
20569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2658720569
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3262012809
Short name T554
Test name
Test status
Simulation time 1326162104 ps
CPU time 31.24 seconds
Started Jul 07 04:47:37 PM PDT 24
Finished Jul 07 04:48:09 PM PDT 24
Peak memory 257332 kb
Host smart-3f54f141-464d-48f6-95c5-1e19a60a1a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32620
12809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3262012809
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.802170215
Short name T505
Test name
Test status
Simulation time 88019119345 ps
CPU time 1517.49 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 05:12:54 PM PDT 24
Peak memory 289720 kb
Host smart-89e1dadb-d7f8-43f0-abbe-9d5d135f866b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802170215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.802170215
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2630735629
Short name T374
Test name
Test status
Simulation time 43407469202 ps
CPU time 1173.56 seconds
Started Jul 07 04:47:34 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 289340 kb
Host smart-aeadf0a8-84c7-4c47-8eea-7478105897d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630735629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2630735629
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1796495054
Short name T575
Test name
Test status
Simulation time 11466220397 ps
CPU time 117.63 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:49:33 PM PDT 24
Peak memory 249268 kb
Host smart-c7b7d049-a4b9-44d9-bc09-3c750fa8fab8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796495054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1796495054
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1623871731
Short name T534
Test name
Test status
Simulation time 3356484926 ps
CPU time 52.71 seconds
Started Jul 07 04:47:34 PM PDT 24
Finished Jul 07 04:48:27 PM PDT 24
Peak memory 257404 kb
Host smart-6015a0fa-5f0e-45e1-a5ca-feb64a6b144d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
71731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1623871731
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1111063280
Short name T445
Test name
Test status
Simulation time 20055972 ps
CPU time 3.09 seconds
Started Jul 07 04:47:33 PM PDT 24
Finished Jul 07 04:47:37 PM PDT 24
Peak memory 240884 kb
Host smart-be6f1df7-7f36-476c-90df-ee3ecdfbe1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
63280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1111063280
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.185477406
Short name T107
Test name
Test status
Simulation time 46908499 ps
CPU time 7.24 seconds
Started Jul 07 04:47:37 PM PDT 24
Finished Jul 07 04:47:44 PM PDT 24
Peak memory 254720 kb
Host smart-a0bb5405-8495-4777-a56e-0b27ac98c82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
7406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.185477406
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4291705535
Short name T556
Test name
Test status
Simulation time 3537792592 ps
CPU time 63.84 seconds
Started Jul 07 04:47:38 PM PDT 24
Finished Jul 07 04:48:42 PM PDT 24
Peak memory 257400 kb
Host smart-33ad8139-7a8c-4f5a-a829-7edc56399d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
05535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4291705535
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2893814501
Short name T568
Test name
Test status
Simulation time 212466309682 ps
CPU time 3190.31 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 303152 kb
Host smart-000d4fce-cb90-4547-b4ad-437e523f8692
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893814501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2893814501
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3932031868
Short name T205
Test name
Test status
Simulation time 27882184 ps
CPU time 2.8 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:47:38 PM PDT 24
Peak memory 249404 kb
Host smart-18c6e7fa-9f45-4e2e-b7b0-93712f425260
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3932031868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3932031868
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1942037957
Short name T73
Test name
Test status
Simulation time 46954327576 ps
CPU time 1050.39 seconds
Started Jul 07 04:47:38 PM PDT 24
Finished Jul 07 05:05:09 PM PDT 24
Peak memory 273744 kb
Host smart-a5f4211d-49e5-4568-91eb-8ed3aeecfc02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942037957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1942037957
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4277798136
Short name T502
Test name
Test status
Simulation time 1101115638 ps
CPU time 24.88 seconds
Started Jul 07 04:47:39 PM PDT 24
Finished Jul 07 04:48:04 PM PDT 24
Peak memory 249160 kb
Host smart-7b974173-5855-425c-884a-c3ecd3313abc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4277798136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4277798136
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2649331842
Short name T478
Test name
Test status
Simulation time 2213150290 ps
CPU time 36.92 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:48:18 PM PDT 24
Peak memory 256844 kb
Host smart-612ea4c8-4175-4a67-bfca-cd8ebe813f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26493
31842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2649331842
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.28237447
Short name T454
Test name
Test status
Simulation time 4808310131 ps
CPU time 59.07 seconds
Started Jul 07 04:47:42 PM PDT 24
Finished Jul 07 04:48:41 PM PDT 24
Peak memory 257316 kb
Host smart-980ef64a-225d-4042-bc28-acb39398bdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.28237447
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1592166801
Short name T285
Test name
Test status
Simulation time 19508775630 ps
CPU time 1242.97 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 05:08:19 PM PDT 24
Peak memory 273748 kb
Host smart-4a57cbeb-b00a-4e97-bce1-2b34e5d66ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592166801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1592166801
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.738271585
Short name T226
Test name
Test status
Simulation time 31484249386 ps
CPU time 1890.39 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 05:19:06 PM PDT 24
Peak memory 290148 kb
Host smart-dff83562-19d1-4268-bb5a-08df5cc66888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738271585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.738271585
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.304903302
Short name T317
Test name
Test status
Simulation time 3337114672 ps
CPU time 128.04 seconds
Started Jul 07 04:47:37 PM PDT 24
Finished Jul 07 04:49:45 PM PDT 24
Peak memory 249088 kb
Host smart-db30f5af-4899-4077-af68-ff9f841cbd03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304903302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.304903302
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4273187034
Short name T670
Test name
Test status
Simulation time 118907665 ps
CPU time 7.94 seconds
Started Jul 07 04:47:39 PM PDT 24
Finished Jul 07 04:47:47 PM PDT 24
Peak memory 249036 kb
Host smart-b5b98246-5b14-41a9-9e67-1c8b3a395629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42731
87034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4273187034
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2846933327
Short name T403
Test name
Test status
Simulation time 3155923045 ps
CPU time 35.78 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 04:48:12 PM PDT 24
Peak memory 257428 kb
Host smart-1f812bc3-2ab0-406f-a8cc-c5f9d2ca722a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28469
33327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2846933327
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2226054069
Short name T497
Test name
Test status
Simulation time 1527104018 ps
CPU time 46.14 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:48:21 PM PDT 24
Peak memory 249124 kb
Host smart-3622c1b7-1332-4b56-b46a-658c45421a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22260
54069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2226054069
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1941488170
Short name T482
Test name
Test status
Simulation time 28446726 ps
CPU time 3.96 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 04:47:44 PM PDT 24
Peak memory 251708 kb
Host smart-c7620e04-6d81-4a23-81fe-471b96344e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
88170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1941488170
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4180930761
Short name T525
Test name
Test status
Simulation time 379070825786 ps
CPU time 3350.81 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 05:43:26 PM PDT 24
Peak memory 305840 kb
Host smart-97d178f1-25bd-4768-93c2-40b7cc5ee8cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180930761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4180930761
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.997850961
Short name T68
Test name
Test status
Simulation time 20294008879 ps
CPU time 1328.2 seconds
Started Jul 07 04:47:38 PM PDT 24
Finished Jul 07 05:09:47 PM PDT 24
Peak memory 273920 kb
Host smart-b4ed255e-9758-4fa4-b3df-1fc20aba481d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997850961 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.997850961
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2238535114
Short name T196
Test name
Test status
Simulation time 37049342 ps
CPU time 2.09 seconds
Started Jul 07 04:47:39 PM PDT 24
Finished Jul 07 04:47:41 PM PDT 24
Peak memory 249396 kb
Host smart-53ef81db-785b-435c-8923-57e9df93d5c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2238535114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2238535114
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2801368999
Short name T519
Test name
Test status
Simulation time 21663305075 ps
CPU time 1365.08 seconds
Started Jul 07 04:47:38 PM PDT 24
Finished Jul 07 05:10:24 PM PDT 24
Peak memory 273220 kb
Host smart-42192f01-4689-4984-bdc5-2038936d7a3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801368999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2801368999
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4261971059
Short name T498
Test name
Test status
Simulation time 1015136767 ps
CPU time 14.47 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:47:56 PM PDT 24
Peak memory 249052 kb
Host smart-fba19472-b8bd-42a8-ab93-006fc6b68b66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4261971059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4261971059
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2654788877
Short name T669
Test name
Test status
Simulation time 1418574213 ps
CPU time 52.53 seconds
Started Jul 07 04:47:39 PM PDT 24
Finished Jul 07 04:48:32 PM PDT 24
Peak memory 256836 kb
Host smart-1b44fd36-0d3d-47b2-8fd0-5bba19e9dd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26547
88877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2654788877
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.694389602
Short name T22
Test name
Test status
Simulation time 338190477 ps
CPU time 25.21 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:48:06 PM PDT 24
Peak memory 256132 kb
Host smart-f194ac17-9d86-45a6-a4c0-e3a2014627a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69438
9602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.694389602
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.60079107
Short name T702
Test name
Test status
Simulation time 16433130317 ps
CPU time 1842.26 seconds
Started Jul 07 04:47:43 PM PDT 24
Finished Jul 07 05:18:25 PM PDT 24
Peak memory 289204 kb
Host smart-19f612ce-16c9-48f9-8f13-777973938b77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60079107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.60079107
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.147118695
Short name T466
Test name
Test status
Simulation time 422988651167 ps
CPU time 2503.43 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 282024 kb
Host smart-fffbe1aa-c7db-4f15-91de-0194917d3032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147118695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.147118695
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4209093259
Short name T543
Test name
Test status
Simulation time 31279715694 ps
CPU time 344.11 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:53:26 PM PDT 24
Peak memory 257172 kb
Host smart-b5f7b264-f7d0-481a-b677-3b037185f02c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209093259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4209093259
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.969918527
Short name T360
Test name
Test status
Simulation time 973322254 ps
CPU time 54.28 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 04:48:31 PM PDT 24
Peak memory 249112 kb
Host smart-25d35d1c-2bdd-42c5-b86c-33955113f4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96991
8527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.969918527
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1024830827
Short name T48
Test name
Test status
Simulation time 1026944853 ps
CPU time 18.36 seconds
Started Jul 07 04:47:35 PM PDT 24
Finished Jul 07 04:47:54 PM PDT 24
Peak memory 248652 kb
Host smart-4c2ca56a-333e-410f-8db4-2120cae84cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
30827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1024830827
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2115744113
Short name T237
Test name
Test status
Simulation time 296161369 ps
CPU time 31.28 seconds
Started Jul 07 04:47:36 PM PDT 24
Finished Jul 07 04:48:08 PM PDT 24
Peak memory 256640 kb
Host smart-17b6190a-b35a-4f92-970d-a954134c30a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21157
44113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2115744113
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1220677841
Short name T550
Test name
Test status
Simulation time 86763765 ps
CPU time 9.7 seconds
Started Jul 07 04:47:34 PM PDT 24
Finished Jul 07 04:47:44 PM PDT 24
Peak memory 249116 kb
Host smart-0160e75b-1743-430b-abd1-365b25fdc7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12206
77841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1220677841
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3231168743
Short name T619
Test name
Test status
Simulation time 56993296775 ps
CPU time 1364.09 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 05:10:25 PM PDT 24
Peak memory 290228 kb
Host smart-7c81e0b1-0dc1-456b-a49d-7e20b507f4c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231168743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3231168743
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3807376473
Short name T228
Test name
Test status
Simulation time 31847414244 ps
CPU time 1091.01 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 05:05:52 PM PDT 24
Peak memory 272940 kb
Host smart-604b4c4d-1b95-40fe-9017-e22f52dcb939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807376473 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3807376473
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.211654828
Short name T208
Test name
Test status
Simulation time 14901670 ps
CPU time 2.55 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 04:47:43 PM PDT 24
Peak memory 249404 kb
Host smart-40938c64-896c-44d5-a0d0-bb7e5ea5d652
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=211654828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.211654828
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1125996571
Short name T439
Test name
Test status
Simulation time 155147017609 ps
CPU time 2389.49 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 05:27:30 PM PDT 24
Peak memory 284732 kb
Host smart-af17ccaa-9076-458d-850c-ed508ea28d01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125996571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1125996571
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.110174573
Short name T691
Test name
Test status
Simulation time 5483637687 ps
CPU time 84.14 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 256884 kb
Host smart-f459d97f-f309-4847-8bbe-4614b5ceb226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11017
4573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.110174573
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1727010418
Short name T372
Test name
Test status
Simulation time 236782638 ps
CPU time 8.06 seconds
Started Jul 07 04:47:38 PM PDT 24
Finished Jul 07 04:47:47 PM PDT 24
Peak memory 248700 kb
Host smart-9136d8a8-22be-446f-9301-54cb5875b487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17270
10418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1727010418
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.342914927
Short name T630
Test name
Test status
Simulation time 48621435159 ps
CPU time 2497.56 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 05:29:18 PM PDT 24
Peak memory 281896 kb
Host smart-6172a5ff-7100-4550-88a2-bd6a4f951301
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342914927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.342914927
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2343571351
Short name T90
Test name
Test status
Simulation time 32157928263 ps
CPU time 1939.69 seconds
Started Jul 07 04:47:42 PM PDT 24
Finished Jul 07 05:20:02 PM PDT 24
Peak memory 286652 kb
Host smart-29499278-1261-4c9b-bbfa-79e4a15692fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343571351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2343571351
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.603256788
Short name T309
Test name
Test status
Simulation time 68402893001 ps
CPU time 335.9 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:53:17 PM PDT 24
Peak memory 249196 kb
Host smart-409f1a15-fbbb-4df3-bdcb-4a41f8fde499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603256788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.603256788
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.436757
Short name T570
Test name
Test status
Simulation time 215272481 ps
CPU time 4.82 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 04:47:45 PM PDT 24
Peak memory 240964 kb
Host smart-b6832286-58d8-4099-b7a5-01a38ed52607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43675
7 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.436757
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1256266956
Short name T597
Test name
Test status
Simulation time 1924077677 ps
CPU time 60.95 seconds
Started Jul 07 04:47:42 PM PDT 24
Finished Jul 07 04:48:43 PM PDT 24
Peak memory 248484 kb
Host smart-cacaa77c-3431-4725-aa0b-289d6802b17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
66956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1256266956
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.713049397
Short name T108
Test name
Test status
Simulation time 878431490 ps
CPU time 30.71 seconds
Started Jul 07 04:47:40 PM PDT 24
Finished Jul 07 04:48:11 PM PDT 24
Peak memory 249216 kb
Host smart-aa6b2a1a-361c-458c-9e6b-63b604e73e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71304
9397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.713049397
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1184642150
Short name T487
Test name
Test status
Simulation time 74558328 ps
CPU time 9.5 seconds
Started Jul 07 04:47:41 PM PDT 24
Finished Jul 07 04:47:50 PM PDT 24
Peak memory 255804 kb
Host smart-0a6ae6fd-8c20-4880-b86a-039f5ff062b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11846
42150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1184642150
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1143030619
Short name T250
Test name
Test status
Simulation time 21944768665 ps
CPU time 613.57 seconds
Started Jul 07 04:47:42 PM PDT 24
Finished Jul 07 04:57:56 PM PDT 24
Peak memory 257444 kb
Host smart-90d130c7-5e4d-4c89-b74d-5642b637fc30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143030619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1143030619
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3654800083
Short name T544
Test name
Test status
Simulation time 81446422975 ps
CPU time 6517.41 seconds
Started Jul 07 04:47:44 PM PDT 24
Finished Jul 07 06:36:32 PM PDT 24
Peak memory 355736 kb
Host smart-b1090086-4c1f-4732-999f-fe6159bce4df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654800083 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3654800083
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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