Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	69386	1			T2	3640		T5	2		T9	22
class_i[0x1]	45508	1			T5	1		T16	29		T26	4
class_i[0x2]	67103	1			T9	7		T16	2		T34	22
class_i[0x3]	51467	1			T5	1		T9	4289		T16	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	55719	1			T2	896		T9	1198		T16	2
alert[0x1]	59545	1			T2	772		T5	3		T9	1037
alert[0x2]	58681	1			T2	987		T9	993		T16	12
alert[0x3]	59519	1			T2	985		T5	1		T9	1090

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

233182

1

T2

3640

T5

2

T9

4318

esc_ping_fail

282

1

T5

2

T11

6

T12

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	55632	1			T2	896		T9	1198		T16	2
esc_integrity_fail	alert[0x1]	59473	1			T2	772		T5	2		T9	1037
esc_integrity_fail	alert[0x2]	58612	1			T2	987		T9	993		T16	12
esc_integrity_fail	alert[0x3]	59465	1			T2	985		T9	1090		T16	12
esc_ping_fail	alert[0x0]	87	1			T11	2		T12	1		T74	2
esc_ping_fail	alert[0x1]	72	1			T5	1		T11	1		T12	3
esc_ping_fail	alert[0x2]	69	1			T11	3		T12	2		T74	1
esc_ping_fail	alert[0x3]	54	1			T5	1		T12	1		T219	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	69291	1			T2	3640		T5	2		T9	22
esc_integrity_fail	class_i[0x1]	45416	1			T16	29		T26	4		T11	12
esc_integrity_fail	class_i[0x2]	67065	1			T9	7		T16	2		T34	22
esc_integrity_fail	class_i[0x3]	51410	1			T9	4289		T16	1		T34	11
esc_ping_fail	class_i[0x0]	95	1			T74	3		T219	6		T218	1
esc_ping_fail	class_i[0x1]	92	1			T5	1		T11	6		T12	7
esc_ping_fail	class_i[0x2]	38	1			T295	1		T99	3		T294	2
esc_ping_fail	class_i[0x3]	57	1			T5	1		T74	1		T218	1