Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	623977616	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	623977616	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	623977616	623795199	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	623977616	623795199	0	0
tb.dut.EdnKnownO_A	0	0	623977616	623795199	0	0
tb.dut.EscPKnownO_A	0	0	623977616	623795199	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	623977616	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	623977616	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	623977616	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	623977616	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	623977616	90	0	0
tb.dut.IrqAKnownO_A	0	0	623977616	623795199	0	0
tb.dut.IrqBKnownO_A	0	0	623977616	623795199	0	0
tb.dut.IrqCKnownO_A	0	0	623977616	623795199	0	0
tb.dut.IrqDKnownO_A	0	0	623977616	623795199	0	0
tb.dut.TlAReadyKnownO_A	0	0	623977616	623795199	0	0
tb.dut.TlDValidKnownO_A	0	0	623977616	623795199	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	647751018	2657545	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	647751018	6476	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	647751018	6620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	647751018	6834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	647751018	6793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	647751018	6585	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	647751018	6774	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	647751018	6598	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	647751018	6659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	647751018	7124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	647751018	7384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	647751018	7048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	647751018	6536	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	647751018	7035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	647751018	7160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	647751018	7306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	647751018	6445	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	647751018	7290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	647751018	6508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	647751018	6666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	647751018	7086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	647751018	7272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	647751018	6985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	647751018	7061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	647751018	7127	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	647751018	6604	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	647751018	7117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	647751018	7775	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	647751018	7508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	647751018	6445	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	647751018	7272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	647751018	7178	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	647751018	6572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	647751018	7083	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	647751018	7758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	647751018	6768	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	647751018	6468	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	647751018	7283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	647751018	6340	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	647751018	7241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	647751018	6596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	647751018	7284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	647751018	6508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	647751018	7124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	647751018	6540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	647751018	7178	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	647751018	6394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	647751018	6287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	647751018	7824	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	647751018	7052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	647751018	6486	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	647751018	6996	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	647751018	6727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	647751018	6614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	647751018	6740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	647751018	6388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	647751018	6690	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	647751018	8111	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	647751018	6600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	647751018	7999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	647751018	7072	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	647751018	6799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	647751018	7151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	647751018	6530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	647751018	6465	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	647751018	7620	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	647751018	6500	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	647751018	6590	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	647751018	6649	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	647751018	6877	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	647751018	9965	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	647751018	6458	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	647751018	6478	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	647751018	7337	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	647751018	6395	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	647751018	7053	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	647751018	6349	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	647751018	6628	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	647751018	6428	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	623977616	5989	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	623977616	250880	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	623977616	304577230	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	623977616	273	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	623977616	801	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	623977616	28	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	623977616	351	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	623608333	222868399	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	623977616	876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	623977616	854	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	623977616	834	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	623977616	817	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	623977616	983	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	623977616	102212	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	623977616	889	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	623977616	65	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	623977616	1662	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	623977616	1392	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	623606642	623537595	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	623977616	623795199	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	623977616	1714	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	623977616	141181	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	623977616	362790349	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	623977616	294	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	623977616	442	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	623977616	17	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	623977616	182	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	623608333	291133224	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	623977616	510	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	623977616	505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	623977616	498	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	623977616	493	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	623977616	1505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	623977616	130962	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	623977616	1432	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	623977616	54	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	623977616	1597	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	623977616	1327	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	623606642	623537595	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	623977616	623795199	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	623977616	3000	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	623977616	188323	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	623977616	347015308	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	623977616	312	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	623977616	534	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	623977616	13	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	623977616	275	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	623608333	278510454	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	623977616	604	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	623977616	589	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	623977616	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	623977616	553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	623977616	1635	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	623977616	122444	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	623977616	1549	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	623977616	71	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	623977616	1680	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	623977616	1410	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	623606642	623537595	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	623977616	623795199	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	623977616	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	623977616	3332	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	623977616	172928	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	623977616	358130432	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	623977616	329	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	623977616	460	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	623977616	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	623977616	211	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	623608333	303622442	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	623977616	536	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	623977616	526	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	623977616	519	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	623977616	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	623977616	1053	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	623977616	101968	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	623977616	966	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	623977616	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	623977616	1618	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	623977616	1348	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	623606642	623537595	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	623977616	623795199	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	647751018	124314566	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	647751018	647069630	0	0
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