Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.53	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	5	39	88.64

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	5	39	88.64	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	192	1			T2	1		T248	1		T97	2
index[0x1]	159	1			T2	1		T31	1		T24	1
index[0x2]	151	1			T2	1		T7	1		T17	2
index[0x3]	151	1			T24	1		T17	1		T20	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	207	1			T2	1		T17	1		T38	1
lens_less_than_1000[1]	145	1			T31	1		T20	1		T97	1
lens_less_than_1000[2]	90	1			T17	1		T20	2		T36	1
lens_less_than_1000[3]	73	1			T17	1		T77	1		T34	1
lens_less_than_1000[4]	44	1			T7	1		T74	1		T81	1
lens_less_than_1000[5]	36	1			T2	1		T17	1		T51	1
lens_less_than_1000[6]	12	1			T24	1		T95	1		T54	1
lens_less_than_1000[7]	27	1			T24	1		T112	10		T249	1
lens_less_than_1000[8]	6	1			T250	1		T251	1		T109	1
lens_less_than_1000[9]	6	1			T2	1		T252	1		T101	3
len_2	7	1			T251	1		T253	1		T254	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	5	39	88.64	5

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x1]]	[len_2]	0	1	1
[index[0x2]]	[lens_less_than_1000[6]]	0	1	1
[index[0x2]]	[lens_less_than_1000[8]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	63	1			T2	1		T97	2		T36	1
index[0x0]	lens_less_than_1000[1]	34	1			T73	1		T53	1		T112	1
index[0x0]	lens_less_than_1000[2]	31	1			T36	1		T112	1		T55	1
index[0x0]	lens_less_than_1000[3]	22	1			T52	1		T91	1		T94	1
index[0x0]	lens_less_than_1000[4]	10	1			T74	1		T252	1		T62	1
index[0x0]	lens_less_than_1000[5]	8	1			T248	1		T255	1		T67	1
index[0x0]	lens_less_than_1000[6]	2	1			T63	1		T256	1		-	-
index[0x0]	lens_less_than_1000[7]	17	1			T112	10		T249	1		T81	1
index[0x0]	lens_less_than_1000[8]	2	1			T257	1		T258	1		-	-
index[0x0]	len_2	3	1			T259	1		T125	1		T260	1
index[0x1]	lens_less_than_1000[0]	48	1			T34	3		T75	1		T76	2
index[0x1]	lens_less_than_1000[1]	49	1			T31	1		T20	1		T34	2
index[0x1]	lens_less_than_1000[2]	17	1			T72	1		T55	1		T98	2
index[0x1]	lens_less_than_1000[3]	15	1			T17	1		T54	1		T261	1
index[0x1]	lens_less_than_1000[4]	12	1			T81	1		T262	1		T263	1
index[0x1]	lens_less_than_1000[5]	7	1			T2	1		T217	1		T264	1
index[0x1]	lens_less_than_1000[6]	3	1			T24	1		T265	1		T266	1
index[0x1]	lens_less_than_1000[7]	3	1			T106	1		T267	1		T268	1
index[0x1]	lens_less_than_1000[8]	2	1			T251	1		T47	1		-	-
index[0x1]	lens_less_than_1000[9]	3	1			T101	3		-	-		-	-
index[0x2]	lens_less_than_1000[0]	54	1			T17	1		T34	1		T37	1
index[0x2]	lens_less_than_1000[1]	32	1			T97	1		T34	1		T37	2
index[0x2]	lens_less_than_1000[2]	20	1			T17	1		T54	1		T98	2
index[0x2]	lens_less_than_1000[3]	17	1			T77	1		T34	1		T81	1
index[0x2]	lens_less_than_1000[4]	8	1			T7	1		T98	1		T62	1
index[0x2]	lens_less_than_1000[5]	12	1			T37	1		T81	2		T269	1
index[0x2]	lens_less_than_1000[7]	4	1			T122	1		T62	1		T270	1
index[0x2]	lens_less_than_1000[9]	3	1			T2	1		T252	1		T271	1
index[0x2]	len_2	1	1			T253	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	42	1			T38	1		T34	2		T89	1
index[0x3]	lens_less_than_1000[1]	30	1			T36	1		T78	1		T79	1
index[0x3]	lens_less_than_1000[2]	22	1			T20	2		T272	1		T221	1
index[0x3]	lens_less_than_1000[3]	19	1			T91	1		T55	3		T57	1
index[0x3]	lens_less_than_1000[4]	14	1			T100	1		T273	3		T238	1
index[0x3]	lens_less_than_1000[5]	9	1			T17	1		T51	1		T262	1
index[0x3]	lens_less_than_1000[6]	7	1			T95	1		T54	1		T274	1
index[0x3]	lens_less_than_1000[7]	3	1			T24	1		T129	1		T106	1
index[0x3]	lens_less_than_1000[8]	2	1			T250	1		T109	1		-	-
index[0x3]	len_2	3	1			T251	1		T254	2		-	-