Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T2	1		T21	1		T34	1
class_index[0x1]	54	1			T2	1		T9	1		T34	1
class_index[0x2]	70	1			T2	1		T4	1		T31	2
class_index[0x3]	62	1			T21	1		T37	3		T70	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	107	1			T2	3		T4	1		T31	2
intr_timeout_cnt[1]	50	1			T21	1		T34	1		T37	2
intr_timeout_cnt[2]	15	1			T70	1		T76	2		T93	1
intr_timeout_cnt[3]	18	1			T79	1		T54	1		T55	2
intr_timeout_cnt[4]	12	1			T34	1		T81	2		T82	1
intr_timeout_cnt[5]	11	1			T89	1		T275	1		T98	1
intr_timeout_cnt[6]	12	1			T37	2		T95	1		T81	2
intr_timeout_cnt[7]	13	1			T95	1		T81	1		T54	1
intr_timeout_cnt[8]	9	1			T62	1		T276	2		T277	2
intr_timeout_cnt[9]	4	1			T276	1		T278	1		T279	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	20	1			T2	1		T37	1		T91	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T21	1		T37	2		T94	1
class_index[0x0]	intr_timeout_cnt[2]	2	1			T209	1		T280	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	12	1			T54	1		T55	2		T281	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T34	1		T82	1		T282	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T89	1		T117	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T95	1		T54	1		T33	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T277	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T276	1		T247	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	27	1			T2	1		T9	1		T37	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T34	1		T94	1		T82	1
class_index[0x1]	intr_timeout_cnt[2]	1	1			T110	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	3	1			T79	1		T117	1		T105	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T283	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T275	1		T284	1		T285	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T95	1		T81	1		T276	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T245	1		T286	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T278	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	31	1			T2	1		T4	1		T31	2
class_index[0x2]	intr_timeout_cnt[1]	13	1			T91	3		T120	1		T281	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T93	1		T121	1		T32	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T108	1		T245	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T81	2		T287	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T105	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T81	1		T108	1		T67	1
class_index[0x2]	intr_timeout_cnt[7]	6	1			T81	1		T253	2		T277	2
class_index[0x2]	intr_timeout_cnt[8]	6	1			T62	1		T276	2		T283	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T279	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	29	1			T21	1		T37	1		T75	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T36	1		T89	1		T114	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T70	1		T76	2		T81	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T285	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T288	1		T286	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	5	1			T98	1		T117	1		T209	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T37	2		T108	1		T287	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T289	1		-	-		-	-