Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336116	1			T2	2165		T3	41		T6	37
all_values[1]	336116	1			T2	2165		T3	41		T6	37
all_values[2]	336116	1			T2	2165		T3	41		T6	37
all_values[3]	336116	1			T2	2165		T3	41		T6	37

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

669561

1

T2

4391

T3

72

T6

76

auto[1]

674903

1

T2

4269

T3

92

T6

72

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

813056

1

T2

6597

T3

144

T6

137

auto[1]

531408

1

T2

2063

T3

20

T6

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96142	1			T2	571		T3	8		T6	14
all_values[0]	auto[0]	auto[1]	70883	1			T2	547		T3	8		T6	6
all_values[0]	auto[1]	auto[0]	97965	1			T2	534		T3	13		T6	12
all_values[0]	auto[1]	auto[1]	71126	1			T2	513		T3	12		T6	5
all_values[1]	auto[0]	auto[0]	102596	1			T2	925		T3	16		T6	21
all_values[1]	auto[0]	auto[1]	65194	1			T2	180		T28	2		T29	42
all_values[1]	auto[1]	auto[0]	103663	1			T2	903		T3	25		T6	16
all_values[1]	auto[1]	auto[1]	64663	1			T2	157		T27	1		T28	1
all_values[2]	auto[0]	auto[0]	103930	1			T2	920		T3	23		T6	19
all_values[2]	auto[0]	auto[1]	63380	1			T2	175		T28	1		T29	26
all_values[2]	auto[1]	auto[0]	105234	1			T2	912		T3	18		T6	18
all_values[2]	auto[1]	auto[1]	63572	1			T2	158		T27	1		T28	2
all_values[3]	auto[0]	auto[0]	101094	1			T2	907		T3	17		T6	16
all_values[3]	auto[0]	auto[1]	66342	1			T2	166		T27	1		T28	1
all_values[3]	auto[1]	auto[0]	102432	1			T2	925		T3	24		T6	21
all_values[3]	auto[1]	auto[1]	66248	1			T2	167		T28	2		T29	41