Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	336116	1			T2	2165		T3	41		T6	37
all_pins[1]	336116	1			T2	2165		T3	41		T6	37
all_pins[2]	336116	1			T2	2165		T3	41		T6	37
all_pins[3]	336116	1			T2	2165		T3	41		T6	37

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1078855	1			T2	7665		T3	152		T6	143
values[0x1]	265609	1			T2	995		T3	12		T6	5
transitions[0x0=>0x1]	177901	1			T2	762		T3	12		T6	4
transitions[0x1=>0x0]	178158	1			T2	762		T3	12		T6	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	264990	1			T2	1652		T3	29		T6	32
all_pins[0]	values[0x1]	71126	1			T2	513		T3	12		T6	5
all_pins[0]	transitions[0x0=>0x1]	70469	1			T2	513		T3	12		T6	4
all_pins[0]	transitions[0x1=>0x0]	65848	1			T2	167		T28	2		T29	41
all_pins[1]	values[0x0]	271453	1			T2	2008		T3	41		T6	37
all_pins[1]	values[0x1]	64663	1			T2	157		T27	1		T28	1
all_pins[1]	transitions[0x0=>0x1]	35271	1			T2	82		T28	1		T29	14
all_pins[1]	transitions[0x1=>0x0]	41734	1			T2	438		T3	12		T6	5
all_pins[2]	values[0x0]	272544	1			T2	2007		T3	41		T6	37
all_pins[2]	values[0x1]	63572	1			T2	158		T27	1		T28	2
all_pins[2]	transitions[0x0=>0x1]	34843	1			T2	84		T28	2		T29	26
all_pins[2]	transitions[0x1=>0x0]	35934	1			T2	83		T28	1		T29	9
all_pins[3]	values[0x0]	269868	1			T2	1998		T3	41		T6	37
all_pins[3]	values[0x1]	66248	1			T2	167		T28	2		T29	41
all_pins[3]	transitions[0x0=>0x1]	37318	1			T2	83		T28	1		T29	19
all_pins[3]	transitions[0x1=>0x0]	34642	1			T2	74		T27	1		T28	1