Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	293	1			T171	4		T172	7		T173	7
all_values[1]	293	1			T171	4		T172	7		T173	7
all_values[2]	293	1			T171	4		T172	7		T173	7
all_values[3]	293	1			T171	4		T172	7		T173	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

654

1

T171

10

T172

13

T173

22

auto[1]

518

1

T171

6

T172

15

T173

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430

1

T171

9

T172

12

T173

9

auto[1]

742

1

T171

7

T172

16

T173

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660

1

T171

11

T172

17

T173

15

auto[1]

512

1

T171

5

T172

11

T173

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

55

1

T171

3

T172

1

T332

1

all_values[0]

auto[0]

auto[0]

auto[1]

34

1

T172

1

T173

3

T333

1

all_values[0]

auto[0]

auto[1]

auto[0]

48

1

T172

1

T332

1

T334

4

all_values[0]

auto[0]

auto[1]

auto[1]

30

1

T172

1

T333

1

T335

1

all_values[0]

auto[1]

auto[0]

auto[1]

73

1

T171

1

T172

2

T173

4

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T172

1

T332

1

T333

1

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T171

1

T172

1

T173

2

all_values[1]

auto[0]

auto[0]

auto[1]

24

1

T172

1

T173

1

T335

1

all_values[1]

auto[0]

auto[1]

auto[0]

54

1

T171

2

T332

2

T333

1

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T172

1

T173

1

T332

1

all_values[1]

auto[1]

auto[0]

auto[1]

71

1

T171

1

T172

1

T173

2

all_values[1]

auto[1]

auto[1]

auto[1]

54

1

T172

3

T173

1

T332

1

all_values[2]

auto[0]

auto[0]

auto[0]

58

1

T172

3

T173

2

T335

1

all_values[2]

auto[0]

auto[0]

auto[1]

33

1

T171

2

T335

1

T336

1

all_values[2]

auto[0]

auto[1]

auto[0]

43

1

T172

1

T333

2

T334

1

all_values[2]

auto[0]

auto[1]

auto[1]

28

1

T172

1

T173

1

T332

1

all_values[2]

auto[1]

auto[0]

auto[1]

75

1

T173

3

T335

2

T337

2

all_values[2]

auto[1]

auto[1]

auto[1]

56

1

T171

2

T172

2

T173

1

all_values[3]

auto[0]

auto[0]

auto[0]

67

1

T171

1

T172

2

T173

4

all_values[3]

auto[0]

auto[0]

auto[1]

24

1

T335

1

T334

1

T337

1

all_values[3]

auto[0]

auto[1]

auto[0]

44

1

T171

2

T172

3

T173

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T332

2

T333

1

T334

1

all_values[3]

auto[1]

auto[0]

auto[1]

79

1

T171

1

T172

1

T173

1

all_values[3]

auto[1]

auto[1]

auto[1]

51

1

T172

1

T173

1

T332

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal