Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	85712	1			T2	114		T7	290		T8	127
accum_cnt_1000	217560	1			T2	521		T29	52		T7	668
accum_cnt_100	24312	1			T2	133		T3	13		T29	43
accum_cnt_50	52291	1			T2	339		T3	8		T6	2
accum_cnt_10	163091	1			T2	451		T3	3		T6	22
accum_cnt_0	408805	1			T2	3602		T3	80		T6	88

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	247471	1			T2	1489		T3	26		T6	28
class_index[0x1]	247471	1			T2	1489		T3	26		T6	28
class_index[0x2]	247471	1			T2	1489		T3	26		T6	28
class_index[0x3]	247471	1			T2	1489		T3	26		T6	28

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25487	1			T2	114		T16	61		T17	354
class_index[0x0]	accum_cnt_1000	62150	1			T2	279		T8	579		T16	617
class_index[0x0]	accum_cnt_100	6985	1			T2	42		T3	13		T8	47
class_index[0x0]	accum_cnt_50	11353	1			T2	93		T3	8		T6	2
class_index[0x0]	accum_cnt_10	44870	1			T2	128		T3	3		T6	22
class_index[0x0]	accum_cnt_0	84527	1			T2	37		T3	2		T6	4
class_index[0x1]	accum_cnt_2000	15684	1			T8	51		T9	552		T38	278
class_index[0x1]	accum_cnt_1000	50567	1			T2	106		T29	18		T8	543
class_index[0x1]	accum_cnt_100	5693	1			T2	41		T29	26		T8	29
class_index[0x1]	accum_cnt_50	16964	1			T2	68		T29	22		T8	25
class_index[0x1]	accum_cnt_10	46758	1			T2	159		T28	2		T29	5
class_index[0x1]	accum_cnt_0	105420	1			T2	1115		T3	26		T6	28
class_index[0x2]	accum_cnt_2000	24255	1			T8	76		T9	501		T18	564
class_index[0x2]	accum_cnt_1000	50686	1			T2	49		T29	34		T8	523
class_index[0x2]	accum_cnt_100	5414	1			T2	33		T29	17		T21	2
class_index[0x2]	accum_cnt_50	12528	1			T2	159		T29	14		T21	18
class_index[0x2]	accum_cnt_10	31939	1			T2	64		T28	2		T29	5
class_index[0x2]	accum_cnt_0	112248	1			T2	1184		T3	26		T6	28
class_index[0x3]	accum_cnt_2000	20286	1			T7	290		T9	252		T38	115
class_index[0x3]	accum_cnt_1000	54157	1			T2	87		T7	668		T23	50
class_index[0x3]	accum_cnt_100	6220	1			T2	17		T4	11		T7	41
class_index[0x3]	accum_cnt_50	11446	1			T2	19		T4	35		T7	30
class_index[0x3]	accum_cnt_10	39524	1			T2	100		T28	2		T4	23
class_index[0x3]	accum_cnt_0	106610	1			T2	1266		T3	26		T6	28