Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4395	1			T17	247		T26	120		T52	28
alert[0x1]	5191	1			T11	1		T53	2		T95	24
alert[0x2]	10575	1			T5	1		T12	1		T37	82
alert[0x3]	3784	1			T26	52		T11	1		T52	253
alert[0x4]	5907	1			T2	561		T11	1		T34	4
alert[0x5]	6485	1			T37	12		T219	1		T92	260
alert[0x6]	6648	1			T37	486		T52	23		T92	280
alert[0x7]	3702	1			T17	6		T34	7		T37	90
alert[0x8]	2827	1			T7	1		T34	1		T37	14
alert[0x9]	8028	1			T52	74		T218	1		T53	2
alert[0xa]	4525	1			T2	40		T11	1		T37	49
alert[0xb]	7380	1			T2	14		T17	2		T52	10
alert[0xc]	7409	1			T11	1		T52	138		T218	2
alert[0xd]	4825	1			T16	1		T12	1		T74	1
alert[0xe]	7867	1			T2	171		T52	10		T219	1
alert[0xf]	5193	1			T17	7		T52	32		T95	17
alert[0x10]	4218	1			T2	445		T11	1		T52	1997
alert[0x11]	5877	1			T2	30		T52	125		T36	8
alert[0x12]	3067	1			T2	1789		T17	12		T12	1
alert[0x13]	5070	1			T2	32		T17	6		T52	68
alert[0x14]	4162	1			T5	1		T9	4		T10	1
alert[0x15]	3113	1			T37	89		T52	104		T36	1
alert[0x16]	1811	1			T10	1		T34	5		T12	1
alert[0x17]	3499	1			T52	220		T218	1		T79	128
alert[0x18]	5863	1			T16	5		T11	1		T34	1
alert[0x19]	10091	1			T12	1		T52	74		T89	5
alert[0x1a]	7596	1			T34	12		T53	2		T95	61
alert[0x1b]	3102	1			T17	6		T37	557		T52	3
alert[0x1c]	2175	1			T17	32		T34	1		T12	1
alert[0x1d]	5822	1			T2	1		T11	1		T12	1
alert[0x1e]	3819	1			T12	1		T52	15		T36	4
alert[0x1f]	5401	1			T218	1		T79	357		T112	137
alert[0x20]	6389	1			T2	1		T11	1		T52	2
alert[0x21]	8901	1			T37	4		T52	8		T112	82
alert[0x22]	12098	1			T2	692		T52	662		T74	1
alert[0x23]	3687	1			T17	5		T11	1		T89	23
alert[0x24]	4530	1			T9	1		T16	1		T34	5
alert[0x25]	6535	1			T12	1		T52	17		T79	158
alert[0x26]	3846	1			T26	13		T37	12		T89	85
alert[0x27]	7732	1			T5	1		T34	1		T37	68
alert[0x28]	4811	1			T17	275		T26	5		T12	1
alert[0x29]	2731	1			T37	821		T36	5		T218	1
alert[0x2a]	3916	1			T9	37		T52	483		T218	1
alert[0x2b]	3681	1			T17	68		T11	1		T52	68
alert[0x2c]	3790	1			T17	8		T26	16		T12	1
alert[0x2d]	6521	1			T17	2		T12	1		T36	1
alert[0x2e]	2504	1			T2	27		T34	3		T52	10
alert[0x2f]	5850	1			T9	4		T17	11		T34	10
alert[0x30]	4632	1			T219	1		T79	344		T82	1
alert[0x31]	13330	1			T17	8		T11	1		T52	9
alert[0x32]	14927	1			T2	118		T89	2		T95	1
alert[0x33]	3023	1			T9	1		T52	51		T218	2
alert[0x34]	1740	1			T2	144		T34	1		T37	64
alert[0x35]	4033	1			T2	45		T89	6		T219	1
alert[0x36]	7972	1			T17	9		T37	2624		T272	2
alert[0x37]	2319	1			T34	2		T12	1		T37	159
alert[0x38]	3792	1			T34	1		T52	55		T36	85
alert[0x39]	6285	1			T34	3		T37	8		T36	352
alert[0x3a]	10865	1			T5	1		T26	49		T34	18
alert[0x3b]	5981	1			T17	6		T74	1		T218	1
alert[0x3c]	3193	1			T2	55		T17	19		T26	16
alert[0x3d]	4159	1			T2	29		T9	2		T34	4
alert[0x3e]	6417	1			T26	7		T11	1		T37	43
alert[0x3f]	5085	1			T17	6		T26	5		T52	116
alert[0x40]	7865	1			T17	14		T26	3		T52	3

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	130140	1			T2	4194		T9	2		T16	7
class_i[0x1]	80174	1			T9	25		T17	28		T34	5
class_i[0x2]	62413	1			T5	4		T7	1		T26	3
class_i[0x3]	89840	1			T9	22		T10	2		T26	283

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

361878

1

T2

4194

T9

49

T16

7

alert_ping_fail

689

1

T5

4

T7

1

T10

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4386	1			T17	247		T26	120		T52	28
alert_integrity_fail	alert[0x1]	5177	1			T53	2		T95	24		T112	287
alert_integrity_fail	alert[0x2]	10568	1			T37	82		T89	3		T113	226
alert_integrity_fail	alert[0x3]	3773	1			T26	52		T52	253		T79	284
alert_integrity_fail	alert[0x4]	5900	1			T2	561		T34	4		T37	13
alert_integrity_fail	alert[0x5]	6473	1			T37	12		T92	260		T79	14
alert_integrity_fail	alert[0x6]	6637	1			T37	486		T52	23		T92	280
alert_integrity_fail	alert[0x7]	3688	1			T17	6		T34	7		T37	90
alert_integrity_fail	alert[0x8]	2815	1			T34	1		T37	14		T52	65
alert_integrity_fail	alert[0x9]	8018	1			T52	74		T53	2		T81	4
alert_integrity_fail	alert[0xa]	4515	1			T2	40		T37	49		T93	1
alert_integrity_fail	alert[0xb]	7374	1			T2	14		T17	2		T52	10
alert_integrity_fail	alert[0xc]	7402	1			T52	138		T79	3448		T54	15
alert_integrity_fail	alert[0xd]	4812	1			T16	1		T79	113		T113	21
alert_integrity_fail	alert[0xe]	7859	1			T2	171		T52	10		T93	1
alert_integrity_fail	alert[0xf]	5185	1			T17	7		T52	32		T95	17
alert_integrity_fail	alert[0x10]	4210	1			T2	445		T52	1997		T36	2
alert_integrity_fail	alert[0x11]	5869	1			T2	30		T52	125		T36	8
alert_integrity_fail	alert[0x12]	3053	1			T2	1789		T17	12		T37	25
alert_integrity_fail	alert[0x13]	5053	1			T2	32		T17	6		T52	68
alert_integrity_fail	alert[0x14]	4139	1			T9	4		T17	177		T37	125
alert_integrity_fail	alert[0x15]	3104	1			T37	89		T52	104		T36	1
alert_integrity_fail	alert[0x16]	1790	1			T34	5		T52	194		T53	20
alert_integrity_fail	alert[0x17]	3488	1			T52	220		T79	128		T113	73
alert_integrity_fail	alert[0x18]	5855	1			T16	5		T34	1		T52	81
alert_integrity_fail	alert[0x19]	10081	1			T52	74		T89	5		T93	2
alert_integrity_fail	alert[0x1a]	7590	1			T34	12		T53	2		T95	61
alert_integrity_fail	alert[0x1b]	3090	1			T17	6		T37	557		T52	3
alert_integrity_fail	alert[0x1c]	2160	1			T17	32		T34	1		T37	10
alert_integrity_fail	alert[0x1d]	5811	1			T2	1		T52	1525		T36	2
alert_integrity_fail	alert[0x1e]	3806	1			T52	15		T36	4		T113	66
alert_integrity_fail	alert[0x1f]	5388	1			T79	357		T112	137		T81	103
alert_integrity_fail	alert[0x20]	6371	1			T2	1		T52	2		T293	30
alert_integrity_fail	alert[0x21]	8896	1			T37	4		T52	8		T112	82
alert_integrity_fail	alert[0x22]	12089	1			T2	692		T52	662		T79	97
alert_integrity_fail	alert[0x23]	3682	1			T17	5		T89	23		T92	227
alert_integrity_fail	alert[0x24]	4513	1			T9	1		T16	1		T34	5
alert_integrity_fail	alert[0x25]	6533	1			T52	17		T79	158		T113	6
alert_integrity_fail	alert[0x26]	3836	1			T26	13		T37	12		T89	85
alert_integrity_fail	alert[0x27]	7722	1			T34	1		T37	68		T36	27
alert_integrity_fail	alert[0x28]	4803	1			T17	275		T26	5		T36	1
alert_integrity_fail	alert[0x29]	2723	1			T37	821		T36	5		T79	4
alert_integrity_fail	alert[0x2a]	3909	1			T9	37		T52	483		T92	287
alert_integrity_fail	alert[0x2b]	3670	1			T17	68		T52	68		T36	1
alert_integrity_fail	alert[0x2c]	3774	1			T17	8		T26	16		T52	48
alert_integrity_fail	alert[0x2d]	6504	1			T17	2		T36	1		T92	258
alert_integrity_fail	alert[0x2e]	2491	1			T2	27		T34	3		T52	10
alert_integrity_fail	alert[0x2f]	5842	1			T9	4		T17	11		T34	10
alert_integrity_fail	alert[0x30]	4627	1			T79	344		T82	1		T293	24
alert_integrity_fail	alert[0x31]	13318	1			T17	8		T52	9		T79	419
alert_integrity_fail	alert[0x32]	14916	1			T2	118		T89	2		T95	1
alert_integrity_fail	alert[0x33]	3010	1			T9	1		T52	51		T92	120
alert_integrity_fail	alert[0x34]	1723	1			T2	144		T34	1		T37	64
alert_integrity_fail	alert[0x35]	4022	1			T2	45		T89	6		T95	23
alert_integrity_fail	alert[0x36]	7958	1			T17	9		T37	2624		T272	2
alert_integrity_fail	alert[0x37]	2313	1			T34	2		T37	159		T52	145
alert_integrity_fail	alert[0x38]	3781	1			T34	1		T52	55		T36	85
alert_integrity_fail	alert[0x39]	6275	1			T34	3		T37	8		T36	352
alert_integrity_fail	alert[0x3a]	10856	1			T26	49		T34	18		T36	2
alert_integrity_fail	alert[0x3b]	5971	1			T17	6		T79	116		T54	2
alert_integrity_fail	alert[0x3c]	3185	1			T2	55		T17	19		T26	16
alert_integrity_fail	alert[0x3d]	4153	1			T2	29		T9	2		T34	4
alert_integrity_fail	alert[0x3e]	6404	1			T26	7		T37	43		T52	42
alert_integrity_fail	alert[0x3f]	5080	1			T17	6		T26	5		T52	116
alert_integrity_fail	alert[0x40]	7859	1			T17	14		T26	3		T52	3
alert_ping_fail	alert[0x0]	9	1			T74	1		T218	1		T99	2
alert_ping_fail	alert[0x1]	14	1			T11	1		T99	3		T294	1
alert_ping_fail	alert[0x2]	7	1			T5	1		T12	1		T119	1
alert_ping_fail	alert[0x3]	11	1			T11	1		T119	1		T242	2
alert_ping_fail	alert[0x4]	7	1			T11	1		T219	1		T119	1
alert_ping_fail	alert[0x5]	12	1			T219	1		T217	2		T295	1
alert_ping_fail	alert[0x6]	11	1			T292	1		T242	1		T296	1
alert_ping_fail	alert[0x7]	14	1			T218	1		T292	1		T241	1
alert_ping_fail	alert[0x8]	12	1			T7	1		T297	1		T298	2
alert_ping_fail	alert[0x9]	10	1			T218	1		T99	1		T119	1
alert_ping_fail	alert[0xa]	10	1			T11	1		T74	1		T299	1
alert_ping_fail	alert[0xb]	6	1			T74	1		T218	1		T255	1
alert_ping_fail	alert[0xc]	7	1			T11	1		T218	2		T300	1
alert_ping_fail	alert[0xd]	13	1			T12	1		T74	1		T218	1
alert_ping_fail	alert[0xe]	8	1			T219	1		T294	1		T242	1
alert_ping_fail	alert[0xf]	8	1			T119	1		T301	1		T302	1
alert_ping_fail	alert[0x10]	8	1			T11	1		T301	1		T255	1
alert_ping_fail	alert[0x11]	8	1			T303	1		T304	1		T305	1
alert_ping_fail	alert[0x12]	14	1			T12	1		T74	1		T219	1
alert_ping_fail	alert[0x13]	17	1			T236	1		T306	1		T255	2
alert_ping_fail	alert[0x14]	23	1			T5	1		T10	1		T241	1
alert_ping_fail	alert[0x15]	9	1			T292	1		T242	1		T306	1
alert_ping_fail	alert[0x16]	21	1			T10	1		T12	1		T219	1
alert_ping_fail	alert[0x17]	11	1			T218	1		T242	1		T43	1
alert_ping_fail	alert[0x18]	8	1			T11	1		T218	1		T294	1
alert_ping_fail	alert[0x19]	10	1			T12	1		T295	1		T242	2
alert_ping_fail	alert[0x1a]	6	1			T116	1		T306	1		T307	1
alert_ping_fail	alert[0x1b]	12	1			T295	1		T99	1		T307	2
alert_ping_fail	alert[0x1c]	15	1			T12	1		T219	1		T218	1
alert_ping_fail	alert[0x1d]	11	1			T11	1		T12	1		T217	1
alert_ping_fail	alert[0x1e]	13	1			T12	1		T294	1		T306	2
alert_ping_fail	alert[0x1f]	13	1			T218	1		T295	1		T301	1
alert_ping_fail	alert[0x20]	18	1			T11	1		T218	2		T295	1
alert_ping_fail	alert[0x21]	5	1			T255	1		T256	1		T305	1
alert_ping_fail	alert[0x22]	9	1			T74	1		T218	1		T298	1
alert_ping_fail	alert[0x23]	5	1			T11	1		T99	1		T308	1
alert_ping_fail	alert[0x24]	17	1			T74	1		T219	1		T119	1
alert_ping_fail	alert[0x25]	2	1			T12	1		T303	1		-	-
alert_ping_fail	alert[0x26]	10	1			T119	1		T307	1		T192	1
alert_ping_fail	alert[0x27]	10	1			T5	1		T74	1		T99	1
alert_ping_fail	alert[0x28]	8	1			T12	1		T218	1		T302	1
alert_ping_fail	alert[0x29]	8	1			T218	1		T302	1		T298	1
alert_ping_fail	alert[0x2a]	7	1			T218	1		T294	1		T302	1
alert_ping_fail	alert[0x2b]	11	1			T11	1		T99	1		T297	2
alert_ping_fail	alert[0x2c]	16	1			T12	1		T295	2		T99	1
alert_ping_fail	alert[0x2d]	17	1			T12	1		T74	1		T295	1
alert_ping_fail	alert[0x2e]	13	1			T295	2		T294	1		T242	1
alert_ping_fail	alert[0x2f]	8	1			T119	1		T255	1		T302	1
alert_ping_fail	alert[0x30]	5	1			T219	1		T301	1		T304	1
alert_ping_fail	alert[0x31]	12	1			T11	1		T219	1		T119	1
alert_ping_fail	alert[0x32]	11	1			T295	1		T242	1		T302	1
alert_ping_fail	alert[0x33]	13	1			T218	2		T116	1		T119	1
alert_ping_fail	alert[0x34]	17	1			T295	2		T242	1		T301	1
alert_ping_fail	alert[0x35]	11	1			T219	1		T306	1		T303	3
alert_ping_fail	alert[0x36]	14	1			T116	1		T99	1		T309	1
alert_ping_fail	alert[0x37]	6	1			T12	1		T306	1		T310	1
alert_ping_fail	alert[0x38]	11	1			T219	1		T295	1		T294	1
alert_ping_fail	alert[0x39]	10	1			T99	1		T255	1		T304	1
alert_ping_fail	alert[0x3a]	9	1			T5	1		T12	2		T74	1
alert_ping_fail	alert[0x3b]	10	1			T74	1		T218	1		T99	2
alert_ping_fail	alert[0x3c]	8	1			T12	1		T74	1		T116	1
alert_ping_fail	alert[0x3d]	6	1			T12	1		T219	1		T301	1
alert_ping_fail	alert[0x3e]	13	1			T11	1		T74	1		T116	2
alert_ping_fail	alert[0x3f]	5	1			T74	1		T309	1		T304	1
alert_ping_fail	alert[0x40]	6	1			T255	1		T311	1		T312	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	129891	1			T2	4194		T9	2		T16	7
alert_integrity_fail	class_i[0x1]	80093	1			T9	25		T17	28		T34	5
alert_integrity_fail	class_i[0x2]	62184	1			T26	3		T34	25		T37	4
alert_integrity_fail	class_i[0x3]	89710	1			T9	22		T26	283		T34	9
alert_ping_fail	class_i[0x0]	249	1			T11	1		T12	14		T74	2
alert_ping_fail	class_i[0x1]	81	1			T12	2		T74	2		T219	12
alert_ping_fail	class_i[0x2]	229	1			T5	4		T7	1		T11	3
alert_ping_fail	class_i[0x3]	130	1			T10	2		T11	9		T12	1