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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.99 98.62 99.97 100.00 100.00 99.38 99.40


Total test records in report: 827
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T763 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.13694739 Jul 09 04:54:05 PM PDT 24 Jul 09 04:54:19 PM PDT 24 236278138 ps
T764 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.973246107 Jul 09 04:54:00 PM PDT 24 Jul 09 04:54:03 PM PDT 24 20981864 ps
T765 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4036344606 Jul 09 04:53:46 PM PDT 24 Jul 09 04:54:20 PM PDT 24 2037727585 ps
T766 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3275402026 Jul 09 04:54:03 PM PDT 24 Jul 09 04:54:05 PM PDT 24 8437235 ps
T767 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.732463614 Jul 09 04:54:06 PM PDT 24 Jul 09 04:54:08 PM PDT 24 37234317 ps
T768 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.135041558 Jul 09 04:54:08 PM PDT 24 Jul 09 04:54:18 PM PDT 24 437585719 ps
T769 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3365474684 Jul 09 04:53:45 PM PDT 24 Jul 09 04:54:03 PM PDT 24 242938636 ps
T770 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2506572646 Jul 09 04:53:43 PM PDT 24 Jul 09 04:53:54 PM PDT 24 187923618 ps
T771 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.997291324 Jul 09 04:54:05 PM PDT 24 Jul 09 04:54:14 PM PDT 24 952888554 ps
T772 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.223497320 Jul 09 04:53:52 PM PDT 24 Jul 09 04:54:05 PM PDT 24 136789659 ps
T773 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4183252680 Jul 09 04:54:02 PM PDT 24 Jul 09 04:54:32 PM PDT 24 4480488078 ps
T157 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1460400270 Jul 09 04:53:41 PM PDT 24 Jul 09 04:57:28 PM PDT 24 4099505033 ps
T774 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2233826757 Jul 09 04:53:40 PM PDT 24 Jul 09 04:54:24 PM PDT 24 2651274915 ps
T344 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1060483037 Jul 09 04:53:49 PM PDT 24 Jul 09 05:00:57 PM PDT 24 6584585553 ps
T775 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.878954694 Jul 09 04:54:09 PM PDT 24 Jul 09 04:54:13 PM PDT 24 17698143 ps
T776 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3151015816 Jul 09 04:53:30 PM PDT 24 Jul 09 04:53:38 PM PDT 24 75176865 ps
T167 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3833159517 Jul 09 04:53:38 PM PDT 24 Jul 09 05:00:20 PM PDT 24 2273952083 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2035258128 Jul 09 04:53:53 PM PDT 24 Jul 09 04:53:59 PM PDT 24 32805975 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.158982940 Jul 09 04:53:45 PM PDT 24 Jul 09 04:54:01 PM PDT 24 405605791 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.631276575 Jul 09 04:53:39 PM PDT 24 Jul 09 04:54:00 PM PDT 24 2686504719 ps
T780 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2603973442 Jul 09 04:54:03 PM PDT 24 Jul 09 04:54:05 PM PDT 24 11989687 ps
T781 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3254613811 Jul 09 04:53:54 PM PDT 24 Jul 09 04:53:56 PM PDT 24 8629244 ps
T782 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4098842553 Jul 09 04:53:50 PM PDT 24 Jul 09 04:53:52 PM PDT 24 8412845 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2714099018 Jul 09 04:53:52 PM PDT 24 Jul 09 04:54:03 PM PDT 24 289523522 ps
T161 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3277150696 Jul 09 04:53:34 PM PDT 24 Jul 09 04:57:00 PM PDT 24 2887631711 ps
T135 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2638017477 Jul 09 04:53:55 PM PDT 24 Jul 09 04:59:06 PM PDT 24 4415469260 ps
T784 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3819258085 Jul 09 04:53:42 PM PDT 24 Jul 09 04:53:58 PM PDT 24 210241719 ps
T785 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1860022615 Jul 09 04:53:52 PM PDT 24 Jul 09 04:54:05 PM PDT 24 471990380 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3069305654 Jul 09 04:53:35 PM PDT 24 Jul 09 04:53:46 PM PDT 24 316942052 ps
T787 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.252056037 Jul 09 04:53:51 PM PDT 24 Jul 09 04:54:08 PM PDT 24 148188986 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.982595836 Jul 09 04:53:41 PM PDT 24 Jul 09 04:58:26 PM PDT 24 5235344230 ps
T789 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2272910156 Jul 09 04:54:00 PM PDT 24 Jul 09 04:54:02 PM PDT 24 8047278 ps
T790 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3912439413 Jul 09 04:54:06 PM PDT 24 Jul 09 04:54:15 PM PDT 24 113439725 ps
T791 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3573700158 Jul 09 04:54:09 PM PDT 24 Jul 09 04:54:12 PM PDT 24 34450795 ps
T163 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4201620552 Jul 09 04:53:58 PM PDT 24 Jul 09 04:57:48 PM PDT 24 1711695433 ps
T164 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.25491461 Jul 09 04:54:07 PM PDT 24 Jul 09 04:55:45 PM PDT 24 819424751 ps
T792 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1812872503 Jul 09 04:54:00 PM PDT 24 Jul 09 04:54:20 PM PDT 24 341951887 ps
T793 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.580605935 Jul 09 04:54:04 PM PDT 24 Jul 09 04:54:07 PM PDT 24 30874353 ps
T794 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2273619594 Jul 09 04:53:39 PM PDT 24 Jul 09 04:56:33 PM PDT 24 9381303906 ps
T160 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2178311183 Jul 09 04:53:48 PM PDT 24 Jul 09 04:56:33 PM PDT 24 2322518447 ps
T795 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3686904655 Jul 09 04:53:34 PM PDT 24 Jul 09 04:53:36 PM PDT 24 6178748 ps
T796 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4191563572 Jul 09 04:53:45 PM PDT 24 Jul 09 04:53:54 PM PDT 24 180600051 ps
T797 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1219592675 Jul 09 04:54:03 PM PDT 24 Jul 09 04:54:05 PM PDT 24 10327617 ps
T798 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.203268575 Jul 09 04:54:08 PM PDT 24 Jul 09 04:54:11 PM PDT 24 8769572 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1207680052 Jul 09 04:54:00 PM PDT 24 Jul 09 04:59:40 PM PDT 24 8524855818 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3136410436 Jul 09 04:54:05 PM PDT 24 Jul 09 04:54:26 PM PDT 24 1414370513 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3085427042 Jul 09 04:53:41 PM PDT 24 Jul 09 04:53:43 PM PDT 24 12202694 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2832020645 Jul 09 04:53:41 PM PDT 24 Jul 09 04:53:43 PM PDT 24 10058348 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4182118111 Jul 09 04:53:46 PM PDT 24 Jul 09 04:53:50 PM PDT 24 19770843 ps
T188 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3054431602 Jul 09 04:54:04 PM PDT 24 Jul 09 04:54:53 PM PDT 24 331247953 ps
T803 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2732840175 Jul 09 04:53:42 PM PDT 24 Jul 09 04:54:21 PM PDT 24 517209149 ps
T166 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1519342683 Jul 09 04:53:53 PM PDT 24 Jul 09 05:10:32 PM PDT 24 15071123727 ps
T804 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3212106109 Jul 09 04:53:58 PM PDT 24 Jul 09 04:54:02 PM PDT 24 17797842 ps
T805 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3057635683 Jul 09 04:53:38 PM PDT 24 Jul 09 04:53:53 PM PDT 24 213258645 ps
T806 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.341331756 Jul 09 04:53:35 PM PDT 24 Jul 09 04:57:33 PM PDT 24 2966863298 ps
T807 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2231753109 Jul 09 04:54:08 PM PDT 24 Jul 09 04:54:11 PM PDT 24 15057282 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2952092801 Jul 09 04:53:40 PM PDT 24 Jul 09 04:53:46 PM PDT 24 196197040 ps
T809 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.986087164 Jul 09 04:53:32 PM PDT 24 Jul 09 04:53:34 PM PDT 24 13921113 ps
T810 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3214576756 Jul 09 04:53:50 PM PDT 24 Jul 09 04:54:00 PM PDT 24 60556846 ps
T811 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1245575496 Jul 09 04:53:46 PM PDT 24 Jul 09 04:53:52 PM PDT 24 29814618 ps
T812 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2795290482 Jul 09 04:53:41 PM PDT 24 Jul 09 04:53:58 PM PDT 24 603483426 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.783332239 Jul 09 04:53:32 PM PDT 24 Jul 09 04:57:56 PM PDT 24 4456696721 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.560459519 Jul 09 04:53:35 PM PDT 24 Jul 09 04:53:45 PM PDT 24 421870182 ps
T815 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3857783751 Jul 09 04:53:54 PM PDT 24 Jul 09 04:54:20 PM PDT 24 1221810198 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.763400228 Jul 09 04:53:34 PM PDT 24 Jul 09 04:53:40 PM PDT 24 65379703 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3935523165 Jul 09 04:54:05 PM PDT 24 Jul 09 04:54:07 PM PDT 24 31801070 ps
T818 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1840418156 Jul 09 04:54:08 PM PDT 24 Jul 09 04:54:10 PM PDT 24 10259960 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2678513643 Jul 09 04:53:54 PM PDT 24 Jul 09 04:54:04 PM PDT 24 283655065 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2942318869 Jul 09 04:53:58 PM PDT 24 Jul 09 04:54:33 PM PDT 24 2065604557 ps
T821 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3258175923 Jul 09 04:53:59 PM PDT 24 Jul 09 04:54:09 PM PDT 24 216541939 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2787083606 Jul 09 04:53:40 PM PDT 24 Jul 09 04:55:51 PM PDT 24 7585858555 ps
T823 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.310725320 Jul 09 04:53:40 PM PDT 24 Jul 09 04:53:46 PM PDT 24 193105211 ps
T824 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.610203639 Jul 09 04:54:00 PM PDT 24 Jul 09 04:54:23 PM PDT 24 570160160 ps
T825 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.427066368 Jul 09 04:54:06 PM PDT 24 Jul 09 04:54:08 PM PDT 24 24010411 ps
T162 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1289129886 Jul 09 04:53:36 PM PDT 24 Jul 09 05:09:52 PM PDT 24 23121379323 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.370264533 Jul 09 04:53:52 PM PDT 24 Jul 09 04:54:01 PM PDT 24 206511711 ps
T827 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2922726024 Jul 09 04:54:03 PM PDT 24 Jul 09 04:54:08 PM PDT 24 20238144 ps

Test location /workspace/coverage/default/29.alert_handler_stress_all.161736853
Short name T2
Test name
Test status
Simulation time 243035171554 ps
CPU time 1687.34 seconds
Started Jul 09 04:55:11 PM PDT 24
Finished Jul 09 05:23:19 PM PDT 24
Peak memory 290216 kb
Host smart-30252d08-9c8e-4fa2-854c-9bffb0f323e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161736853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.161736853
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2402515732
Short name T17
Test name
Test status
Simulation time 40269622879 ps
CPU time 3720.97 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 05:57:53 PM PDT 24
Peak memory 338824 kb
Host smart-3e4a4055-0c79-42ed-87a8-461e97ac47c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402515732 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2402515732
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3061297080
Short name T14
Test name
Test status
Simulation time 2159281611 ps
CPU time 26.55 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:45 PM PDT 24
Peak memory 270484 kb
Host smart-c25b643d-e3dc-4862-871e-f2ef5e050228
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3061297080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3061297080
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3129990590
Short name T34
Test name
Test status
Simulation time 142142599957 ps
CPU time 1867.86 seconds
Started Jul 09 04:55:18 PM PDT 24
Finished Jul 09 05:26:27 PM PDT 24
Peak memory 298456 kb
Host smart-3a4b5d5b-3f82-4a3c-91e7-99d888fbc347
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129990590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3129990590
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3923706404
Short name T130
Test name
Test status
Simulation time 22248189353 ps
CPU time 388.43 seconds
Started Jul 09 04:53:34 PM PDT 24
Finished Jul 09 05:00:03 PM PDT 24
Peak memory 265284 kb
Host smart-23765ec6-2467-4a90-9a09-b23273482d75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3923706404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3923706404
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.444169984
Short name T112
Test name
Test status
Simulation time 61718765304 ps
CPU time 1790.09 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 05:24:39 PM PDT 24
Peak memory 290016 kb
Host smart-b703fc9a-4ad3-48b3-8f56-d9a3a70fa0c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444169984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.444169984
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1645400165
Short name T169
Test name
Test status
Simulation time 1218471399 ps
CPU time 38.31 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:54:36 PM PDT 24
Peak memory 237776 kb
Host smart-9fe9c36f-fd35-4274-a694-87de1e3e319b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1645400165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1645400165
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2921005078
Short name T215
Test name
Test status
Simulation time 1828582008 ps
CPU time 77.06 seconds
Started Jul 09 04:54:39 PM PDT 24
Finished Jul 09 04:55:57 PM PDT 24
Peak memory 249124 kb
Host smart-ef613a39-9023-43c7-a6a1-4133f44cdb0c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2921005078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2921005078
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.109061818
Short name T10
Test name
Test status
Simulation time 166605918252 ps
CPU time 2450.38 seconds
Started Jul 09 04:54:35 PM PDT 24
Finished Jul 09 05:35:27 PM PDT 24
Peak memory 282020 kb
Host smart-ed894bd1-19a2-4c6f-9c90-638bf8cdb707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109061818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.109061818
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.782850903
Short name T317
Test name
Test status
Simulation time 74023836251 ps
CPU time 2331.55 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:33:51 PM PDT 24
Peak memory 282068 kb
Host smart-51dab494-17df-425a-a01e-fe8986da40f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782850903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.782850903
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2775556147
Short name T98
Test name
Test status
Simulation time 50391455813 ps
CPU time 1409.72 seconds
Started Jul 09 04:55:04 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 289832 kb
Host smart-f03988da-e278-4c1f-b164-f9cfbbdc8adf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775556147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2775556147
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.199126983
Short name T131
Test name
Test status
Simulation time 12249404564 ps
CPU time 849.76 seconds
Started Jul 09 04:54:01 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 272520 kb
Host smart-2db70209-063e-453e-a87f-79167827dad3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199126983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.199126983
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3316770414
Short name T151
Test name
Test status
Simulation time 4446381266 ps
CPU time 738.7 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 05:06:17 PM PDT 24
Peak memory 265260 kb
Host smart-bcd1391b-2829-4b19-87ff-c6698326c1eb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316770414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3316770414
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3498554597
Short name T100
Test name
Test status
Simulation time 65430104782 ps
CPU time 2225.96 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 05:31:20 PM PDT 24
Peak memory 282036 kb
Host smart-d65498f6-2995-4598-ab85-f6add6a1530f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498554597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3498554597
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3685457574
Short name T142
Test name
Test status
Simulation time 4175928007 ps
CPU time 357.08 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 04:59:49 PM PDT 24
Peak memory 265440 kb
Host smart-2ac7b0e3-c898-46b8-a9f6-2252cc1da7fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3685457574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3685457574
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2511408338
Short name T218
Test name
Test status
Simulation time 15500918612 ps
CPU time 685.01 seconds
Started Jul 09 04:56:03 PM PDT 24
Finished Jul 09 05:07:30 PM PDT 24
Peak memory 256328 kb
Host smart-7dd859a8-2767-44c2-a921-e2abe6553bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511408338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2511408338
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2724015734
Short name T217
Test name
Test status
Simulation time 211760867607 ps
CPU time 2934.41 seconds
Started Jul 09 04:55:30 PM PDT 24
Finished Jul 09 05:44:26 PM PDT 24
Peak memory 286764 kb
Host smart-822c8943-0791-4118-bb89-294fb483d890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724015734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2724015734
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3929180770
Short name T336
Test name
Test status
Simulation time 12673603 ps
CPU time 1.5 seconds
Started Jul 09 04:54:04 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 237456 kb
Host smart-58b76a42-6310-4d09-a6a7-8f2bcf8de864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3929180770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3929180770
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3103371849
Short name T140
Test name
Test status
Simulation time 12850452930 ps
CPU time 1016.75 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 05:11:14 PM PDT 24
Peak memory 265424 kb
Host smart-e84d97a1-d9d3-478c-9160-92a012aa28ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103371849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3103371849
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.637366778
Short name T55
Test name
Test status
Simulation time 47589291689 ps
CPU time 1995.03 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 05:27:50 PM PDT 24
Peak memory 288384 kb
Host smart-2b16b5bc-6ba1-4cf5-a064-882fe477edc0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637366778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.637366778
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3552435158
Short name T321
Test name
Test status
Simulation time 201248879279 ps
CPU time 2739.88 seconds
Started Jul 09 04:54:35 PM PDT 24
Finished Jul 09 05:40:16 PM PDT 24
Peak memory 288908 kb
Host smart-2bd1ad15-fe59-4b1e-b3d8-86b69a8b4b54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552435158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3552435158
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3553909253
Short name T242
Test name
Test status
Simulation time 49318889523 ps
CPU time 514.26 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 05:03:32 PM PDT 24
Peak memory 249268 kb
Host smart-9c408808-63b3-4845-991e-7a965c5cf69c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553909253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3553909253
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2112636480
Short name T149
Test name
Test status
Simulation time 3083743749 ps
CPU time 207.83 seconds
Started Jul 09 04:54:06 PM PDT 24
Finished Jul 09 04:57:35 PM PDT 24
Peak memory 265360 kb
Host smart-c51abea1-5397-418d-801d-14071cb5cfa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2112636480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2112636480
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.659650548
Short name T241
Test name
Test status
Simulation time 62389062818 ps
CPU time 1702.68 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:23:21 PM PDT 24
Peak memory 273780 kb
Host smart-cfdd5958-71b0-41d1-bbd6-d174cd3526a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659650548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.659650548
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.160457094
Short name T81
Test name
Test status
Simulation time 93123714022 ps
CPU time 1875.47 seconds
Started Jul 09 04:54:36 PM PDT 24
Finished Jul 09 05:25:53 PM PDT 24
Peak memory 298484 kb
Host smart-299787da-9c5f-4244-a775-968f265a6307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160457094 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.160457094
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2865747468
Short name T12
Test name
Test status
Simulation time 179917350203 ps
CPU time 437.44 seconds
Started Jul 09 04:54:55 PM PDT 24
Finished Jul 09 05:02:13 PM PDT 24
Peak memory 256040 kb
Host smart-97b82ed7-e79c-47a7-b1a0-cefe24f34a08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865747468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2865747468
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1519342683
Short name T166
Test name
Test status
Simulation time 15071123727 ps
CPU time 999.12 seconds
Started Jul 09 04:53:53 PM PDT 24
Finished Jul 09 05:10:32 PM PDT 24
Peak memory 265424 kb
Host smart-c53890b2-577f-43f6-ad1d-60b7fa1b8221
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519342683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1519342683
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4184066561
Short name T304
Test name
Test status
Simulation time 83608050179 ps
CPU time 422.3 seconds
Started Jul 09 04:55:10 PM PDT 24
Finished Jul 09 05:02:13 PM PDT 24
Peak memory 255784 kb
Host smart-efa95b54-a754-4a89-aded-13babac286ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184066561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4184066561
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3403160409
Short name T117
Test name
Test status
Simulation time 30302292908 ps
CPU time 875.87 seconds
Started Jul 09 04:55:22 PM PDT 24
Finished Jul 09 05:09:58 PM PDT 24
Peak memory 265680 kb
Host smart-86a05d02-89eb-425f-a317-ede7540f26b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403160409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3403160409
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.360825583
Short name T148
Test name
Test status
Simulation time 9335721400 ps
CPU time 520.81 seconds
Started Jul 09 04:53:48 PM PDT 24
Finished Jul 09 05:02:29 PM PDT 24
Peak memory 265200 kb
Host smart-c394f99e-a2fd-4d72-8287-a913e8df8756
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360825583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.360825583
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.154122060
Short name T314
Test name
Test status
Simulation time 38311891644 ps
CPU time 2166.84 seconds
Started Jul 09 04:54:59 PM PDT 24
Finished Jul 09 05:31:07 PM PDT 24
Peak memory 290220 kb
Host smart-98e39da2-960a-4280-98bc-1a4528270b78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154122060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.154122060
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3248609582
Short name T139
Test name
Test status
Simulation time 12558541761 ps
CPU time 989.53 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 05:10:39 PM PDT 24
Peak memory 265268 kb
Host smart-7acb38a7-ad4b-484a-ab7d-f9fe153fd425
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248609582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3248609582
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.40161227
Short name T255
Test name
Test status
Simulation time 11809001335 ps
CPU time 462.68 seconds
Started Jul 09 04:54:58 PM PDT 24
Finished Jul 09 05:02:43 PM PDT 24
Peak memory 249032 kb
Host smart-818e6c3e-50a5-42d0-92f3-38a2028c9973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40161227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.40161227
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2520224227
Short name T319
Test name
Test status
Simulation time 164971629978 ps
CPU time 2319.96 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 05:34:55 PM PDT 24
Peak memory 283692 kb
Host smart-4615826d-f238-4897-8a83-c033ce3b43de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520224227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2520224227
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1366523016
Short name T9
Test name
Test status
Simulation time 37888882627 ps
CPU time 2379.61 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 05:33:54 PM PDT 24
Peak memory 289876 kb
Host smart-94a9d59d-2d83-442b-a4af-f53c8be4ad20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366523016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1366523016
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3897398649
Short name T62
Test name
Test status
Simulation time 46689600623 ps
CPU time 2619.83 seconds
Started Jul 09 04:55:41 PM PDT 24
Finished Jul 09 05:39:21 PM PDT 24
Peak memory 290068 kb
Host smart-e6be2b6c-5f63-44d4-98c5-9238d104a12d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897398649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3897398649
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3098486682
Short name T711
Test name
Test status
Simulation time 15596018 ps
CPU time 1.6 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:53:58 PM PDT 24
Peak memory 237468 kb
Host smart-a36a7800-efc1-4542-84d9-a5f77ae94713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3098486682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3098486682
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.302430655
Short name T11
Test name
Test status
Simulation time 34460147760 ps
CPU time 337.41 seconds
Started Jul 09 04:55:38 PM PDT 24
Finished Jul 09 05:01:16 PM PDT 24
Peak memory 249240 kb
Host smart-e14434d1-f332-4919-9487-cdc32707b04b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302430655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.302430655
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4210308847
Short name T58
Test name
Test status
Simulation time 108929765103 ps
CPU time 1231.76 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 05:16:23 PM PDT 24
Peak memory 273852 kb
Host smart-a519f291-927c-494c-a84b-ef1e1f6ed2c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210308847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4210308847
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1072829452
Short name T251
Test name
Test status
Simulation time 3391090548 ps
CPU time 40.18 seconds
Started Jul 09 04:54:45 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 249324 kb
Host smart-20b20ebb-87a5-4d46-ad5a-86a8df53a121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10728
29452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1072829452
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.95452938
Short name T158
Test name
Test status
Simulation time 18549580599 ps
CPU time 355.82 seconds
Started Jul 09 04:53:42 PM PDT 24
Finished Jul 09 04:59:39 PM PDT 24
Peak memory 264324 kb
Host smart-4f8db1d9-7cb9-4578-9052-92a09bb27b4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95452938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors
.95452938
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1289129886
Short name T162
Test name
Test status
Simulation time 23121379323 ps
CPU time 975.33 seconds
Started Jul 09 04:53:36 PM PDT 24
Finished Jul 09 05:09:52 PM PDT 24
Peak memory 273432 kb
Host smart-bcfacc78-f287-49ee-8fa1-b1d2d683567e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289129886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1289129886
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3129263084
Short name T307
Test name
Test status
Simulation time 33735834940 ps
CPU time 355.12 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 05:00:07 PM PDT 24
Peak memory 249104 kb
Host smart-8ccf6915-746b-47ff-a75c-e2d05523d36c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129263084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3129263084
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3535309617
Short name T222
Test name
Test status
Simulation time 14645144605 ps
CPU time 1274.52 seconds
Started Jul 09 04:54:37 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 289596 kb
Host smart-88889caa-a0e4-499c-903d-7d11cb0b74dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535309617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3535309617
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2357898751
Short name T233
Test name
Test status
Simulation time 56712656 ps
CPU time 3.36 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:12 PM PDT 24
Peak memory 249396 kb
Host smart-16258cdc-8fc5-40ae-8bd9-bc40ce774f4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2357898751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2357898751
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3814150911
Short name T30
Test name
Test status
Simulation time 184093937 ps
CPU time 4.2 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 04:54:17 PM PDT 24
Peak memory 249400 kb
Host smart-1c25c410-79a8-43b2-9a93-1f00d6d25d75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3814150911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3814150911
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.310390552
Short name T226
Test name
Test status
Simulation time 23077464 ps
CPU time 2.51 seconds
Started Jul 09 04:54:26 PM PDT 24
Finished Jul 09 04:54:29 PM PDT 24
Peak memory 249396 kb
Host smart-b75bbc9f-74af-450d-b1e3-729b9d17bb8c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=310390552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.310390552
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1826533695
Short name T232
Test name
Test status
Simulation time 116165950 ps
CPU time 3 seconds
Started Jul 09 04:54:38 PM PDT 24
Finished Jul 09 04:54:42 PM PDT 24
Peak memory 249484 kb
Host smart-6217956b-2087-4b9f-853e-16743de48970
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1826533695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1826533695
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4043202783
Short name T33
Test name
Test status
Simulation time 16736056838 ps
CPU time 1583.73 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 05:22:35 PM PDT 24
Peak memory 288528 kb
Host smart-9c8c3e80-6bb8-4c12-959c-3438c80c3090
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043202783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4043202783
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1716592017
Short name T285
Test name
Test status
Simulation time 277402898124 ps
CPU time 5498.05 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 06:26:37 PM PDT 24
Peak memory 316072 kb
Host smart-6ad16fb6-f292-4555-8f15-7326576a57a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716592017 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1716592017
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1894740990
Short name T286
Test name
Test status
Simulation time 3583070367 ps
CPU time 59.08 seconds
Started Jul 09 04:54:14 PM PDT 24
Finished Jul 09 04:55:14 PM PDT 24
Peak memory 249352 kb
Host smart-0bbcadab-1e55-4fea-8304-fb3151545df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18947
40990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1894740990
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.231733152
Short name T101
Test name
Test status
Simulation time 75049641223 ps
CPU time 1433.13 seconds
Started Jul 09 04:54:46 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 287704 kb
Host smart-ad841268-dbcf-42d2-ba26-80ba8e30ff0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231733152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.231733152
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1761436751
Short name T279
Test name
Test status
Simulation time 2029878349 ps
CPU time 62.52 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 04:55:57 PM PDT 24
Peak memory 257376 kb
Host smart-2c42234b-d433-4934-919a-50ab52946031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17614
36751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1761436751
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3902244395
Short name T108
Test name
Test status
Simulation time 87668553037 ps
CPU time 2497.35 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 05:36:47 PM PDT 24
Peak memory 289536 kb
Host smart-f3de3877-dd21-4fae-89ad-24d42d188054
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902244395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3902244395
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3159413505
Short name T7
Test name
Test status
Simulation time 27419397571 ps
CPU time 1815.5 seconds
Started Jul 09 04:55:32 PM PDT 24
Finished Jul 09 05:25:48 PM PDT 24
Peak memory 283012 kb
Host smart-d9037aae-696d-4236-a6f5-8068cecc504d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159413505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3159413505
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2161580270
Short name T106
Test name
Test status
Simulation time 126071715330 ps
CPU time 5790.64 seconds
Started Jul 09 04:54:24 PM PDT 24
Finished Jul 09 06:30:56 PM PDT 24
Peak memory 322432 kb
Host smart-8e15ea8d-f5b4-4372-9eea-f79c48e1d5e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161580270 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2161580270
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2603460078
Short name T178
Test name
Test status
Simulation time 74094769 ps
CPU time 3.53 seconds
Started Jul 09 04:54:01 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 237480 kb
Host smart-086e7452-20a9-4917-b55f-0668169035af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2603460078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2603460078
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.100903956
Short name T154
Test name
Test status
Simulation time 1366936149 ps
CPU time 101.07 seconds
Started Jul 09 04:53:33 PM PDT 24
Finished Jul 09 04:55:15 PM PDT 24
Peak memory 267560 kb
Host smart-a9f27eb0-13ea-4e2a-92e6-c9a8bce3d9e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100903956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.100903956
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2171585161
Short name T176
Test name
Test status
Simulation time 889890839 ps
CPU time 3.91 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:53:40 PM PDT 24
Peak memory 237896 kb
Host smart-30c82123-1702-4a29-9ca8-50444d9e03de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2171585161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2171585161
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2638017477
Short name T135
Test name
Test status
Simulation time 4415469260 ps
CPU time 309.66 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:59:06 PM PDT 24
Peak memory 272744 kb
Host smart-6dabbcf2-69a7-4bfb-9267-9b7a31371389
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2638017477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2638017477
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1535211020
Short name T155
Test name
Test status
Simulation time 15110166209 ps
CPU time 476.89 seconds
Started Jul 09 04:53:51 PM PDT 24
Finished Jul 09 05:01:49 PM PDT 24
Peak memory 265292 kb
Host smart-a8e2722f-4061-409e-ac34-8bc47eaf253c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535211020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1535211020
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1177392763
Short name T156
Test name
Test status
Simulation time 12181393137 ps
CPU time 543.61 seconds
Started Jul 09 04:53:53 PM PDT 24
Finished Jul 09 05:02:57 PM PDT 24
Peak memory 265292 kb
Host smart-aee8959d-e386-4046-b13f-43bb40ee58c0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177392763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1177392763
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1645325195
Short name T320
Test name
Test status
Simulation time 32070707448 ps
CPU time 1944.29 seconds
Started Jul 09 04:54:30 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 282184 kb
Host smart-02f46c9e-b6fc-43a1-804d-1a3784bf6e53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645325195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1645325195
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3645048059
Short name T119
Test name
Test status
Simulation time 45960355468 ps
CPU time 509.16 seconds
Started Jul 09 04:54:26 PM PDT 24
Finished Jul 09 05:02:56 PM PDT 24
Peak memory 249236 kb
Host smart-d70c5f65-9486-4226-ac12-f68b59d5236e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645048059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3645048059
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1320718990
Short name T283
Test name
Test status
Simulation time 3184949913 ps
CPU time 54.26 seconds
Started Jul 09 04:54:27 PM PDT 24
Finished Jul 09 04:55:21 PM PDT 24
Peak memory 256536 kb
Host smart-edd608cf-140d-413b-a438-521de935e312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
18990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1320718990
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.216451534
Short name T260
Test name
Test status
Simulation time 372035866186 ps
CPU time 2834.48 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 285428 kb
Host smart-e8d82b9c-5df5-4983-859f-52bed3e1de4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216451534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.216451534
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2391129527
Short name T257
Test name
Test status
Simulation time 3873677825 ps
CPU time 60.62 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 04:55:36 PM PDT 24
Peak memory 256744 kb
Host smart-8a4d3955-3f2a-4c8e-b554-48a811dc318b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23911
29527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2391129527
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2526280319
Short name T110
Test name
Test status
Simulation time 2643764245 ps
CPU time 48.25 seconds
Started Jul 09 04:54:41 PM PDT 24
Finished Jul 09 04:55:30 PM PDT 24
Peak memory 249068 kb
Host smart-d68322a0-84de-4fbd-9384-3d848f0775bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25262
80319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2526280319
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1258571549
Short name T265
Test name
Test status
Simulation time 120057541806 ps
CPU time 3271.95 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 05:49:16 PM PDT 24
Peak memory 289428 kb
Host smart-02f9d790-2d63-4cc7-ae79-bfa1f05f8d78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258571549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1258571549
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2670097054
Short name T109
Test name
Test status
Simulation time 280720517 ps
CPU time 9.98 seconds
Started Jul 09 04:54:52 PM PDT 24
Finished Jul 09 04:55:04 PM PDT 24
Peak memory 248580 kb
Host smart-a2fff27e-775c-40b4-9d8b-2674135ed5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26700
97054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2670097054
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2075141478
Short name T247
Test name
Test status
Simulation time 43661143593 ps
CPU time 2481.03 seconds
Started Jul 09 04:54:59 PM PDT 24
Finished Jul 09 05:36:22 PM PDT 24
Peak memory 286440 kb
Host smart-4b3de332-b5ca-4df3-a597-3b3365e42b9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075141478 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2075141478
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.586253576
Short name T63
Test name
Test status
Simulation time 14803072801 ps
CPU time 1531.57 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 05:19:44 PM PDT 24
Peak memory 290236 kb
Host smart-bed6cef0-5941-4b10-8218-012831f11c6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586253576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.586253576
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.412706241
Short name T105
Test name
Test status
Simulation time 38582982722 ps
CPU time 4136.73 seconds
Started Jul 09 04:55:16 PM PDT 24
Finished Jul 09 06:04:14 PM PDT 24
Peak memory 336996 kb
Host smart-acd6ca31-61d0-4fca-98c0-38adf2e2ab42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412706241 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.412706241
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3941372640
Short name T278
Test name
Test status
Simulation time 421218825 ps
CPU time 8.1 seconds
Started Jul 09 04:55:24 PM PDT 24
Finished Jul 09 04:55:33 PM PDT 24
Peak memory 248368 kb
Host smart-ad766dce-2437-4709-8c01-a8f91ebed0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39413
72640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3941372640
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2069380611
Short name T289
Test name
Test status
Simulation time 123015248 ps
CPU time 5.67 seconds
Started Jul 09 04:55:31 PM PDT 24
Finished Jul 09 04:55:37 PM PDT 24
Peak memory 240996 kb
Host smart-5bd04ad8-92af-4afb-82bf-6ff2479062b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
80611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2069380611
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1415356401
Short name T277
Test name
Test status
Simulation time 2864965457 ps
CPU time 45.35 seconds
Started Jul 09 04:55:50 PM PDT 24
Finished Jul 09 04:56:35 PM PDT 24
Peak memory 248776 kb
Host smart-9819170a-1272-4f8f-811f-07812a3b3f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
56401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1415356401
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1040948889
Short name T209
Test name
Test status
Simulation time 159898428415 ps
CPU time 7608.01 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 07:02:40 PM PDT 24
Peak memory 364080 kb
Host smart-a5543c91-2a03-4cea-829b-25c5cb44e670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040948889 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1040948889
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3837339145
Short name T253
Test name
Test status
Simulation time 6515677921 ps
CPU time 62.01 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 04:57:17 PM PDT 24
Peak memory 249192 kb
Host smart-8efc8856-86ba-494f-83e6-de82140c3f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38373
39145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3837339145
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2178311183
Short name T160
Test name
Test status
Simulation time 2322518447 ps
CPU time 164.89 seconds
Started Jul 09 04:53:48 PM PDT 24
Finished Jul 09 04:56:33 PM PDT 24
Peak memory 257152 kb
Host smart-88e207c3-1273-477a-8d03-38e21a18025f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2178311183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2178311183
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3830624569
Short name T136
Test name
Test status
Simulation time 1723361540 ps
CPU time 107.2 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:55:44 PM PDT 24
Peak memory 265244 kb
Host smart-4a738a8c-9aa6-476f-a1f2-5a941d50c8e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3830624569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3830624569
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.381347278
Short name T174
Test name
Test status
Simulation time 38547361 ps
CPU time 3.33 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:53:59 PM PDT 24
Peak memory 237660 kb
Host smart-0a26440e-6aaf-4fee-874c-8b1d47cf97a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=381347278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.381347278
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3501208208
Short name T168
Test name
Test status
Simulation time 70388816 ps
CPU time 2.18 seconds
Started Jul 09 04:53:44 PM PDT 24
Finished Jul 09 04:53:47 PM PDT 24
Peak memory 237304 kb
Host smart-7f8e14fa-0af5-4e49-b11e-90dc2c91c753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3501208208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3501208208
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3712131602
Short name T137
Test name
Test status
Simulation time 14279933793 ps
CPU time 313.67 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:59:09 PM PDT 24
Peak memory 266312 kb
Host smart-c539fe2e-10a5-4495-8c49-22703c613da6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3712131602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3712131602
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.201942080
Short name T180
Test name
Test status
Simulation time 36742661 ps
CPU time 2.83 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:53:59 PM PDT 24
Peak memory 236456 kb
Host smart-1951ecbb-f358-4d0d-9858-012205551be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=201942080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.201942080
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1338784253
Short name T175
Test name
Test status
Simulation time 61805444 ps
CPU time 2.82 seconds
Started Jul 09 04:54:00 PM PDT 24
Finished Jul 09 04:54:04 PM PDT 24
Peak memory 237404 kb
Host smart-c2b0bec0-2890-4467-a707-8bc18faf078e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1338784253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1338784253
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2210070466
Short name T181
Test name
Test status
Simulation time 211093964 ps
CPU time 4.72 seconds
Started Jul 09 04:53:43 PM PDT 24
Finished Jul 09 04:53:48 PM PDT 24
Peak memory 237692 kb
Host smart-24bf75ec-976b-4470-ab75-c45b4db8c34d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2210070466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2210070466
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1460400270
Short name T157
Test name
Test status
Simulation time 4099505033 ps
CPU time 226.15 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:57:28 PM PDT 24
Peak memory 265276 kb
Host smart-aa89261b-f0bc-4bd3-8c9d-04d3a2e1bb8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1460400270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1460400270
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2064452196
Short name T177
Test name
Test status
Simulation time 974945053 ps
CPU time 24.24 seconds
Started Jul 09 04:53:49 PM PDT 24
Finished Jul 09 04:54:14 PM PDT 24
Peak memory 245904 kb
Host smart-3b9d872e-83d9-4d42-8ca9-b26bf04ba172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2064452196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2064452196
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.744636619
Short name T185
Test name
Test status
Simulation time 64669880 ps
CPU time 3.42 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:09 PM PDT 24
Peak memory 237444 kb
Host smart-58d90f5f-d6a0-4b10-a061-0aeef26e2e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=744636619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.744636619
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1937343169
Short name T182
Test name
Test status
Simulation time 31138243 ps
CPU time 2.06 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 04:53:55 PM PDT 24
Peak memory 237444 kb
Host smart-7dbeee25-94f6-49b0-8d22-35a3c83463d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1937343169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1937343169
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3054431602
Short name T188
Test name
Test status
Simulation time 331247953 ps
CPU time 47.8 seconds
Started Jul 09 04:54:04 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 240372 kb
Host smart-1385c991-3d81-44aa-b7dd-0ede1e7b82e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3054431602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3054431602
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2990250743
Short name T187
Test name
Test status
Simulation time 179922206 ps
CPU time 2.62 seconds
Started Jul 09 04:53:38 PM PDT 24
Finished Jul 09 04:53:42 PM PDT 24
Peak memory 236468 kb
Host smart-9eee7ca9-6491-4a25-83eb-d4ae48036ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2990250743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2990250743
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1586815600
Short name T186
Test name
Test status
Simulation time 22145619 ps
CPU time 2.73 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:53:43 PM PDT 24
Peak memory 238468 kb
Host smart-baf6e596-898a-4491-91ba-976d6c0d2741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1586815600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1586815600
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.324239795
Short name T32
Test name
Test status
Simulation time 82022689891 ps
CPU time 5043.63 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 06:18:54 PM PDT 24
Peak memory 298536 kb
Host smart-901b9b09-b333-49f1-b313-2b60d4766756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324239795 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.324239795
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3545694422
Short name T737
Test name
Test status
Simulation time 6767265710 ps
CPU time 129.31 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:55:45 PM PDT 24
Peak memory 240488 kb
Host smart-2e7190ba-7e62-4d89-8c6e-b67f20c81df8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3545694422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3545694422
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.783332239
Short name T813
Test name
Test status
Simulation time 4456696721 ps
CPU time 263.38 seconds
Started Jul 09 04:53:32 PM PDT 24
Finished Jul 09 04:57:56 PM PDT 24
Peak memory 240456 kb
Host smart-f8b819e5-61f6-4771-b275-c91f0a90507a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=783332239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.783332239
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3151015816
Short name T776
Test name
Test status
Simulation time 75176865 ps
CPU time 6.92 seconds
Started Jul 09 04:53:30 PM PDT 24
Finished Jul 09 04:53:38 PM PDT 24
Peak memory 240428 kb
Host smart-3e060387-39f5-4067-a12a-15f630c7439f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3151015816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3151015816
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.560459519
Short name T814
Test name
Test status
Simulation time 421870182 ps
CPU time 9.36 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:53:45 PM PDT 24
Peak memory 239660 kb
Host smart-5dedd88b-6201-4ed6-b26d-1d9224c28557
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560459519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.560459519
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.763400228
Short name T816
Test name
Test status
Simulation time 65379703 ps
CPU time 5.4 seconds
Started Jul 09 04:53:34 PM PDT 24
Finished Jul 09 04:53:40 PM PDT 24
Peak memory 237420 kb
Host smart-2b75fe7b-0ed3-4b09-bf37-56d981a9ff36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=763400228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.763400228
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.986087164
Short name T809
Test name
Test status
Simulation time 13921113 ps
CPU time 1.47 seconds
Started Jul 09 04:53:32 PM PDT 24
Finished Jul 09 04:53:34 PM PDT 24
Peak memory 237468 kb
Host smart-1f8bcbbe-35b1-49c1-b632-0641bb078bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=986087164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.986087164
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3465168371
Short name T202
Test name
Test status
Simulation time 1788159853 ps
CPU time 22.73 seconds
Started Jul 09 04:53:36 PM PDT 24
Finished Jul 09 04:54:00 PM PDT 24
Peak memory 245656 kb
Host smart-cdbd048b-2832-4fc9-9965-8beb1ef3ccb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3465168371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3465168371
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2349614085
Short name T713
Test name
Test status
Simulation time 360925111 ps
CPU time 24.19 seconds
Started Jul 09 04:53:32 PM PDT 24
Finished Jul 09 04:53:56 PM PDT 24
Peak memory 255576 kb
Host smart-1c11a165-0adb-46d7-96c6-e6166f76fa0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2349614085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2349614085
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3368462675
Short name T341
Test name
Test status
Simulation time 1125215396 ps
CPU time 163.22 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:56:24 PM PDT 24
Peak memory 240428 kb
Host smart-58ad9fec-a97b-4933-9cb5-ee1588bb5315
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3368462675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3368462675
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2323460015
Short name T757
Test name
Test status
Simulation time 22873140918 ps
CPU time 376.24 seconds
Started Jul 09 04:54:12 PM PDT 24
Finished Jul 09 05:00:29 PM PDT 24
Peak memory 236512 kb
Host smart-1619e238-a791-4621-b1b8-6ffe28307007
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2323460015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2323460015
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2292633618
Short name T731
Test name
Test status
Simulation time 73752646 ps
CPU time 6.85 seconds
Started Jul 09 04:53:37 PM PDT 24
Finished Jul 09 04:53:44 PM PDT 24
Peak memory 248592 kb
Host smart-f1772109-5ea9-48bb-9eca-23df2a5c5113
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2292633618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2292633618
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2860708773
Short name T739
Test name
Test status
Simulation time 232666397 ps
CPU time 9.7 seconds
Started Jul 09 04:53:36 PM PDT 24
Finished Jul 09 04:53:47 PM PDT 24
Peak memory 238248 kb
Host smart-bde60922-67b5-4d92-9282-9c0d7e706a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860708773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2860708773
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4182118111
Short name T802
Test name
Test status
Simulation time 19770843 ps
CPU time 3.04 seconds
Started Jul 09 04:53:46 PM PDT 24
Finished Jul 09 04:53:50 PM PDT 24
Peak memory 240064 kb
Host smart-8ef95c5d-7cf9-4de0-8eec-f793eca9f5c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4182118111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4182118111
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3311612660
Short name T710
Test name
Test status
Simulation time 10507069 ps
CPU time 1.38 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:53:37 PM PDT 24
Peak memory 235444 kb
Host smart-5cdd3fe2-cb5d-414a-8678-6bc1efa78af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3311612660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3311612660
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3069305654
Short name T786
Test name
Test status
Simulation time 316942052 ps
CPU time 10.26 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:53:46 PM PDT 24
Peak memory 244648 kb
Host smart-1ebe719e-a0dc-41e6-b429-b8554691b9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3069305654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3069305654
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3671214251
Short name T134
Test name
Test status
Simulation time 889418664 ps
CPU time 92.26 seconds
Started Jul 09 04:53:37 PM PDT 24
Finished Jul 09 04:55:09 PM PDT 24
Peak memory 265128 kb
Host smart-9b306983-316c-43d9-bc18-e24d5310df83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3671214251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3671214251
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3057635683
Short name T805
Test name
Test status
Simulation time 213258645 ps
CPU time 14.7 seconds
Started Jul 09 04:53:38 PM PDT 24
Finished Jul 09 04:53:53 PM PDT 24
Peak memory 253996 kb
Host smart-be8fd763-3bce-4896-9b1c-7e090cdae64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3057635683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3057635683
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3099539259
Short name T170
Test name
Test status
Simulation time 168986528 ps
CPU time 2.36 seconds
Started Jul 09 04:53:34 PM PDT 24
Finished Jul 09 04:53:37 PM PDT 24
Peak memory 237312 kb
Host smart-3a47315a-5ca8-4804-93b9-61ceb34fa3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3099539259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3099539259
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2065736384
Short name T729
Test name
Test status
Simulation time 1180032267 ps
CPU time 14.1 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 243660 kb
Host smart-bf2a870d-d7e0-4b2d-8d1a-054a1c1784d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065736384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2065736384
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1215091601
Short name T210
Test name
Test status
Simulation time 299027378 ps
CPU time 4.51 seconds
Started Jul 09 04:53:51 PM PDT 24
Finished Jul 09 04:53:56 PM PDT 24
Peak memory 240420 kb
Host smart-fcec7699-9664-4b32-862d-6e22132d15f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1215091601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1215091601
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3254613811
Short name T781
Test name
Test status
Simulation time 8629244 ps
CPU time 1.42 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:53:56 PM PDT 24
Peak memory 236464 kb
Host smart-de1335ec-6c85-4366-84f9-e5ee8077e7bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3254613811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3254613811
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.170782215
Short name T752
Test name
Test status
Simulation time 2208017252 ps
CPU time 33.49 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:54:29 PM PDT 24
Peak memory 244704 kb
Host smart-28f62c8a-3999-4c74-be12-c7d1e43d517b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=170782215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.170782215
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1243719411
Short name T704
Test name
Test status
Simulation time 155661262 ps
CPU time 10.5 seconds
Started Jul 09 04:53:53 PM PDT 24
Finished Jul 09 04:54:04 PM PDT 24
Peak memory 255028 kb
Host smart-7a1c220c-5c75-4a61-af80-6a8c13e58fde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1243719411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1243719411
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2678513643
Short name T819
Test name
Test status
Simulation time 283655065 ps
CPU time 10.29 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:54:04 PM PDT 24
Peak memory 256740 kb
Host smart-5d82c2e1-89bd-4da1-9586-dd268b1832d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678513643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2678513643
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2035258128
Short name T777
Test name
Test status
Simulation time 32805975 ps
CPU time 5.57 seconds
Started Jul 09 04:53:53 PM PDT 24
Finished Jul 09 04:53:59 PM PDT 24
Peak memory 237416 kb
Host smart-783cb2b7-9e03-4058-8076-d4e09033a42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2035258128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2035258128
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3935523165
Short name T817
Test name
Test status
Simulation time 31801070 ps
CPU time 1.52 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:07 PM PDT 24
Peak memory 237452 kb
Host smart-f2635f91-c688-44d1-86c0-4ad1e013bda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3935523165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3935523165
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4048279084
Short name T736
Test name
Test status
Simulation time 534174982 ps
CPU time 38.73 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:54:34 PM PDT 24
Peak memory 248620 kb
Host smart-6ec23aaf-d036-452f-b9b1-e5767dc45f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048279084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4048279084
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1492005649
Short name T143
Test name
Test status
Simulation time 40028195294 ps
CPU time 789.37 seconds
Started Jul 09 04:53:58 PM PDT 24
Finished Jul 09 05:07:09 PM PDT 24
Peak memory 271084 kb
Host smart-a2c31c94-5b4a-4108-b53c-304b4f94c979
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492005649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1492005649
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.370264533
Short name T826
Test name
Test status
Simulation time 206511711 ps
CPU time 7.79 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 04:54:01 PM PDT 24
Peak memory 252116 kb
Host smart-6456d6bc-23d2-48cf-8b24-f6b745be2f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=370264533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.370264533
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.829570193
Short name T340
Test name
Test status
Simulation time 33142282 ps
CPU time 5.85 seconds
Started Jul 09 04:53:59 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 240976 kb
Host smart-4beee820-e50d-44ff-8fe6-3339ea99f0da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829570193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.829570193
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2367055172
Short name T211
Test name
Test status
Simulation time 132299985 ps
CPU time 5.03 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:54:00 PM PDT 24
Peak memory 240420 kb
Host smart-5ef09854-60c9-45c5-984f-f068a1b40f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2367055172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2367055172
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1860022615
Short name T785
Test name
Test status
Simulation time 471990380 ps
CPU time 12.13 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 245648 kb
Host smart-22ebf658-65c8-429e-a0b3-00ef36db0af9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1860022615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1860022615
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2714099018
Short name T783
Test name
Test status
Simulation time 289523522 ps
CPU time 10.55 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 04:54:03 PM PDT 24
Peak memory 248604 kb
Host smart-20067089-b8b8-46db-99a2-17e12a9ce9ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2714099018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2714099018
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.223497320
Short name T772
Test name
Test status
Simulation time 136789659 ps
CPU time 11.73 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 240472 kb
Host smart-13ddd37a-2bf2-46e5-807e-108c2191d0ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223497320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.223497320
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1449208336
Short name T343
Test name
Test status
Simulation time 41695834 ps
CPU time 6.69 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:54:02 PM PDT 24
Peak memory 237432 kb
Host smart-2d5163d1-9ee4-4b83-b6d3-a42fd879965e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1449208336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1449208336
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1120827059
Short name T332
Test name
Test status
Simulation time 22810219 ps
CPU time 1.45 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:53:56 PM PDT 24
Peak memory 237424 kb
Host smart-38df0af6-0ef8-4e6f-a145-9650d2857271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1120827059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1120827059
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1179305416
Short name T721
Test name
Test status
Simulation time 527387842 ps
CPU time 41.09 seconds
Started Jul 09 04:53:58 PM PDT 24
Finished Jul 09 04:54:40 PM PDT 24
Peak memory 245572 kb
Host smart-e2f6b68c-13a5-41aa-93cd-c1e37443cc0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1179305416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1179305416
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1477538500
Short name T145
Test name
Test status
Simulation time 1568164864 ps
CPU time 98.85 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:55:36 PM PDT 24
Peak memory 265260 kb
Host smart-3f2408f6-7d0a-4665-9e8e-433a6d1f34fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1477538500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1477538500
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3258175923
Short name T821
Test name
Test status
Simulation time 216541939 ps
CPU time 9.2 seconds
Started Jul 09 04:53:59 PM PDT 24
Finished Jul 09 04:54:09 PM PDT 24
Peak memory 248420 kb
Host smart-28fc20b2-0246-421b-8a6e-cc890fe06632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3258175923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3258175923
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3857783751
Short name T815
Test name
Test status
Simulation time 1221810198 ps
CPU time 25.43 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:54:20 PM PDT 24
Peak memory 240320 kb
Host smart-c3a4462a-e887-45aa-9da6-dd6e063f276a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3857783751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3857783751
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.876891875
Short name T758
Test name
Test status
Simulation time 135876660 ps
CPU time 5.81 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 04:54:04 PM PDT 24
Peak memory 240472 kb
Host smart-72842406-eec0-4232-80f4-9e6d14f2ce53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876891875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.876891875
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1729009488
Short name T740
Test name
Test status
Simulation time 93185591 ps
CPU time 8.1 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 240336 kb
Host smart-a36b5667-256d-4059-96aa-929a3fec2d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1729009488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1729009488
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3212106109
Short name T804
Test name
Test status
Simulation time 17797842 ps
CPU time 1.93 seconds
Started Jul 09 04:53:58 PM PDT 24
Finished Jul 09 04:54:02 PM PDT 24
Peak memory 237456 kb
Host smart-c719e71a-1525-4cda-bf91-babeadc65047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3212106109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3212106109
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2827904388
Short name T720
Test name
Test status
Simulation time 171690228 ps
CPU time 23.66 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 245672 kb
Host smart-c1183e58-c754-48c3-b3c2-38b1399f1295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2827904388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2827904388
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.291361708
Short name T146
Test name
Test status
Simulation time 6347861588 ps
CPU time 535.54 seconds
Started Jul 09 04:53:52 PM PDT 24
Finished Jul 09 05:02:48 PM PDT 24
Peak memory 265508 kb
Host smart-9fa70324-2e1b-44fd-9d7c-c32570d7a2b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291361708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.291361708
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.13694739
Short name T763
Test name
Test status
Simulation time 236278138 ps
CPU time 13.11 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:19 PM PDT 24
Peak memory 256664 kb
Host smart-3533bb27-9d97-41e0-a1b3-18a3510e3ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=13694739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.13694739
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3936389474
Short name T179
Test name
Test status
Simulation time 93077146 ps
CPU time 3.87 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 04:54:02 PM PDT 24
Peak memory 237456 kb
Host smart-ea4b7b46-00b9-4e78-a681-086cb58797d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3936389474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3936389474
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2798415158
Short name T184
Test name
Test status
Simulation time 142908491 ps
CPU time 10.83 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 239140 kb
Host smart-b9adb16a-20e5-4358-b1c1-d8972cc72ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798415158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2798415158
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1372395167
Short name T338
Test name
Test status
Simulation time 69436160 ps
CPU time 5.27 seconds
Started Jul 09 04:53:55 PM PDT 24
Finished Jul 09 04:54:00 PM PDT 24
Peak memory 237356 kb
Host smart-6edc1cfa-bdfb-40a5-94f2-eeda123d4e47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1372395167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1372395167
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.938985595
Short name T732
Test name
Test status
Simulation time 12877406 ps
CPU time 1.85 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 04:53:58 PM PDT 24
Peak memory 237572 kb
Host smart-eb324d81-27e7-4155-9956-3718c7db9379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=938985595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.938985595
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2942318869
Short name T820
Test name
Test status
Simulation time 2065604557 ps
CPU time 34.53 seconds
Started Jul 09 04:53:58 PM PDT 24
Finished Jul 09 04:54:33 PM PDT 24
Peak memory 244720 kb
Host smart-1e03ac99-4b4d-4d47-977a-7b3af29d3d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2942318869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2942318869
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2618961609
Short name T708
Test name
Test status
Simulation time 682268789 ps
CPU time 23.38 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 255112 kb
Host smart-5143ead6-05a5-4e91-86da-dea6322d0217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2618961609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2618961609
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3912439413
Short name T790
Test name
Test status
Simulation time 113439725 ps
CPU time 8.04 seconds
Started Jul 09 04:54:06 PM PDT 24
Finished Jul 09 04:54:15 PM PDT 24
Peak memory 256780 kb
Host smart-cf2dbbb8-af1a-40d7-81f7-b276a04e2a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912439413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3912439413
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2146659682
Short name T342
Test name
Test status
Simulation time 62574560 ps
CPU time 6.8 seconds
Started Jul 09 04:53:58 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 237368 kb
Host smart-8191f038-44b0-483b-b87b-cb33fb734749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2146659682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2146659682
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1061490940
Short name T171
Test name
Test status
Simulation time 11109727 ps
CPU time 1.36 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 04:53:59 PM PDT 24
Peak memory 237416 kb
Host smart-fa2d4b7b-1b1d-405b-966e-fcb96df643ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1061490940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1061490940
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3057198580
Short name T183
Test name
Test status
Simulation time 92855193 ps
CPU time 13.03 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:19 PM PDT 24
Peak memory 245644 kb
Host smart-350103d4-d642-4172-87c0-6069853e7b8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3057198580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3057198580
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4201620552
Short name T163
Test name
Test status
Simulation time 1711695433 ps
CPU time 229.5 seconds
Started Jul 09 04:53:58 PM PDT 24
Finished Jul 09 04:57:48 PM PDT 24
Peak memory 265384 kb
Host smart-75ed8abc-9741-4f5f-bd76-1fa45dfc8d1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4201620552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4201620552
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4119721041
Short name T152
Test name
Test status
Simulation time 6339666868 ps
CPU time 525.24 seconds
Started Jul 09 04:53:56 PM PDT 24
Finished Jul 09 05:02:42 PM PDT 24
Peak memory 268940 kb
Host smart-e108a85e-0a10-43c7-a899-2784412a005f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119721041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4119721041
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2536684096
Short name T735
Test name
Test status
Simulation time 105723572 ps
CPU time 8.62 seconds
Started Jul 09 04:53:57 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 248648 kb
Host smart-080210ec-374e-46b0-84c7-e5f3e8aca8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2536684096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2536684096
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.135041558
Short name T768
Test name
Test status
Simulation time 437585719 ps
CPU time 8.22 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:18 PM PDT 24
Peak memory 240096 kb
Host smart-ce55944d-74ba-49b4-854c-ac090fd8d256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135041558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.135041558
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2714463754
Short name T749
Test name
Test status
Simulation time 374452029 ps
CPU time 6.41 seconds
Started Jul 09 04:53:59 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 240512 kb
Host smart-6898113d-dbf8-451b-b3df-407f0ef1a77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2714463754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2714463754
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3179235017
Short name T333
Test name
Test status
Simulation time 14005316 ps
CPU time 1.27 seconds
Started Jul 09 04:54:07 PM PDT 24
Finished Jul 09 04:54:09 PM PDT 24
Peak memory 237504 kb
Host smart-09e5ff45-5523-4d3d-b955-f71fb0a2c7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3179235017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3179235017
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.610203639
Short name T824
Test name
Test status
Simulation time 570160160 ps
CPU time 22.49 seconds
Started Jul 09 04:54:00 PM PDT 24
Finished Jul 09 04:54:23 PM PDT 24
Peak memory 248728 kb
Host smart-6e09f122-7a87-46ec-9051-6d4e4724c5ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=610203639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.610203639
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.25491461
Short name T164
Test name
Test status
Simulation time 819424751 ps
CPU time 96.94 seconds
Started Jul 09 04:54:07 PM PDT 24
Finished Jul 09 04:55:45 PM PDT 24
Peak memory 265292 kb
Host smart-79559878-05d3-4432-acd0-8a16b7038617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25491461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.25491461
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1207680052
Short name T165
Test name
Test status
Simulation time 8524855818 ps
CPU time 338.85 seconds
Started Jul 09 04:54:00 PM PDT 24
Finished Jul 09 04:59:40 PM PDT 24
Peak memory 270548 kb
Host smart-04c8c50c-c15e-48c2-bbe1-650893605977
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207680052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1207680052
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3136410436
Short name T799
Test name
Test status
Simulation time 1414370513 ps
CPU time 20.27 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:26 PM PDT 24
Peak memory 249648 kb
Host smart-345a350d-71c8-4e2d-b4db-500a0b34cd18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136410436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3136410436
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.997291324
Short name T771
Test name
Test status
Simulation time 952888554 ps
CPU time 8.14 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:14 PM PDT 24
Peak memory 240800 kb
Host smart-82fc0217-b9c9-4deb-8cfe-a4bf0e5c4ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997291324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.997291324
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2922726024
Short name T827
Test name
Test status
Simulation time 20238144 ps
CPU time 4.21 seconds
Started Jul 09 04:54:03 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 237524 kb
Host smart-7a8d6ca4-b27b-4e1b-bc89-7218551f1022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2922726024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2922726024
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2784609084
Short name T716
Test name
Test status
Simulation time 12566862 ps
CPU time 1.63 seconds
Started Jul 09 04:54:01 PM PDT 24
Finished Jul 09 04:54:03 PM PDT 24
Peak memory 237416 kb
Host smart-994407d5-e8f5-4ae0-8165-ac5b47ad5380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2784609084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2784609084
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1299995377
Short name T755
Test name
Test status
Simulation time 832881147 ps
CPU time 26.93 seconds
Started Jul 09 04:54:01 PM PDT 24
Finished Jul 09 04:54:29 PM PDT 24
Peak memory 245660 kb
Host smart-9f17125c-958a-46b9-b468-5df0fe8262cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1299995377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1299995377
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.689521540
Short name T147
Test name
Test status
Simulation time 3233206314 ps
CPU time 209.21 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:57:38 PM PDT 24
Peak memory 265316 kb
Host smart-33b6c282-b130-454f-81c5-d2daa4bddd27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=689521540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.689521540
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1812872503
Short name T792
Test name
Test status
Simulation time 341951887 ps
CPU time 19.06 seconds
Started Jul 09 04:54:00 PM PDT 24
Finished Jul 09 04:54:20 PM PDT 24
Peak memory 248072 kb
Host smart-ff763383-6134-4012-9660-25571d09be92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1812872503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1812872503
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3348202466
Short name T345
Test name
Test status
Simulation time 125614280 ps
CPU time 8.63 seconds
Started Jul 09 04:54:07 PM PDT 24
Finished Jul 09 04:54:16 PM PDT 24
Peak memory 240320 kb
Host smart-299e0b9b-dc0d-4fb4-ba4d-9711f5e786c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348202466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3348202466
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2454779924
Short name T725
Test name
Test status
Simulation time 405109810 ps
CPU time 9.3 seconds
Started Jul 09 04:53:59 PM PDT 24
Finished Jul 09 04:54:10 PM PDT 24
Peak memory 236512 kb
Host smart-9e46418e-2ffa-4bbf-80c1-501b28c899ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2454779924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2454779924
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.732463614
Short name T767
Test name
Test status
Simulation time 37234317 ps
CPU time 1.32 seconds
Started Jul 09 04:54:06 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 236564 kb
Host smart-f1c97ca0-0251-4429-aabb-2e819dfaf8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=732463614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.732463614
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3007620231
Short name T728
Test name
Test status
Simulation time 1822531037 ps
CPU time 24.74 seconds
Started Jul 09 04:54:01 PM PDT 24
Finished Jul 09 04:54:26 PM PDT 24
Peak memory 245608 kb
Host smart-ff183714-f24a-499d-804a-12c149acec09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3007620231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3007620231
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4183252680
Short name T773
Test name
Test status
Simulation time 4480488078 ps
CPU time 29.79 seconds
Started Jul 09 04:54:02 PM PDT 24
Finished Jul 09 04:54:32 PM PDT 24
Peak memory 247964 kb
Host smart-efe4d660-8e55-4cd1-9d48-3042d38844d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4183252680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4183252680
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1603663119
Short name T719
Test name
Test status
Simulation time 3282326395 ps
CPU time 265.74 seconds
Started Jul 09 04:53:38 PM PDT 24
Finished Jul 09 04:58:04 PM PDT 24
Peak memory 240492 kb
Host smart-6f19ca75-bffe-4680-8a10-61b979038a41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1603663119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1603663119
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.341331756
Short name T806
Test name
Test status
Simulation time 2966863298 ps
CPU time 237.15 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:57:33 PM PDT 24
Peak memory 240428 kb
Host smart-061e0fe7-b333-435c-aaf3-621b51c7b56b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=341331756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.341331756
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1823015822
Short name T727
Test name
Test status
Simulation time 73240151 ps
CPU time 6.25 seconds
Started Jul 09 04:53:37 PM PDT 24
Finished Jul 09 04:53:44 PM PDT 24
Peak memory 249004 kb
Host smart-26f25581-776c-4089-b0aa-3efab0606cc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1823015822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1823015822
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3180949124
Short name T730
Test name
Test status
Simulation time 209230904 ps
CPU time 9.62 seconds
Started Jul 09 04:53:36 PM PDT 24
Finished Jul 09 04:53:46 PM PDT 24
Peak memory 252152 kb
Host smart-bf308e04-7dbf-4aa3-b086-cd99b16725d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180949124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3180949124
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2593880369
Short name T200
Test name
Test status
Simulation time 124778108 ps
CPU time 6.02 seconds
Started Jul 09 04:53:33 PM PDT 24
Finished Jul 09 04:53:40 PM PDT 24
Peak memory 237464 kb
Host smart-3f5d12c2-2545-4b5c-abc4-f367499eedc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2593880369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2593880369
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3686904655
Short name T795
Test name
Test status
Simulation time 6178748 ps
CPU time 1.46 seconds
Started Jul 09 04:53:34 PM PDT 24
Finished Jul 09 04:53:36 PM PDT 24
Peak memory 237588 kb
Host smart-0aa72a9f-b04d-4c57-b8de-8ae732f73c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3686904655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3686904655
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2426900709
Short name T714
Test name
Test status
Simulation time 334258922 ps
CPU time 10.93 seconds
Started Jul 09 04:53:36 PM PDT 24
Finished Jul 09 04:53:47 PM PDT 24
Peak memory 240428 kb
Host smart-50ed0bf7-7e6a-48e3-bbaf-2a5fed83158e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2426900709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2426900709
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.602001114
Short name T133
Test name
Test status
Simulation time 17557285059 ps
CPU time 674.81 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 05:04:51 PM PDT 24
Peak memory 273196 kb
Host smart-c3b11199-3533-4726-a699-01e52913779d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602001114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.602001114
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.158982940
Short name T778
Test name
Test status
Simulation time 405605791 ps
CPU time 14.69 seconds
Started Jul 09 04:53:45 PM PDT 24
Finished Jul 09 04:54:01 PM PDT 24
Peak memory 247816 kb
Host smart-7549ec3a-89cc-430b-9954-0dc1ad665dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=158982940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.158982940
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2272910156
Short name T789
Test name
Test status
Simulation time 8047278 ps
CPU time 1.34 seconds
Started Jul 09 04:54:00 PM PDT 24
Finished Jul 09 04:54:02 PM PDT 24
Peak memory 237468 kb
Host smart-e304c8d5-9109-4bf1-a946-2242143de256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2272910156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2272910156
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.973246107
Short name T764
Test name
Test status
Simulation time 20981864 ps
CPU time 1.6 seconds
Started Jul 09 04:54:00 PM PDT 24
Finished Jul 09 04:54:03 PM PDT 24
Peak memory 235456 kb
Host smart-cdfbe027-c92f-4290-929f-670fc598afb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=973246107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.973246107
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3198986537
Short name T173
Test name
Test status
Simulation time 19050795 ps
CPU time 1.4 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 237464 kb
Host smart-b106537d-39d4-4cfe-a43e-b6d052564002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3198986537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3198986537
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.362092495
Short name T335
Test name
Test status
Simulation time 7965696 ps
CPU time 1.45 seconds
Started Jul 09 04:54:02 PM PDT 24
Finished Jul 09 04:54:04 PM PDT 24
Peak memory 236616 kb
Host smart-e620c8bf-b2c6-4b24-9c5a-e9078945de0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=362092495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.362092495
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3374016408
Short name T334
Test name
Test status
Simulation time 12026337 ps
CPU time 1.37 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 236484 kb
Host smart-96e96ced-19dd-4486-a9fc-f475c9523d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3374016408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3374016408
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.580605935
Short name T793
Test name
Test status
Simulation time 30874353 ps
CPU time 1.43 seconds
Started Jul 09 04:54:04 PM PDT 24
Finished Jul 09 04:54:07 PM PDT 24
Peak memory 236508 kb
Host smart-3f24d95f-e133-4fab-9955-d32d82ae5ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580605935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.580605935
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.608180008
Short name T762
Test name
Test status
Simulation time 17663536 ps
CPU time 1.34 seconds
Started Jul 09 04:54:02 PM PDT 24
Finished Jul 09 04:54:04 PM PDT 24
Peak memory 237452 kb
Host smart-7877782a-c810-4fa5-a054-5ca6f440cf0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=608180008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.608180008
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3275402026
Short name T766
Test name
Test status
Simulation time 8437235 ps
CPU time 1.55 seconds
Started Jul 09 04:54:03 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 236616 kb
Host smart-85c52e7e-4996-48c5-adce-4b2cad3b9750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3275402026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3275402026
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.406353268
Short name T750
Test name
Test status
Simulation time 31720466 ps
CPU time 1.41 seconds
Started Jul 09 04:54:09 PM PDT 24
Finished Jul 09 04:54:12 PM PDT 24
Peak memory 236864 kb
Host smart-69471328-acfa-4e7c-abc2-1a453a3b661b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=406353268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.406353268
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2633353793
Short name T754
Test name
Test status
Simulation time 7968337091 ps
CPU time 126.63 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:55:47 PM PDT 24
Peak memory 240452 kb
Host smart-accf8e73-f9a8-48d1-a991-e4c0dfcc8a7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2633353793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2633353793
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2252716406
Short name T346
Test name
Test status
Simulation time 21924387025 ps
CPU time 452.95 seconds
Started Jul 09 04:53:38 PM PDT 24
Finished Jul 09 05:01:12 PM PDT 24
Peak memory 237644 kb
Host smart-3a9e1ce6-d99f-42de-a6a9-b847d93af0bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2252716406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2252716406
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.310725320
Short name T823
Test name
Test status
Simulation time 193105211 ps
CPU time 5.1 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:53:46 PM PDT 24
Peak memory 240368 kb
Host smart-8875a825-05d2-4581-abb0-d5e92f225d25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=310725320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.310725320
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3128634442
Short name T733
Test name
Test status
Simulation time 47185847 ps
CPU time 5.92 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:53:46 PM PDT 24
Peak memory 248632 kb
Host smart-0cbaded8-8273-4b3a-b173-08cb049ef41f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128634442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3128634442
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.319838730
Short name T724
Test name
Test status
Simulation time 60820718 ps
CPU time 4.85 seconds
Started Jul 09 04:53:39 PM PDT 24
Finished Jul 09 04:53:44 PM PDT 24
Peak memory 237388 kb
Host smart-803eecd9-0200-4f2a-b179-e59a2697ab29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=319838730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.319838730
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3085427042
Short name T800
Test name
Test status
Simulation time 12202694 ps
CPU time 1.36 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:53:43 PM PDT 24
Peak memory 237472 kb
Host smart-16ebdf03-daeb-4191-a510-c2f977253a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3085427042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3085427042
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.631276575
Short name T779
Test name
Test status
Simulation time 2686504719 ps
CPU time 21.21 seconds
Started Jul 09 04:53:39 PM PDT 24
Finished Jul 09 04:54:00 PM PDT 24
Peak memory 240448 kb
Host smart-1f3785d7-5961-40d7-82d9-36c2e1a29e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=631276575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.631276575
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3277150696
Short name T161
Test name
Test status
Simulation time 2887631711 ps
CPU time 205.9 seconds
Started Jul 09 04:53:34 PM PDT 24
Finished Jul 09 04:57:00 PM PDT 24
Peak memory 265344 kb
Host smart-12c6f261-4fa6-4b3d-a6dd-8e55bcb0f621
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3277150696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3277150696
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4191828406
Short name T144
Test name
Test status
Simulation time 8865111313 ps
CPU time 298.16 seconds
Started Jul 09 04:53:35 PM PDT 24
Finished Jul 09 04:58:33 PM PDT 24
Peak memory 265196 kb
Host smart-bbc14358-b7a4-43a9-ae3b-1a8319326854
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191828406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4191828406
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3448594533
Short name T705
Test name
Test status
Simulation time 86605946 ps
CPU time 7.69 seconds
Started Jul 09 04:53:38 PM PDT 24
Finished Jul 09 04:53:46 PM PDT 24
Peak memory 251488 kb
Host smart-efcda595-c6de-4537-a4df-8b4abb400b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3448594533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3448594533
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3573700158
Short name T791
Test name
Test status
Simulation time 34450795 ps
CPU time 1.42 seconds
Started Jul 09 04:54:09 PM PDT 24
Finished Jul 09 04:54:12 PM PDT 24
Peak memory 236524 kb
Host smart-97dfb491-77a8-4ec8-8aef-57f8d84ea261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3573700158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3573700158
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1103127086
Short name T715
Test name
Test status
Simulation time 8617981 ps
CPU time 1.65 seconds
Started Jul 09 04:54:06 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 237456 kb
Host smart-a444f743-0933-4b26-99ad-1d0121884905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1103127086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1103127086
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2996391996
Short name T743
Test name
Test status
Simulation time 10779634 ps
CPU time 1.64 seconds
Started Jul 09 04:54:04 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 237488 kb
Host smart-401822a5-26d2-4c57-a6c7-b8811838914b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2996391996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2996391996
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.86126678
Short name T726
Test name
Test status
Simulation time 23506337 ps
CPU time 1.61 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 237416 kb
Host smart-207212df-0da4-47b3-9801-482c63d3fcf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=86126678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.86126678
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3518938121
Short name T337
Test name
Test status
Simulation time 24414854 ps
CPU time 1.47 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:10 PM PDT 24
Peak memory 237428 kb
Host smart-fe84526b-14e9-49d8-aae8-a0041f56055c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3518938121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3518938121
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2231753109
Short name T807
Test name
Test status
Simulation time 15057282 ps
CPU time 1.41 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 237412 kb
Host smart-f40bd12f-2e3c-498b-bd5c-aaeb475fbedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2231753109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2231753109
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.777848462
Short name T707
Test name
Test status
Simulation time 11361168 ps
CPU time 1.66 seconds
Started Jul 09 04:54:05 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 236544 kb
Host smart-9c6c52b2-5738-42b1-bc20-7890d4177c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777848462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.777848462
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.878954694
Short name T775
Test name
Test status
Simulation time 17698143 ps
CPU time 1.89 seconds
Started Jul 09 04:54:09 PM PDT 24
Finished Jul 09 04:54:13 PM PDT 24
Peak memory 236504 kb
Host smart-50986e44-ba87-4918-bc6f-5054dad702ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=878954694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.878954694
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2888578589
Short name T753
Test name
Test status
Simulation time 12269579 ps
CPU time 1.4 seconds
Started Jul 09 04:54:07 PM PDT 24
Finished Jul 09 04:54:10 PM PDT 24
Peak memory 236512 kb
Host smart-708c8ffd-b7cd-4043-9d57-4840a847b0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2888578589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2888578589
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2302876525
Short name T751
Test name
Test status
Simulation time 11068633 ps
CPU time 1.43 seconds
Started Jul 09 04:54:03 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 237516 kb
Host smart-06345430-1d61-4ff2-9824-df7504f9ff03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2302876525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2302876525
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2787083606
Short name T822
Test name
Test status
Simulation time 7585858555 ps
CPU time 130.55 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:55:51 PM PDT 24
Peak memory 237484 kb
Host smart-b1b4968b-8a61-46eb-914e-59ff544043e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2787083606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2787083606
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.982595836
Short name T788
Test name
Test status
Simulation time 5235344230 ps
CPU time 283.93 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:58:26 PM PDT 24
Peak memory 237432 kb
Host smart-2b6cf893-f8ec-46bb-80ae-2bebd9983c9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=982595836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.982595836
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2952092801
Short name T808
Test name
Test status
Simulation time 196197040 ps
CPU time 5.51 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:53:46 PM PDT 24
Peak memory 248716 kb
Host smart-25ec4ccd-e060-4435-b93a-8c9553bac14f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2952092801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2952092801
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3819258085
Short name T784
Test name
Test status
Simulation time 210241719 ps
CPU time 15.42 seconds
Started Jul 09 04:53:42 PM PDT 24
Finished Jul 09 04:53:58 PM PDT 24
Peak memory 251168 kb
Host smart-0a7f9f5c-aad2-41e0-841e-c6344c73a101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819258085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3819258085
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2316392803
Short name T722
Test name
Test status
Simulation time 63702456 ps
CPU time 3.33 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:53:45 PM PDT 24
Peak memory 237524 kb
Host smart-dc9e98d1-f0d1-4b3c-9638-a61f565bc4c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2316392803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2316392803
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1678857938
Short name T718
Test name
Test status
Simulation time 18327968 ps
CPU time 1.32 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:53:42 PM PDT 24
Peak memory 236468 kb
Host smart-dd4c8686-860d-444c-a918-50712e25de37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678857938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1678857938
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2233826757
Short name T774
Test name
Test status
Simulation time 2651274915 ps
CPU time 43.34 seconds
Started Jul 09 04:53:40 PM PDT 24
Finished Jul 09 04:54:24 PM PDT 24
Peak memory 248664 kb
Host smart-41e9599a-e197-4faa-8eb8-06adf43df10d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2233826757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2233826757
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3471876433
Short name T153
Test name
Test status
Simulation time 6052720703 ps
CPU time 323.16 seconds
Started Jul 09 04:53:43 PM PDT 24
Finished Jul 09 04:59:06 PM PDT 24
Peak memory 265276 kb
Host smart-e1d039ce-774c-4f6f-8b1d-50640c669f3f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471876433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3471876433
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1899136288
Short name T706
Test name
Test status
Simulation time 170495693 ps
CPU time 6.56 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:53:48 PM PDT 24
Peak memory 253580 kb
Host smart-004cd268-3dfd-4df4-ba71-5986d6904b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1899136288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1899136288
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.427066368
Short name T825
Test name
Test status
Simulation time 24010411 ps
CPU time 1.52 seconds
Started Jul 09 04:54:06 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 236512 kb
Host smart-a84f4039-1527-43a2-822b-d57367ae8307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=427066368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.427066368
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3818230299
Short name T744
Test name
Test status
Simulation time 22024728 ps
CPU time 2.13 seconds
Started Jul 09 04:54:07 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 236536 kb
Host smart-0cd29379-2bf9-48ea-a493-72650c814b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3818230299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3818230299
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2603973442
Short name T780
Test name
Test status
Simulation time 11989687 ps
CPU time 1.53 seconds
Started Jul 09 04:54:03 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 237560 kb
Host smart-bcef5d3d-aad8-46b5-962d-af4c618125eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2603973442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2603973442
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.203268575
Short name T798
Test name
Test status
Simulation time 8769572 ps
CPU time 1.43 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:11 PM PDT 24
Peak memory 235552 kb
Host smart-1df65f55-d933-4f7a-8d25-f44cd2d68bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=203268575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.203268575
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1840418156
Short name T818
Test name
Test status
Simulation time 10259960 ps
CPU time 1.42 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:10 PM PDT 24
Peak memory 235460 kb
Host smart-f931ed8a-7898-46d7-bd79-2aafc711a1d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1840418156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1840418156
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1314083020
Short name T756
Test name
Test status
Simulation time 9757894 ps
CPU time 1.64 seconds
Started Jul 09 04:54:04 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 236580 kb
Host smart-0ef6e61c-b439-4928-b327-98de000daafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1314083020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1314083020
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1263419887
Short name T717
Test name
Test status
Simulation time 25172974 ps
CPU time 1.5 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:16 PM PDT 24
Peak memory 237396 kb
Host smart-21c069fc-f07d-437a-aa36-3fbff7e28d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1263419887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1263419887
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1219592675
Short name T797
Test name
Test status
Simulation time 10327617 ps
CPU time 1.55 seconds
Started Jul 09 04:54:03 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 236676 kb
Host smart-0e21b527-9f0c-4ccb-b12a-81dc4d95231f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1219592675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1219592675
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1227070365
Short name T746
Test name
Test status
Simulation time 27110493 ps
CPU time 1.53 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:54:13 PM PDT 24
Peak memory 237412 kb
Host smart-063d0115-d455-4845-939d-301e1942371d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1227070365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1227070365
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2341384274
Short name T172
Test name
Test status
Simulation time 23181353 ps
CPU time 1.36 seconds
Started Jul 09 04:54:09 PM PDT 24
Finished Jul 09 04:54:13 PM PDT 24
Peak memory 237464 kb
Host smart-0c4a5654-a49b-42a4-8164-f44c1e02622f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2341384274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2341384274
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4191563572
Short name T796
Test name
Test status
Simulation time 180600051 ps
CPU time 8.72 seconds
Started Jul 09 04:53:45 PM PDT 24
Finished Jul 09 04:53:54 PM PDT 24
Peak memory 253140 kb
Host smart-2eac0b68-4118-4003-a489-52f9d5fcfd07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191563572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4191563572
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1814772675
Short name T734
Test name
Test status
Simulation time 71735528 ps
CPU time 6.34 seconds
Started Jul 09 04:53:42 PM PDT 24
Finished Jul 09 04:53:49 PM PDT 24
Peak memory 237544 kb
Host smart-cd0c390f-92e9-44ca-9f51-24791fa81672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1814772675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1814772675
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2832020645
Short name T801
Test name
Test status
Simulation time 10058348 ps
CPU time 1.42 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:53:43 PM PDT 24
Peak memory 237428 kb
Host smart-e1393d46-bb42-42f4-b0f7-9fb74aec2ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2832020645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2832020645
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.248092576
Short name T748
Test name
Test status
Simulation time 265012621 ps
CPU time 21.67 seconds
Started Jul 09 04:53:45 PM PDT 24
Finished Jul 09 04:54:07 PM PDT 24
Peak memory 248684 kb
Host smart-682d6f17-2301-47db-9be5-db85b9da1aab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=248092576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.248092576
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2273619594
Short name T794
Test name
Test status
Simulation time 9381303906 ps
CPU time 173.63 seconds
Started Jul 09 04:53:39 PM PDT 24
Finished Jul 09 04:56:33 PM PDT 24
Peak memory 266412 kb
Host smart-f467d0c5-3673-47d6-aed6-2edaa84b8821
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2273619594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2273619594
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3833159517
Short name T167
Test name
Test status
Simulation time 2273952083 ps
CPU time 402.28 seconds
Started Jul 09 04:53:38 PM PDT 24
Finished Jul 09 05:00:20 PM PDT 24
Peak memory 265612 kb
Host smart-5372d33a-32c4-407d-9940-cb500fe3809b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833159517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3833159517
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2795290482
Short name T812
Test name
Test status
Simulation time 603483426 ps
CPU time 17.04 seconds
Started Jul 09 04:53:41 PM PDT 24
Finished Jul 09 04:53:58 PM PDT 24
Peak memory 249704 kb
Host smart-905f1522-0959-4763-90e7-cb97d163da43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2795290482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2795290482
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1258529488
Short name T290
Test name
Test status
Simulation time 602374475 ps
CPU time 26.16 seconds
Started Jul 09 04:53:39 PM PDT 24
Finished Jul 09 04:54:05 PM PDT 24
Peak memory 237964 kb
Host smart-0489d276-217c-4a16-9b36-783115b00248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1258529488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1258529488
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1245575496
Short name T811
Test name
Test status
Simulation time 29814618 ps
CPU time 5.42 seconds
Started Jul 09 04:53:46 PM PDT 24
Finished Jul 09 04:53:52 PM PDT 24
Peak memory 240456 kb
Host smart-1738eb52-492e-46dc-9a21-090b5a97ab32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245575496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1245575496
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2506572646
Short name T770
Test name
Test status
Simulation time 187923618 ps
CPU time 10.82 seconds
Started Jul 09 04:53:43 PM PDT 24
Finished Jul 09 04:53:54 PM PDT 24
Peak memory 237408 kb
Host smart-a4bce242-6459-4375-a759-6763303eb7ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2506572646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2506572646
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2456347348
Short name T723
Test name
Test status
Simulation time 10085515 ps
CPU time 1.35 seconds
Started Jul 09 04:53:43 PM PDT 24
Finished Jul 09 04:53:44 PM PDT 24
Peak memory 236504 kb
Host smart-70c672d7-f2e0-409a-ae57-d360825b103f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2456347348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2456347348
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.102460761
Short name T201
Test name
Test status
Simulation time 2788202715 ps
CPU time 20.42 seconds
Started Jul 09 04:53:49 PM PDT 24
Finished Jul 09 04:54:10 PM PDT 24
Peak memory 245536 kb
Host smart-2605142d-4d52-4da2-aa2e-5b1ef2a6c881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=102460761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.102460761
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.972070354
Short name T150
Test name
Test status
Simulation time 6523049653 ps
CPU time 354.89 seconds
Started Jul 09 04:53:46 PM PDT 24
Finished Jul 09 04:59:42 PM PDT 24
Peak memory 265328 kb
Host smart-bf345857-32a7-4533-80c3-a0e690fa9400
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=972070354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.972070354
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1060483037
Short name T344
Test name
Test status
Simulation time 6584585553 ps
CPU time 427.98 seconds
Started Jul 09 04:53:49 PM PDT 24
Finished Jul 09 05:00:57 PM PDT 24
Peak memory 265092 kb
Host smart-8d720d3d-77d0-4341-a05c-d29a72f81d23
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060483037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1060483037
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.869678916
Short name T759
Test name
Test status
Simulation time 861263333 ps
CPU time 16.54 seconds
Started Jul 09 04:53:49 PM PDT 24
Finished Jul 09 04:54:06 PM PDT 24
Peak memory 248384 kb
Host smart-4a78907f-5344-422f-baf1-ff8c4dda5c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869678916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.869678916
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3214576756
Short name T810
Test name
Test status
Simulation time 60556846 ps
CPU time 9.7 seconds
Started Jul 09 04:53:50 PM PDT 24
Finished Jul 09 04:54:00 PM PDT 24
Peak memory 252932 kb
Host smart-b24f005f-8ed3-48f5-a3c9-1301754487b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214576756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3214576756
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1239885391
Short name T741
Test name
Test status
Simulation time 597855577 ps
CPU time 4.81 seconds
Started Jul 09 04:53:48 PM PDT 24
Finished Jul 09 04:53:54 PM PDT 24
Peak memory 240116 kb
Host smart-af6f9d64-83b4-4fe4-a807-f9ee7353710b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1239885391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1239885391
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1884091289
Short name T761
Test name
Test status
Simulation time 24978713 ps
CPU time 1.32 seconds
Started Jul 09 04:53:42 PM PDT 24
Finished Jul 09 04:53:44 PM PDT 24
Peak memory 237472 kb
Host smart-deaf562f-e329-416c-b611-4837ec0f5948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1884091289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1884091289
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2732840175
Short name T803
Test name
Test status
Simulation time 517209149 ps
CPU time 38.86 seconds
Started Jul 09 04:53:42 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 248576 kb
Host smart-c46852cd-4e28-4592-8004-bf969bfa6675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2732840175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2732840175
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.983165649
Short name T132
Test name
Test status
Simulation time 4284104410 ps
CPU time 304.77 seconds
Started Jul 09 04:53:44 PM PDT 24
Finished Jul 09 04:58:49 PM PDT 24
Peak memory 265196 kb
Host smart-2069bfca-a348-4bc4-9548-970444f505b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983165649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.983165649
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3365474684
Short name T769
Test name
Test status
Simulation time 242938636 ps
CPU time 17.93 seconds
Started Jul 09 04:53:45 PM PDT 24
Finished Jul 09 04:54:03 PM PDT 24
Peak memory 248416 kb
Host smart-4a83d0bb-a9bc-4e64-8684-03c1b19ebc61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3365474684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3365474684
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2994317658
Short name T742
Test name
Test status
Simulation time 605333407 ps
CPU time 42.86 seconds
Started Jul 09 04:53:43 PM PDT 24
Finished Jul 09 04:54:26 PM PDT 24
Peak memory 240356 kb
Host smart-3ad755b1-af25-456c-ae45-62bb974e8be5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2994317658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2994317658
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3639052530
Short name T339
Test name
Test status
Simulation time 170405210 ps
CPU time 7.85 seconds
Started Jul 09 04:53:48 PM PDT 24
Finished Jul 09 04:53:56 PM PDT 24
Peak memory 242156 kb
Host smart-6ce1aec1-6b1d-4f81-a87b-dd294616bd46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639052530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3639052530
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3384312454
Short name T199
Test name
Test status
Simulation time 66669995 ps
CPU time 5.56 seconds
Started Jul 09 04:53:48 PM PDT 24
Finished Jul 09 04:53:54 PM PDT 24
Peak memory 237440 kb
Host smart-41595014-2748-41e4-88d2-33c20d864f84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3384312454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3384312454
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2588510128
Short name T709
Test name
Test status
Simulation time 22782157 ps
CPU time 1.43 seconds
Started Jul 09 04:53:47 PM PDT 24
Finished Jul 09 04:53:49 PM PDT 24
Peak memory 236528 kb
Host smart-f3ab596d-62a5-420f-9e2a-01c264e55e3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2588510128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2588510128
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4036344606
Short name T765
Test name
Test status
Simulation time 2037727585 ps
CPU time 33.41 seconds
Started Jul 09 04:53:46 PM PDT 24
Finished Jul 09 04:54:20 PM PDT 24
Peak memory 244676 kb
Host smart-708094b8-5486-4aca-a41d-d341a66f1fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4036344606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4036344606
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2321816278
Short name T159
Test name
Test status
Simulation time 9353534849 ps
CPU time 203.92 seconds
Started Jul 09 04:53:50 PM PDT 24
Finished Jul 09 04:57:15 PM PDT 24
Peak memory 268624 kb
Host smart-6fb80489-ed2f-4780-b249-509e3ae16174
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2321816278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2321816278
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.680647053
Short name T141
Test name
Test status
Simulation time 92266578356 ps
CPU time 1328.49 seconds
Started Jul 09 04:53:49 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 265228 kb
Host smart-d302e42d-178f-429d-a441-e1f1e0c49be4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680647053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.680647053
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.252056037
Short name T787
Test name
Test status
Simulation time 148188986 ps
CPU time 16.34 seconds
Started Jul 09 04:53:51 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 254776 kb
Host smart-c3089af2-3d40-4968-ad31-80cd0aeccd90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=252056037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.252056037
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1359929687
Short name T760
Test name
Test status
Simulation time 34300463 ps
CPU time 2.85 seconds
Started Jul 09 04:53:47 PM PDT 24
Finished Jul 09 04:53:51 PM PDT 24
Peak memory 237720 kb
Host smart-a2966e8b-4130-4d94-b700-d6e9168abc94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1359929687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1359929687
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4247319377
Short name T747
Test name
Test status
Simulation time 213343041 ps
CPU time 4.58 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:53:59 PM PDT 24
Peak memory 237500 kb
Host smart-49d32b8e-5bd0-4021-8d27-9ce189b97e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247319377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.4247319377
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3476338720
Short name T738
Test name
Test status
Simulation time 95400870 ps
CPU time 3.36 seconds
Started Jul 09 04:53:49 PM PDT 24
Finished Jul 09 04:53:53 PM PDT 24
Peak memory 240284 kb
Host smart-8452fc8c-102c-4914-943a-74a10feb3bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3476338720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3476338720
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4098842553
Short name T782
Test name
Test status
Simulation time 8412845 ps
CPU time 1.41 seconds
Started Jul 09 04:53:50 PM PDT 24
Finished Jul 09 04:53:52 PM PDT 24
Peak memory 235492 kb
Host smart-f86f2c6d-d9d4-4978-80e9-21236c77688d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098842553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4098842553
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1169965537
Short name T745
Test name
Test status
Simulation time 184183379 ps
CPU time 14.68 seconds
Started Jul 09 04:53:54 PM PDT 24
Finished Jul 09 04:54:09 PM PDT 24
Peak memory 244664 kb
Host smart-661854d7-ea67-4e9d-9553-b315f414eeb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1169965537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1169965537
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3632442309
Short name T138
Test name
Test status
Simulation time 11899888401 ps
CPU time 193.71 seconds
Started Jul 09 04:53:47 PM PDT 24
Finished Jul 09 04:57:01 PM PDT 24
Peak memory 257112 kb
Host smart-453fba89-0717-4ec2-b4c7-e88d0bb5cd44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3632442309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3632442309
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3554407857
Short name T712
Test name
Test status
Simulation time 239439021 ps
CPU time 16.75 seconds
Started Jul 09 04:53:51 PM PDT 24
Finished Jul 09 04:54:08 PM PDT 24
Peak memory 248744 kb
Host smart-6485b74f-b0e0-4266-9d6e-d80928ce5c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3554407857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3554407857
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1694122634
Short name T625
Test name
Test status
Simulation time 36644324079 ps
CPU time 2333.06 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 05:33:03 PM PDT 24
Peak memory 289392 kb
Host smart-61ca9714-1643-44d8-8398-43241bef6615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694122634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1694122634
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1007941842
Short name T393
Test name
Test status
Simulation time 609795595 ps
CPU time 26.3 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:54:38 PM PDT 24
Peak memory 249156 kb
Host smart-e91585ad-869e-45f4-8668-11ea85e7804a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1007941842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1007941842
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3575366437
Short name T666
Test name
Test status
Simulation time 1011318831 ps
CPU time 77.44 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 256884 kb
Host smart-12d9c500-2320-42d4-a6a0-12d890b1826d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
66437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3575366437
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3363239890
Short name T605
Test name
Test status
Simulation time 469310808 ps
CPU time 9.43 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 248612 kb
Host smart-10456a63-8706-4794-9d7a-b870cfa07390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33632
39890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3363239890
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1707438631
Short name T299
Test name
Test status
Simulation time 551375000883 ps
CPU time 2316.58 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 05:32:46 PM PDT 24
Peak memory 289584 kb
Host smart-e36eef28-5db5-4cb6-8762-e367224ab8aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707438631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1707438631
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2158412
Short name T18
Test name
Test status
Simulation time 10172991604 ps
CPU time 1138.5 seconds
Started Jul 09 04:54:12 PM PDT 24
Finished Jul 09 05:13:12 PM PDT 24
Peak memory 286176 kb
Host smart-c2361ec9-28d3-4c98-acaf-a0fb9bb2e6eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2158412
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2156883397
Short name T516
Test name
Test status
Simulation time 745867449 ps
CPU time 23.89 seconds
Started Jul 09 04:54:09 PM PDT 24
Finished Jul 09 04:54:35 PM PDT 24
Peak memory 249160 kb
Host smart-a372d53d-a565-457d-9a4a-f27b201521e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
83397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2156883397
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2212031483
Short name T553
Test name
Test status
Simulation time 2350901481 ps
CPU time 69.99 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:55:19 PM PDT 24
Peak memory 248792 kb
Host smart-2be33c8d-33ee-4103-8e95-7fe83b2b6a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22120
31483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2212031483
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.678350997
Short name T13
Test name
Test status
Simulation time 1873294976 ps
CPU time 46.94 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 04:55:00 PM PDT 24
Peak memory 274236 kb
Host smart-6cab9ce9-6576-43ec-aa3a-3e4e884ba21f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=678350997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.678350997
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3896992509
Short name T212
Test name
Test status
Simulation time 2658569627 ps
CPU time 48.6 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:55:00 PM PDT 24
Peak memory 249128 kb
Host smart-a49dd210-5a22-494f-a90c-db266a4556d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969
92509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3896992509
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1249674032
Short name T206
Test name
Test status
Simulation time 3259185667 ps
CPU time 40.39 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:54:52 PM PDT 24
Peak memory 257416 kb
Host smart-0a3c8e07-7e8d-4c70-aff7-dd9ee88720d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12496
74032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1249674032
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3591476261
Short name T36
Test name
Test status
Simulation time 22868293666 ps
CPU time 2187.46 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 306684 kb
Host smart-2546904c-86b2-4b83-9af0-df36d277b969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591476261 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3591476261
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.918822704
Short name T66
Test name
Test status
Simulation time 47275862622 ps
CPU time 2850.56 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 289388 kb
Host smart-86c3b086-5c4d-43a2-8a9f-738e0d4d6f8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918822704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.918822704
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2339612256
Short name T552
Test name
Test status
Simulation time 773546235 ps
CPU time 12.16 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 04:54:25 PM PDT 24
Peak memory 249152 kb
Host smart-a152e155-24e9-43b4-8ca8-d7f5c6046230
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2339612256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2339612256
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3374197763
Short name T650
Test name
Test status
Simulation time 1177277788 ps
CPU time 25.66 seconds
Started Jul 09 04:54:09 PM PDT 24
Finished Jul 09 04:54:37 PM PDT 24
Peak memory 256432 kb
Host smart-db93d53f-3cb0-4d63-811b-7a2ca7faba09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33741
97763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3374197763
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2551932034
Short name T114
Test name
Test status
Simulation time 237620579 ps
CPU time 13.19 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:54:25 PM PDT 24
Peak memory 249180 kb
Host smart-216b1e33-042b-4c5b-b03e-adc83361d032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25519
32034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2551932034
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2979866128
Short name T235
Test name
Test status
Simulation time 15147914628 ps
CPU time 1439.68 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 282024 kb
Host smart-22546ea8-2442-40c2-b8bd-e305505bbad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979866128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2979866128
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3438450125
Short name T499
Test name
Test status
Simulation time 90064061723 ps
CPU time 1451.76 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 265748 kb
Host smart-41f5cfe1-4420-45ea-8c54-15a789442c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438450125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3438450125
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1150306001
Short name T311
Test name
Test status
Simulation time 15467386901 ps
CPU time 153.53 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:56:43 PM PDT 24
Peak memory 249268 kb
Host smart-3479633a-0660-4771-b10a-cbc627cc2baa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150306001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1150306001
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1975179320
Short name T491
Test name
Test status
Simulation time 152384023 ps
CPU time 15.16 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 04:54:28 PM PDT 24
Peak memory 257284 kb
Host smart-4a6478cf-57cf-41f7-830c-2391a17e9e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
79320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1975179320
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2607709124
Short name T447
Test name
Test status
Simulation time 152621317 ps
CPU time 9.53 seconds
Started Jul 09 04:54:10 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 249156 kb
Host smart-da4edd27-67fb-4281-aa44-698dd8d3aa84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26077
09124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2607709124
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3471039451
Short name T15
Test name
Test status
Simulation time 1286198686 ps
CPU time 54.21 seconds
Started Jul 09 04:54:12 PM PDT 24
Finished Jul 09 04:55:07 PM PDT 24
Peak memory 271572 kb
Host smart-d502fa25-40b4-448c-9f84-85adba90a282
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3471039451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3471039451
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1225270753
Short name T267
Test name
Test status
Simulation time 3962859206 ps
CPU time 43.23 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:58 PM PDT 24
Peak memory 256732 kb
Host smart-65ceda9c-0e30-4148-b981-3e9505d71e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12252
70753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1225270753
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1694607882
Short name T378
Test name
Test status
Simulation time 1037269229 ps
CPU time 46.89 seconds
Started Jul 09 04:54:12 PM PDT 24
Finished Jul 09 04:55:00 PM PDT 24
Peak memory 249456 kb
Host smart-9de9704f-8506-48ac-8acb-1a1ab08aa333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
07882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1694607882
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.676241079
Short name T522
Test name
Test status
Simulation time 72904747311 ps
CPU time 1970.46 seconds
Started Jul 09 04:54:07 PM PDT 24
Finished Jul 09 05:26:58 PM PDT 24
Peak memory 289204 kb
Host smart-7ad97243-cfee-4560-9911-41937906cd55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676241079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.676241079
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.635497514
Short name T45
Test name
Test status
Simulation time 110162547043 ps
CPU time 1235.83 seconds
Started Jul 09 04:54:27 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 288588 kb
Host smart-6b8a9ab1-895f-46e1-869f-539436d06583
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635497514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.635497514
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2560742380
Short name T595
Test name
Test status
Simulation time 167054221 ps
CPU time 9.5 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 04:54:36 PM PDT 24
Peak memory 249256 kb
Host smart-d8c61861-f166-4cbc-ac8f-4332e215ac69
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2560742380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2560742380
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1113225982
Short name T674
Test name
Test status
Simulation time 26289058136 ps
CPU time 237.09 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 04:58:23 PM PDT 24
Peak memory 257468 kb
Host smart-734335fc-fa9a-4c91-9240-acbcb993958b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11132
25982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1113225982
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3772494334
Short name T389
Test name
Test status
Simulation time 445399399 ps
CPU time 21.8 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 04:54:48 PM PDT 24
Peak memory 256536 kb
Host smart-6ccee3d5-8494-44b5-80fa-d21ccb0277ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
94334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3772494334
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1558458261
Short name T20
Test name
Test status
Simulation time 11341979784 ps
CPU time 1124.71 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 05:13:20 PM PDT 24
Peak memory 286476 kb
Host smart-b5917038-2763-409b-a359-5aa55d4d2230
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558458261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1558458261
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.976984765
Short name T240
Test name
Test status
Simulation time 2512698451 ps
CPU time 43.56 seconds
Started Jul 09 04:54:26 PM PDT 24
Finished Jul 09 04:55:10 PM PDT 24
Peak memory 257316 kb
Host smart-194d69f5-4544-4063-b8da-daaffe26b8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97698
4765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.976984765
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4220093011
Short name T465
Test name
Test status
Simulation time 872629498 ps
CPU time 7.7 seconds
Started Jul 09 04:54:27 PM PDT 24
Finished Jul 09 04:54:35 PM PDT 24
Peak memory 255092 kb
Host smart-0aa1d22b-34ae-4f0b-8e30-541324d446c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42200
93011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4220093011
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2229536629
Short name T408
Test name
Test status
Simulation time 1104655143 ps
CPU time 31.05 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:55:00 PM PDT 24
Peak memory 256352 kb
Host smart-2e3db64e-607d-4d82-8bd4-2d0b2375c012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22295
36629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2229536629
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4086800562
Short name T47
Test name
Test status
Simulation time 15006825559 ps
CPU time 278.37 seconds
Started Jul 09 04:54:26 PM PDT 24
Finished Jul 09 04:59:05 PM PDT 24
Peak memory 257476 kb
Host smart-9fbeeccc-49ff-4af4-9dc2-828cea1fad4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086800562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4086800562
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2647565175
Short name T231
Test name
Test status
Simulation time 39431498 ps
CPU time 3.65 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:54:33 PM PDT 24
Peak memory 249544 kb
Host smart-e5e94c6a-2d48-4108-b080-c2b272172960
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2647565175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2647565175
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1124096705
Short name T486
Test name
Test status
Simulation time 171513656 ps
CPU time 9.98 seconds
Started Jul 09 04:54:31 PM PDT 24
Finished Jul 09 04:54:41 PM PDT 24
Peak memory 249120 kb
Host smart-c4c2d686-8f05-4ee7-8b4e-daf07667fc20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1124096705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1124096705
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1034499175
Short name T518
Test name
Test status
Simulation time 4961104697 ps
CPU time 272 seconds
Started Jul 09 04:54:30 PM PDT 24
Finished Jul 09 04:59:03 PM PDT 24
Peak memory 252584 kb
Host smart-73feac13-71c6-483b-8fde-02ea0ccf964b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10344
99175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1034499175
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1344251315
Short name T87
Test name
Test status
Simulation time 472796049 ps
CPU time 29.4 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:54:58 PM PDT 24
Peak memory 256504 kb
Host smart-d6640118-82ba-439a-910d-7493c1dc1f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13442
51315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1344251315
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2137904579
Short name T691
Test name
Test status
Simulation time 80882136098 ps
CPU time 1361 seconds
Started Jul 09 04:54:29 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 273680 kb
Host smart-450dc458-e73e-48ba-af53-3cad6f5cca76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137904579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2137904579
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.973401943
Short name T80
Test name
Test status
Simulation time 77657930604 ps
CPU time 2240.01 seconds
Started Jul 09 04:54:29 PM PDT 24
Finished Jul 09 05:31:50 PM PDT 24
Peak memory 273916 kb
Host smart-14b9e407-5599-4c87-b68e-dd3acec88cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973401943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.973401943
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1626249279
Short name T308
Test name
Test status
Simulation time 10973001649 ps
CPU time 423.16 seconds
Started Jul 09 04:54:31 PM PDT 24
Finished Jul 09 05:01:35 PM PDT 24
Peak memory 249364 kb
Host smart-ceccde0e-090e-42e3-be53-7c43caa9f887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626249279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1626249279
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.104097801
Short name T370
Test name
Test status
Simulation time 7370920392 ps
CPU time 47.69 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:55:17 PM PDT 24
Peak memory 256672 kb
Host smart-81c17e3a-e783-44a0-8d8b-187485177ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
7801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.104097801
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1710935885
Short name T638
Test name
Test status
Simulation time 106973355 ps
CPU time 9.02 seconds
Started Jul 09 04:54:30 PM PDT 24
Finished Jul 09 04:54:40 PM PDT 24
Peak memory 256412 kb
Host smart-ba9f2f08-a4c7-4f2a-a0b6-9538d5c36992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109
35885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1710935885
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.983653076
Short name T275
Test name
Test status
Simulation time 811327091 ps
CPU time 48.48 seconds
Started Jul 09 04:54:29 PM PDT 24
Finished Jul 09 04:55:18 PM PDT 24
Peak memory 256876 kb
Host smart-06ad1738-10c5-40a8-ba65-81d182dad2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98365
3076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.983653076
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1973517384
Short name T363
Test name
Test status
Simulation time 3317928772 ps
CPU time 49.5 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:55:19 PM PDT 24
Peak memory 257072 kb
Host smart-d60bf317-a7ae-4ae9-97bc-52a773d8fcf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19735
17384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1973517384
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3274407622
Short name T281
Test name
Test status
Simulation time 45361713975 ps
CPU time 2900.02 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 289828 kb
Host smart-7787991c-498b-47a4-9690-4caee12ad373
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274407622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3274407622
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3843203569
Short name T243
Test name
Test status
Simulation time 96103835368 ps
CPU time 2927.17 seconds
Started Jul 09 04:54:30 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 298500 kb
Host smart-2c0e56fe-f4d0-44be-8fc7-81ece04c0433
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843203569 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3843203569
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3231200015
Short name T224
Test name
Test status
Simulation time 250586825 ps
CPU time 3.44 seconds
Started Jul 09 04:54:37 PM PDT 24
Finished Jul 09 04:54:42 PM PDT 24
Peak memory 249456 kb
Host smart-62870be4-43a5-46da-8262-ebf4701b9a02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3231200015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3231200015
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3925199305
Short name T631
Test name
Test status
Simulation time 44480436768 ps
CPU time 1546.66 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 05:20:21 PM PDT 24
Peak memory 289508 kb
Host smart-34ef2838-7bc9-4378-8a6e-3d40798cbd22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925199305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3925199305
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.839031037
Short name T367
Test name
Test status
Simulation time 910971178 ps
CPU time 24.02 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 04:54:59 PM PDT 24
Peak memory 249060 kb
Host smart-394313f9-c1be-413b-bd6d-f0513f71ff2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=839031037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.839031037
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2593645455
Short name T23
Test name
Test status
Simulation time 11269783380 ps
CPU time 352.29 seconds
Started Jul 09 04:54:30 PM PDT 24
Finished Jul 09 05:00:24 PM PDT 24
Peak memory 252564 kb
Host smart-7e7ba3ff-e0aa-45b9-8eba-f3b326556129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25936
45455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2593645455
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.985304783
Short name T204
Test name
Test status
Simulation time 510731377 ps
CPU time 35.11 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:55:04 PM PDT 24
Peak memory 257340 kb
Host smart-1a5a77a6-91b3-4588-9cda-116e573ad356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98530
4783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.985304783
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.692166858
Short name T490
Test name
Test status
Simulation time 50011314675 ps
CPU time 1368.36 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 05:17:24 PM PDT 24
Peak memory 289960 kb
Host smart-0d6bb961-8d09-46f3-8faa-8d1c9100221e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692166858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.692166858
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1342887884
Short name T583
Test name
Test status
Simulation time 2900587524 ps
CPU time 130.19 seconds
Started Jul 09 04:54:36 PM PDT 24
Finished Jul 09 04:56:47 PM PDT 24
Peak memory 255828 kb
Host smart-c9d86abd-e1b3-4dd0-919c-ac2e74c51bf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342887884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1342887884
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1400763440
Short name T443
Test name
Test status
Simulation time 42723785 ps
CPU time 6.89 seconds
Started Jul 09 04:54:29 PM PDT 24
Finished Jul 09 04:54:36 PM PDT 24
Peak memory 249132 kb
Host smart-c3116bd5-bad8-406e-b739-b198fa5359e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
63440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1400763440
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1545419298
Short name T588
Test name
Test status
Simulation time 311875374 ps
CPU time 8.41 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:54:37 PM PDT 24
Peak memory 249140 kb
Host smart-96434172-bd0c-4dcd-a9cd-f95169daf51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15454
19298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1545419298
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1922513802
Short name T203
Test name
Test status
Simulation time 61669690 ps
CPU time 2.68 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 04:54:38 PM PDT 24
Peak memory 241008 kb
Host smart-1a04f349-270c-4771-8f35-eca474d52b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19225
13802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1922513802
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3039839655
Short name T531
Test name
Test status
Simulation time 295859364 ps
CPU time 17.6 seconds
Started Jul 09 04:54:28 PM PDT 24
Finished Jul 09 04:54:47 PM PDT 24
Peak memory 249152 kb
Host smart-91af233a-9929-4ff0-b1fd-29ec084ab0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30398
39655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3039839655
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.554835098
Short name T82
Test name
Test status
Simulation time 40403144728 ps
CPU time 3094.81 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 305952 kb
Host smart-18ff25d8-76ad-4108-9102-972ad1f2fe1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554835098 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.554835098
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1472034560
Short name T44
Test name
Test status
Simulation time 33116516 ps
CPU time 2.34 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:54:37 PM PDT 24
Peak memory 249472 kb
Host smart-430d8175-7c39-4673-9be0-fc68864245ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1472034560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1472034560
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1251143334
Short name T194
Test name
Test status
Simulation time 98606647251 ps
CPU time 1598.2 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 05:21:12 PM PDT 24
Peak memory 273592 kb
Host smart-746421af-6e8e-418c-98f4-74b54fb95ff2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251143334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1251143334
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2254368277
Short name T382
Test name
Test status
Simulation time 635807607 ps
CPU time 9.63 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:54:43 PM PDT 24
Peak memory 249072 kb
Host smart-54feef30-0b8f-4746-8f13-3eba86f4af4b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2254368277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2254368277
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1481058267
Short name T420
Test name
Test status
Simulation time 10472816211 ps
CPU time 299.15 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 04:59:35 PM PDT 24
Peak memory 256840 kb
Host smart-9887edc4-91e1-43a7-af01-b5c93472117e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14810
58267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1481058267
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.752250714
Short name T73
Test name
Test status
Simulation time 428577257 ps
CPU time 22.89 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:54:57 PM PDT 24
Peak memory 248840 kb
Host smart-95453d1d-caf5-4cda-9730-d138ef3981f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75225
0714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.752250714
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3470413638
Short name T489
Test name
Test status
Simulation time 79877516025 ps
CPU time 1224.05 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 05:14:59 PM PDT 24
Peak memory 266776 kb
Host smart-dafd8496-d2e4-43c9-bba8-094e02692d82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470413638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3470413638
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1433984014
Short name T687
Test name
Test status
Simulation time 6051611702 ps
CPU time 78.19 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 04:55:53 PM PDT 24
Peak memory 255408 kb
Host smart-31e0d980-f70c-4319-a136-7ad801caed2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433984014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1433984014
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1070751587
Short name T190
Test name
Test status
Simulation time 31847128 ps
CPU time 4.84 seconds
Started Jul 09 04:54:36 PM PDT 24
Finished Jul 09 04:54:42 PM PDT 24
Peak memory 254184 kb
Host smart-4936a953-9f40-41da-979f-4c8871cf108d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
51587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1070751587
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2378611155
Short name T618
Test name
Test status
Simulation time 65768017 ps
CPU time 9.31 seconds
Started Jul 09 04:54:32 PM PDT 24
Finished Jul 09 04:54:42 PM PDT 24
Peak memory 255512 kb
Host smart-3bdb4142-33bf-4743-b56f-74a7f8502748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786
11155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2378611155
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3849196234
Short name T442
Test name
Test status
Simulation time 524729824 ps
CPU time 20.75 seconds
Started Jul 09 04:54:32 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 257356 kb
Host smart-8cbc0dc9-c01b-4f70-9a67-85a37074627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
96234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3849196234
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3954271290
Short name T50
Test name
Test status
Simulation time 163398452 ps
CPU time 4.49 seconds
Started Jul 09 04:54:35 PM PDT 24
Finished Jul 09 04:54:41 PM PDT 24
Peak memory 240976 kb
Host smart-5851cd52-10b6-41b0-b4ba-a8cabd03f444
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954271290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3954271290
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3825316149
Short name T89
Test name
Test status
Simulation time 21397520460 ps
CPU time 2390.3 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 05:34:26 PM PDT 24
Peak memory 306120 kb
Host smart-373dd396-b220-4a55-8c1d-3b19f2863940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825316149 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3825316149
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1086801021
Short name T450
Test name
Test status
Simulation time 197692963123 ps
CPU time 2649.51 seconds
Started Jul 09 04:54:44 PM PDT 24
Finished Jul 09 05:38:55 PM PDT 24
Peak memory 289720 kb
Host smart-98559ecc-ca63-42ba-8275-5927ed3cd3bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086801021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1086801021
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1575548445
Short name T655
Test name
Test status
Simulation time 1645377443 ps
CPU time 121.99 seconds
Started Jul 09 04:54:36 PM PDT 24
Finished Jul 09 04:56:38 PM PDT 24
Peak memory 257476 kb
Host smart-ed047409-789d-49f4-9ca1-1a5fbbd7aab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
48445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1575548445
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2304295581
Short name T481
Test name
Test status
Simulation time 40747509 ps
CPU time 2.93 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:54:47 PM PDT 24
Peak memory 240280 kb
Host smart-efdf8793-c31b-4173-b7b6-5cc20a548be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23042
95581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2304295581
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1006322102
Short name T315
Test name
Test status
Simulation time 32263560777 ps
CPU time 2060.37 seconds
Started Jul 09 04:54:36 PM PDT 24
Finished Jul 09 05:28:57 PM PDT 24
Peak memory 282064 kb
Host smart-8e13da27-1e2d-473a-b2ca-c76134b4e73e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006322102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1006322102
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.199488995
Short name T399
Test name
Test status
Simulation time 220880547978 ps
CPU time 2932.21 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 289944 kb
Host smart-1b3f339b-5892-4bd3-9412-0e3e7c3c1f3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199488995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.199488995
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1034397823
Short name T312
Test name
Test status
Simulation time 9116976363 ps
CPU time 360.51 seconds
Started Jul 09 04:54:44 PM PDT 24
Finished Jul 09 05:00:46 PM PDT 24
Peak memory 249232 kb
Host smart-692e7815-f0b8-46f1-8fc3-d07c0be44b3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034397823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1034397823
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.259585980
Short name T77
Test name
Test status
Simulation time 903042473 ps
CPU time 17.36 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:54:51 PM PDT 24
Peak memory 255776 kb
Host smart-b7198ea1-6eac-4f9e-8809-52b79b1b07c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958
5980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.259585980
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3307501873
Short name T90
Test name
Test status
Simulation time 152085139 ps
CPU time 9.89 seconds
Started Jul 09 04:54:37 PM PDT 24
Finished Jul 09 04:54:48 PM PDT 24
Peak memory 256092 kb
Host smart-46fff6c6-4431-41a0-a9ad-2a821f5497e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33075
01873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3307501873
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1412910209
Short name T591
Test name
Test status
Simulation time 270675591 ps
CPU time 30.14 seconds
Started Jul 09 04:54:36 PM PDT 24
Finished Jul 09 04:55:06 PM PDT 24
Peak memory 256716 kb
Host smart-43687f6e-c722-4ec9-9a67-a3f22ebfbaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14129
10209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1412910209
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1962942471
Short name T695
Test name
Test status
Simulation time 3930681235 ps
CPU time 42.15 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:55:16 PM PDT 24
Peak memory 257428 kb
Host smart-e851faa7-969c-4af3-813f-967898372e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
42471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1962942471
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1531867458
Short name T480
Test name
Test status
Simulation time 52768599834 ps
CPU time 1348.66 seconds
Started Jul 09 04:54:38 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 289676 kb
Host smart-fed3142b-b9f4-4bc1-aa55-0f7d8abea3e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531867458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1531867458
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3035899107
Short name T25
Test name
Test status
Simulation time 23449517 ps
CPU time 3.37 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:55:02 PM PDT 24
Peak memory 249388 kb
Host smart-f0bf6c8d-c2d4-4d18-a52f-d73510834ce0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3035899107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3035899107
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3469920113
Short name T444
Test name
Test status
Simulation time 45861522256 ps
CPU time 1521.5 seconds
Started Jul 09 04:54:38 PM PDT 24
Finished Jul 09 05:20:00 PM PDT 24
Peak memory 273764 kb
Host smart-de5ff0d8-84f5-40eb-a662-3670314a1fde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469920113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3469920113
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1742521465
Short name T558
Test name
Test status
Simulation time 136535369 ps
CPU time 9.24 seconds
Started Jul 09 04:54:41 PM PDT 24
Finished Jul 09 04:54:52 PM PDT 24
Peak memory 249084 kb
Host smart-1a06877c-654e-4ad0-974f-1b1c96aeea44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1742521465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1742521465
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1139532899
Short name T364
Test name
Test status
Simulation time 18116943852 ps
CPU time 256.18 seconds
Started Jul 09 04:54:38 PM PDT 24
Finished Jul 09 04:58:55 PM PDT 24
Peak memory 257484 kb
Host smart-d6554904-e340-4685-bf42-c6a6bb049887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395
32899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1139532899
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.772982689
Short name T198
Test name
Test status
Simulation time 1653931405 ps
CPU time 53.51 seconds
Started Jul 09 04:54:39 PM PDT 24
Finished Jul 09 04:55:33 PM PDT 24
Peak memory 249072 kb
Host smart-a4c0f50c-6129-4de9-83fb-cdf10a0c14fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77298
2689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.772982689
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.229450316
Short name T665
Test name
Test status
Simulation time 14365291747 ps
CPU time 1527.98 seconds
Started Jul 09 04:54:37 PM PDT 24
Finished Jul 09 05:20:06 PM PDT 24
Peak memory 289896 kb
Host smart-befe7cf9-4d11-4abf-a333-b1272918363a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229450316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.229450316
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.390936402
Short name T300
Test name
Test status
Simulation time 2824435095 ps
CPU time 69.01 seconds
Started Jul 09 04:54:37 PM PDT 24
Finished Jul 09 04:55:47 PM PDT 24
Peak memory 254876 kb
Host smart-5d2a8870-4507-460c-8794-03533c7e071e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390936402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.390936402
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1414761697
Short name T645
Test name
Test status
Simulation time 836834131 ps
CPU time 26.09 seconds
Started Jul 09 04:54:38 PM PDT 24
Finished Jul 09 04:55:05 PM PDT 24
Peak memory 255648 kb
Host smart-00de8a2e-47b2-4ea4-bb0a-ef3276acafdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147
61697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1414761697
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3925404881
Short name T535
Test name
Test status
Simulation time 937645751 ps
CPU time 35.11 seconds
Started Jul 09 04:54:38 PM PDT 24
Finished Jul 09 04:55:14 PM PDT 24
Peak memory 248920 kb
Host smart-d7914f4f-7179-4d28-85d8-10a51e5436e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39254
04881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3925404881
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.874302010
Short name T403
Test name
Test status
Simulation time 1490696486 ps
CPU time 55.65 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 04:55:47 PM PDT 24
Peak memory 249092 kb
Host smart-bff2cbe8-9aae-4e29-acb1-d012b4628a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87430
2010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.874302010
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1541124374
Short name T511
Test name
Test status
Simulation time 94834511 ps
CPU time 6.56 seconds
Started Jul 09 04:54:37 PM PDT 24
Finished Jul 09 04:54:45 PM PDT 24
Peak memory 253104 kb
Host smart-073466fd-abfe-4e3a-b129-458d57b5ea3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15411
24374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1541124374
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.295936748
Short name T412
Test name
Test status
Simulation time 55923877401 ps
CPU time 1500.92 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:20:01 PM PDT 24
Peak memory 306384 kb
Host smart-726c4c4e-f7bc-4345-89e7-f59b848129a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295936748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.295936748
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2259820574
Short name T228
Test name
Test status
Simulation time 33256714 ps
CPU time 3.31 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 04:54:46 PM PDT 24
Peak memory 249404 kb
Host smart-c8d2fdfb-d3a5-4b1f-99bd-abba95772e17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2259820574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2259820574
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.154885742
Short name T572
Test name
Test status
Simulation time 40202570636 ps
CPU time 1006.97 seconds
Started Jul 09 04:54:41 PM PDT 24
Finished Jul 09 05:11:29 PM PDT 24
Peak memory 272824 kb
Host smart-5d988b5a-a879-497f-9d38-71be87f762a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154885742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.154885742
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2496777038
Short name T380
Test name
Test status
Simulation time 196661702 ps
CPU time 12.05 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:12 PM PDT 24
Peak memory 248848 kb
Host smart-c591c8ed-9ac8-4693-b0b1-4cfdece596a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2496777038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2496777038
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3502597726
Short name T548
Test name
Test status
Simulation time 12779213200 ps
CPU time 186.61 seconds
Started Jul 09 04:54:41 PM PDT 24
Finished Jul 09 04:57:49 PM PDT 24
Peak memory 257404 kb
Host smart-2ee491c4-71dc-467d-a086-728830cee7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35025
97726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3502597726
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.992777111
Short name T430
Test name
Test status
Simulation time 488162480 ps
CPU time 25.67 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 04:55:09 PM PDT 24
Peak memory 256456 kb
Host smart-34b8aa1f-eaee-4894-a5bc-c5dc642e18e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99277
7111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.992777111
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2315035685
Short name T292
Test name
Test status
Simulation time 89618828180 ps
CPU time 2480.37 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 05:36:04 PM PDT 24
Peak memory 289976 kb
Host smart-b4711f5b-5ae2-4e10-84c2-e49831f7f078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315035685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2315035685
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2558777047
Short name T219
Test name
Test status
Simulation time 8975499349 ps
CPU time 374.6 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 05:00:58 PM PDT 24
Peak memory 255988 kb
Host smart-ac0043f0-06d6-47f6-bb3c-918eb5c44c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558777047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2558777047
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3162304782
Short name T627
Test name
Test status
Simulation time 1990308009 ps
CPU time 27.21 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:27 PM PDT 24
Peak memory 257016 kb
Host smart-7190df32-18ba-4e5c-b275-91211e2e46e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31623
04782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3162304782
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2177798268
Short name T459
Test name
Test status
Simulation time 885984617 ps
CPU time 23.23 seconds
Started Jul 09 04:54:52 PM PDT 24
Finished Jul 09 04:55:16 PM PDT 24
Peak memory 256732 kb
Host smart-9a681d33-fe5d-4162-a977-56de1bcaf242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
98268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2177798268
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2017971844
Short name T35
Test name
Test status
Simulation time 4500800672 ps
CPU time 28.19 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:55:13 PM PDT 24
Peak memory 256536 kb
Host smart-152f2489-2de6-40b6-8734-ab4b6c847c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20179
71844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2017971844
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1677734289
Short name T567
Test name
Test status
Simulation time 23485756446 ps
CPU time 2030.34 seconds
Started Jul 09 04:54:45 PM PDT 24
Finished Jul 09 05:28:37 PM PDT 24
Peak memory 305132 kb
Host smart-0e8d7a52-27a3-46a7-b82d-415f0a9f1531
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677734289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1677734289
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1525703497
Short name T191
Test name
Test status
Simulation time 61211537 ps
CPU time 4.64 seconds
Started Jul 09 04:54:45 PM PDT 24
Finished Jul 09 04:54:51 PM PDT 24
Peak memory 249544 kb
Host smart-91854045-4ca0-49ee-893d-246615d45c75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1525703497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1525703497
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3290106085
Short name T221
Test name
Test status
Simulation time 286067870939 ps
CPU time 2484.3 seconds
Started Jul 09 04:54:45 PM PDT 24
Finished Jul 09 05:36:10 PM PDT 24
Peak memory 285856 kb
Host smart-c0372d59-e9bf-4427-a598-15542240437d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290106085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3290106085
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4173086115
Short name T504
Test name
Test status
Simulation time 1225724285 ps
CPU time 10.33 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:54:55 PM PDT 24
Peak memory 249144 kb
Host smart-1f0e7c80-2ce6-4858-845b-e232597fcd62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4173086115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4173086115
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1497408065
Short name T405
Test name
Test status
Simulation time 5961590563 ps
CPU time 81.41 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:56:06 PM PDT 24
Peak memory 257404 kb
Host smart-1ca04efd-d9f8-4b0d-af48-80b79d4edc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
08065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1497408065
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1043137965
Short name T91
Test name
Test status
Simulation time 433638545 ps
CPU time 25.31 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:24 PM PDT 24
Peak memory 249044 kb
Host smart-8ecf7d9a-33f6-422e-873d-3bf57cbeacae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
37965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1043137965
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3781935217
Short name T313
Test name
Test status
Simulation time 18083808129 ps
CPU time 793.2 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 05:07:57 PM PDT 24
Peak memory 272464 kb
Host smart-3f433e76-9568-45df-9ebc-9f150a734ff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781935217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3781935217
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2394192035
Short name T635
Test name
Test status
Simulation time 26435856929 ps
CPU time 494.38 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 05:03:06 PM PDT 24
Peak memory 249364 kb
Host smart-09be1eec-0e48-4e6c-81f9-0ccc9d210221
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394192035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2394192035
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1343897910
Short name T85
Test name
Test status
Simulation time 328726304 ps
CPU time 19.2 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 04:55:03 PM PDT 24
Peak memory 256412 kb
Host smart-33eb2e74-fbee-47b5-85f7-f454e7e93e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13438
97910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1343897910
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3581771287
Short name T497
Test name
Test status
Simulation time 183810189 ps
CPU time 4.34 seconds
Started Jul 09 04:54:45 PM PDT 24
Finished Jul 09 04:54:50 PM PDT 24
Peak memory 240960 kb
Host smart-3e21e09d-ed0b-462b-b9fc-5a185d13d656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35817
71287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3581771287
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.417646134
Short name T214
Test name
Test status
Simulation time 749934569 ps
CPU time 53.16 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:55:37 PM PDT 24
Peak memory 248940 kb
Host smart-62ac479f-de94-428b-8305-12091cbb61ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
6134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.417646134
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1836917609
Short name T629
Test name
Test status
Simulation time 875136834 ps
CPU time 44.03 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:55:28 PM PDT 24
Peak memory 257332 kb
Host smart-e012f856-f8a9-4ac9-8fee-9f6204d9e672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18369
17609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1836917609
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3323870201
Short name T104
Test name
Test status
Simulation time 18371001279 ps
CPU time 1505.74 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 05:19:49 PM PDT 24
Peak memory 290068 kb
Host smart-096a6f48-ff93-4185-b5e4-27d84f5a6543
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323870201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3323870201
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2638979636
Short name T223
Test name
Test status
Simulation time 696728655 ps
CPU time 3.8 seconds
Started Jul 09 04:54:46 PM PDT 24
Finished Jul 09 04:54:50 PM PDT 24
Peak memory 249484 kb
Host smart-71d6e24e-078f-44a3-9601-e79ad6239f69
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2638979636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2638979636
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3211005940
Short name T570
Test name
Test status
Simulation time 61111253112 ps
CPU time 1381.51 seconds
Started Jul 09 04:54:46 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 288512 kb
Host smart-910021c4-98fd-4151-84a4-dbe2e72b7dfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211005940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3211005940
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.557028988
Short name T579
Test name
Test status
Simulation time 127855649 ps
CPU time 7.43 seconds
Started Jul 09 04:54:44 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 249064 kb
Host smart-e465ec31-3a74-4c6b-8ef3-aaca036f88fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=557028988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.557028988
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1631282564
Short name T636
Test name
Test status
Simulation time 404498635 ps
CPU time 24.5 seconds
Started Jul 09 04:54:44 PM PDT 24
Finished Jul 09 04:55:10 PM PDT 24
Peak memory 256880 kb
Host smart-fd38d3cd-6921-431b-9daf-587f9952a089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16312
82564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1631282564
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.278038120
Short name T545
Test name
Test status
Simulation time 11667311149 ps
CPU time 661.96 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 05:05:52 PM PDT 24
Peak memory 265992 kb
Host smart-a2239fa6-9ddf-4625-a378-a3c6d7fe6c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278038120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.278038120
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1827125532
Short name T74
Test name
Test status
Simulation time 37264253707 ps
CPU time 384.22 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:01:23 PM PDT 24
Peak memory 248356 kb
Host smart-c7cfd5ca-586e-4cd5-9601-41a4f60d405e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827125532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1827125532
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2265942427
Short name T679
Test name
Test status
Simulation time 5277389699 ps
CPU time 76.06 seconds
Started Jul 09 04:54:43 PM PDT 24
Finished Jul 09 04:56:01 PM PDT 24
Peak memory 249300 kb
Host smart-33e85774-04c1-4551-babc-6f9cc72751d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22659
42427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2265942427
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1884794553
Short name T472
Test name
Test status
Simulation time 1615035906 ps
CPU time 27.74 seconds
Started Jul 09 04:54:42 PM PDT 24
Finished Jul 09 04:55:11 PM PDT 24
Peak memory 249160 kb
Host smart-11da5ad0-6b12-4390-a773-c5740b73063d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18847
94553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1884794553
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.759320766
Short name T466
Test name
Test status
Simulation time 1535485477 ps
CPU time 48.23 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 04:55:42 PM PDT 24
Peak memory 249184 kb
Host smart-cb447931-8f97-46b2-9e84-3b0a4255b8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75932
0766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.759320766
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2338552569
Short name T699
Test name
Test status
Simulation time 2146850389 ps
CPU time 33.75 seconds
Started Jul 09 04:54:44 PM PDT 24
Finished Jul 09 04:55:19 PM PDT 24
Peak memory 249576 kb
Host smart-62dc7e6e-f80c-4265-ade7-c035d478886b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385
52569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2338552569
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2333006423
Short name T67
Test name
Test status
Simulation time 75666613837 ps
CPU time 3089.69 seconds
Started Jul 09 04:54:46 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 289756 kb
Host smart-af169fc8-d981-43a0-ab61-62664b894672
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333006423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2333006423
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1396366568
Short name T230
Test name
Test status
Simulation time 37929998 ps
CPU time 3.6 seconds
Started Jul 09 04:54:50 PM PDT 24
Finished Jul 09 04:54:55 PM PDT 24
Peak memory 249428 kb
Host smart-e4da9a09-4daa-419d-9e9e-11f65b14881c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1396366568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1396366568
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3529867091
Short name T467
Test name
Test status
Simulation time 98066931126 ps
CPU time 1132.51 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 05:13:47 PM PDT 24
Peak memory 265664 kb
Host smart-1b4b2617-fc1e-43d5-b759-61253bcb03a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529867091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3529867091
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3466668622
Short name T593
Test name
Test status
Simulation time 2395104346 ps
CPU time 55.11 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 04:55:49 PM PDT 24
Peak memory 249256 kb
Host smart-fbc33f8c-8689-4a2a-b89a-aca8e5316efc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3466668622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3466668622
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4105761491
Short name T237
Test name
Test status
Simulation time 4158170128 ps
CPU time 122.95 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 04:56:55 PM PDT 24
Peak memory 256636 kb
Host smart-51cea6e3-57ed-4c4b-b7c5-d2caa9421ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41057
61491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4105761491
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.380024181
Short name T70
Test name
Test status
Simulation time 503874531 ps
CPU time 36.74 seconds
Started Jul 09 04:54:47 PM PDT 24
Finished Jul 09 04:55:24 PM PDT 24
Peak memory 249092 kb
Host smart-5955f1a7-8cbf-4432-b8f9-d883ad88f233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38002
4181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.380024181
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1036399172
Short name T601
Test name
Test status
Simulation time 26411695503 ps
CPU time 731.63 seconds
Started Jul 09 04:54:47 PM PDT 24
Finished Jul 09 05:06:59 PM PDT 24
Peak memory 272820 kb
Host smart-3d0d54cc-a345-494d-9059-042fbe78f371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036399172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1036399172
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.241188851
Short name T681
Test name
Test status
Simulation time 283619320497 ps
CPU time 1587.1 seconds
Started Jul 09 04:54:55 PM PDT 24
Finished Jul 09 05:21:23 PM PDT 24
Peak memory 273828 kb
Host smart-3882bd42-0293-4eaf-a2a1-3c7c67035ee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241188851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.241188851
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2415274995
Short name T99
Test name
Test status
Simulation time 12887562512 ps
CPU time 528.21 seconds
Started Jul 09 04:54:45 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 256204 kb
Host smart-905fa670-b064-4cb4-afaf-d6aa7ae9cb75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415274995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2415274995
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.762585474
Short name T640
Test name
Test status
Simulation time 920056049 ps
CPU time 33.58 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 249128 kb
Host smart-ff3c6033-635b-4d7b-937c-69915109f349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76258
5474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.762585474
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1513173050
Short name T551
Test name
Test status
Simulation time 2817415872 ps
CPU time 13.63 seconds
Started Jul 09 04:54:52 PM PDT 24
Finished Jul 09 04:55:06 PM PDT 24
Peak memory 248668 kb
Host smart-792b6a1f-b3bc-4746-8388-52044940478c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
73050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1513173050
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2312438072
Short name T93
Test name
Test status
Simulation time 231680613 ps
CPU time 33.51 seconds
Started Jul 09 04:54:52 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 256880 kb
Host smart-9d74e183-c77c-439e-8f72-ff311b5959ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23124
38072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2312438072
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.163137803
Short name T615
Test name
Test status
Simulation time 412664783 ps
CPU time 15.06 seconds
Started Jul 09 04:54:52 PM PDT 24
Finished Jul 09 04:55:08 PM PDT 24
Peak memory 255308 kb
Host smart-3b3c9217-3f4d-4b83-9353-fbab25f9ece9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16313
7803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.163137803
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1700688664
Short name T79
Test name
Test status
Simulation time 35507463909 ps
CPU time 1838.72 seconds
Started Jul 09 04:54:46 PM PDT 24
Finished Jul 09 05:25:26 PM PDT 24
Peak memory 301728 kb
Host smart-87e3dfba-fbee-4e6c-a7a1-715de9ee991e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700688664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1700688664
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.436147871
Short name T95
Test name
Test status
Simulation time 182234676974 ps
CPU time 4712.8 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 06:13:27 PM PDT 24
Peak memory 338968 kb
Host smart-80eac731-e99b-4801-8d87-8855afbf7520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436147871 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.436147871
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3163938453
Short name T71
Test name
Test status
Simulation time 15359911 ps
CPU time 2.34 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 04:54:18 PM PDT 24
Peak memory 249452 kb
Host smart-ac1ab411-6d15-4ab9-80b1-9dd4dab85023
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3163938453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3163938453
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2840484560
Short name T216
Test name
Test status
Simulation time 2017780335 ps
CPU time 25.05 seconds
Started Jul 09 04:54:14 PM PDT 24
Finished Jul 09 04:54:40 PM PDT 24
Peak memory 249268 kb
Host smart-6ad1a737-cc29-42de-ac6a-faaa8c8879a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2840484560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2840484560
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3844888559
Short name T492
Test name
Test status
Simulation time 2067700114 ps
CPU time 68.6 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 04:55:21 PM PDT 24
Peak memory 256684 kb
Host smart-f6520bc9-917e-498a-ac67-9ec60566d1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
88559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3844888559
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3180205954
Short name T536
Test name
Test status
Simulation time 341169249 ps
CPU time 13.37 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:28 PM PDT 24
Peak memory 257352 kb
Host smart-21416dd9-74e1-4f4a-bcfb-e291afb4c02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
05954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3180205954
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3545711601
Short name T327
Test name
Test status
Simulation time 54088267528 ps
CPU time 1195.69 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 05:14:09 PM PDT 24
Peak memory 285120 kb
Host smart-685e9f88-1a30-4dd6-a1da-86f836548cb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545711601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3545711601
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1487117024
Short name T220
Test name
Test status
Simulation time 116861247773 ps
CPU time 1634.67 seconds
Started Jul 09 04:54:14 PM PDT 24
Finished Jul 09 05:21:30 PM PDT 24
Peak memory 273836 kb
Host smart-625d7809-7324-4fcd-8dbd-b20647707bea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487117024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1487117024
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1735955059
Short name T302
Test name
Test status
Simulation time 50614155914 ps
CPU time 493.26 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 05:02:28 PM PDT 24
Peak memory 249364 kb
Host smart-7f7b63ba-43ed-4ca2-b1a3-2bfc17101ec0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735955059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1735955059
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2161983517
Short name T446
Test name
Test status
Simulation time 1376235382 ps
CPU time 40.48 seconds
Started Jul 09 04:54:12 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 256436 kb
Host smart-5719fca1-d53b-46fd-ad7f-a57a8497db8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21619
83517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2161983517
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2853911782
Short name T589
Test name
Test status
Simulation time 500967619 ps
CPU time 18.72 seconds
Started Jul 09 04:54:08 PM PDT 24
Finished Jul 09 04:54:29 PM PDT 24
Peak memory 248168 kb
Host smart-69e95b7a-e885-453b-8102-267120fbd350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
11782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2853911782
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4095836181
Short name T39
Test name
Test status
Simulation time 1427533838 ps
CPU time 31.07 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:45 PM PDT 24
Peak memory 271004 kb
Host smart-894a0d9a-1735-49db-8456-702349eb39a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4095836181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4095836181
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1171673317
Short name T624
Test name
Test status
Simulation time 1699156132 ps
CPU time 22.94 seconds
Started Jul 09 04:54:11 PM PDT 24
Finished Jul 09 04:54:36 PM PDT 24
Peak memory 257304 kb
Host smart-f7e959d0-20e9-438d-9094-99b963db8307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716
73317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1171673317
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.244007177
Short name T37
Test name
Test status
Simulation time 34705185621 ps
CPU time 2294.55 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 05:32:30 PM PDT 24
Peak memory 290236 kb
Host smart-6250d3d0-855f-4803-98aa-e0738e4bff3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244007177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.244007177
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1401209874
Short name T613
Test name
Test status
Simulation time 1267574749 ps
CPU time 39.98 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:39 PM PDT 24
Peak memory 257292 kb
Host smart-9883326d-2f10-4570-87e9-9fef165b8a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14012
09874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1401209874
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3850814141
Short name T473
Test name
Test status
Simulation time 179600644 ps
CPU time 5.31 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 04:54:57 PM PDT 24
Peak memory 249552 kb
Host smart-0e3d47a9-e350-41d0-ac4e-1f229a333e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
14141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3850814141
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2104438205
Short name T619
Test name
Test status
Simulation time 33310633 ps
CPU time 4.98 seconds
Started Jul 09 04:54:46 PM PDT 24
Finished Jul 09 04:54:52 PM PDT 24
Peak memory 240988 kb
Host smart-a0e70f47-e80d-402a-a52c-38daf314e957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21044
38205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2104438205
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2203859377
Short name T431
Test name
Test status
Simulation time 221853666 ps
CPU time 26.67 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 248648 kb
Host smart-c9a13714-6f88-40bf-a3d7-cd5ed9e39d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22038
59377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2203859377
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3287857197
Short name T661
Test name
Test status
Simulation time 1187962523 ps
CPU time 32.46 seconds
Started Jul 09 04:54:44 PM PDT 24
Finished Jul 09 04:55:18 PM PDT 24
Peak memory 256772 kb
Host smart-04b623b7-359d-4c6a-a93b-bfa76cd3ebc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
57197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3287857197
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.413514281
Short name T460
Test name
Test status
Simulation time 4999631297 ps
CPU time 275.86 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:59:32 PM PDT 24
Peak memory 252568 kb
Host smart-a47bca3f-0c39-45e5-b718-eaf69347a419
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413514281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.413514281
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3498093693
Short name T663
Test name
Test status
Simulation time 66470739323 ps
CPU time 2065.53 seconds
Started Jul 09 04:54:50 PM PDT 24
Finished Jul 09 05:29:16 PM PDT 24
Peak memory 273296 kb
Host smart-dbee64b4-ef9b-4862-bb34-dd7370bb8f65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498093693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3498093693
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.720948052
Short name T675
Test name
Test status
Simulation time 2367275742 ps
CPU time 147.48 seconds
Started Jul 09 04:54:48 PM PDT 24
Finished Jul 09 04:57:16 PM PDT 24
Peak memory 256884 kb
Host smart-ff368055-8740-4908-87c1-26ab3d370091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72094
8052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.720948052
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2566424526
Short name T355
Test name
Test status
Simulation time 167724477 ps
CPU time 18.57 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:55:15 PM PDT 24
Peak memory 256432 kb
Host smart-ba8d6270-bd88-4223-aaba-9b1e6147767d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25664
24526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2566424526
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1602236609
Short name T318
Test name
Test status
Simulation time 10311334014 ps
CPU time 916.69 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 05:10:09 PM PDT 24
Peak memory 273764 kb
Host smart-e21b90ad-fbd8-467e-9f9f-eec6d6641729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602236609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1602236609
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.21457853
Short name T454
Test name
Test status
Simulation time 25292079413 ps
CPU time 648.81 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 05:05:38 PM PDT 24
Peak memory 265604 kb
Host smart-3eabc560-27ec-4c3d-a0c5-81d6198e0e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21457853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.21457853
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3251408899
Short name T667
Test name
Test status
Simulation time 33097074363 ps
CPU time 508.43 seconds
Started Jul 09 04:54:48 PM PDT 24
Finished Jul 09 05:03:17 PM PDT 24
Peak memory 249104 kb
Host smart-310e4a16-bf75-450e-a36f-f16a452a1c4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251408899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3251408899
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1169524207
Short name T602
Test name
Test status
Simulation time 465780929 ps
CPU time 20 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 04:55:10 PM PDT 24
Peak memory 249180 kb
Host smart-9f860ded-bb33-48a5-972e-23635aef2f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11695
24207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1169524207
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.803643252
Short name T400
Test name
Test status
Simulation time 1944835000 ps
CPU time 37.73 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 04:55:27 PM PDT 24
Peak memory 249444 kb
Host smart-00536559-4a2c-4485-8679-8dea8acf6970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80364
3252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.803643252
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1700596229
Short name T623
Test name
Test status
Simulation time 108679891 ps
CPU time 7.5 seconds
Started Jul 09 04:54:50 PM PDT 24
Finished Jul 09 04:54:58 PM PDT 24
Peak memory 249260 kb
Host smart-3d8b1b2e-3d9e-43ea-9fa7-97b19aff000d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005
96229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1700596229
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2923052857
Short name T543
Test name
Test status
Simulation time 863047614 ps
CPU time 29.8 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 257164 kb
Host smart-c4130181-fbd8-425e-9403-f4856d630dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
52857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2923052857
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2000349484
Short name T118
Test name
Test status
Simulation time 239166234479 ps
CPU time 3251.01 seconds
Started Jul 09 04:54:58 PM PDT 24
Finished Jul 09 05:49:11 PM PDT 24
Peak memory 298252 kb
Host smart-d9afa926-7cbc-4f0a-bfdb-42960b31a619
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000349484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2000349484
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3301148670
Short name T607
Test name
Test status
Simulation time 24404504776 ps
CPU time 1390.34 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 286940 kb
Host smart-760df5b9-f080-4bbf-9790-14164e613f4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301148670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3301148670
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1759937897
Short name T568
Test name
Test status
Simulation time 5564751330 ps
CPU time 143.34 seconds
Started Jul 09 04:54:48 PM PDT 24
Finished Jul 09 04:57:11 PM PDT 24
Peak memory 256880 kb
Host smart-ec4ade26-010a-4850-8d63-209460c5c691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17599
37897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1759937897
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3692247387
Short name T86
Test name
Test status
Simulation time 122552836 ps
CPU time 9.18 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 04:55:03 PM PDT 24
Peak memory 255504 kb
Host smart-2a157ee1-f382-4016-9269-02cf2807d632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36922
47387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3692247387
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2213434567
Short name T323
Test name
Test status
Simulation time 63092809489 ps
CPU time 1596.99 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:21:36 PM PDT 24
Peak memory 273092 kb
Host smart-4ef831ea-b545-44e9-b84d-4029068a99ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213434567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2213434567
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3138612481
Short name T669
Test name
Test status
Simulation time 18822157794 ps
CPU time 1115.24 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 05:13:27 PM PDT 24
Peak memory 282040 kb
Host smart-0f50f339-07da-4f3a-a9c1-1fbde68daca2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138612481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3138612481
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4049827131
Short name T659
Test name
Test status
Simulation time 63553502900 ps
CPU time 546.22 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 248232 kb
Host smart-4777b39b-9f74-49d6-9479-3adff062501f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049827131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4049827131
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2140594793
Short name T685
Test name
Test status
Simulation time 293759366 ps
CPU time 29.28 seconds
Started Jul 09 04:54:49 PM PDT 24
Finished Jul 09 04:55:19 PM PDT 24
Peak memory 256996 kb
Host smart-e6bb3505-0478-4830-8ed7-570b7243bd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405
94793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2140594793
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1036526655
Short name T427
Test name
Test status
Simulation time 1220852013 ps
CPU time 24.15 seconds
Started Jul 09 04:54:58 PM PDT 24
Finished Jul 09 04:55:24 PM PDT 24
Peak memory 249160 kb
Host smart-37e69102-4633-4928-ab27-8101554be357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10365
26655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1036526655
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4251660030
Short name T429
Test name
Test status
Simulation time 1385709550 ps
CPU time 54.49 seconds
Started Jul 09 04:54:51 PM PDT 24
Finished Jul 09 04:55:47 PM PDT 24
Peak memory 256872 kb
Host smart-fd573bbc-26c3-4959-a989-5620bd9407fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
60030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4251660030
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3346303762
Short name T566
Test name
Test status
Simulation time 7070564733 ps
CPU time 24.77 seconds
Started Jul 09 04:54:53 PM PDT 24
Finished Jul 09 04:55:19 PM PDT 24
Peak memory 256756 kb
Host smart-054600a5-6ae6-4d68-819a-1c0d469039ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
03762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3346303762
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.742179414
Short name T633
Test name
Test status
Simulation time 41532828569 ps
CPU time 328.78 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:00:27 PM PDT 24
Peak memory 256164 kb
Host smart-f2a3321d-394c-40d5-b85d-bc99ffd004ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742179414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.742179414
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.445068586
Short name T479
Test name
Test status
Simulation time 185141595275 ps
CPU time 2699.7 seconds
Started Jul 09 04:54:55 PM PDT 24
Finished Jul 09 05:39:56 PM PDT 24
Peak memory 289384 kb
Host smart-29969b48-4ddd-4cc2-b821-d506da83329f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445068586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.445068586
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1016995597
Short name T506
Test name
Test status
Simulation time 8297034480 ps
CPU time 103.78 seconds
Started Jul 09 04:55:00 PM PDT 24
Finished Jul 09 04:56:45 PM PDT 24
Peak memory 257496 kb
Host smart-6b5e7ea7-6b77-4e55-b35a-7e619102b6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10169
95597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1016995597
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.670201984
Short name T96
Test name
Test status
Simulation time 1723133912 ps
CPU time 41.57 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:41 PM PDT 24
Peak memory 248568 kb
Host smart-a52fbf37-33c5-4794-afc9-4bc76e58f362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67020
1984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.670201984
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.596359276
Short name T512
Test name
Test status
Simulation time 148203857840 ps
CPU time 2068.91 seconds
Started Jul 09 04:54:55 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 281648 kb
Host smart-6d417d2e-cbb7-4d1e-8a36-a70edaae1dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596359276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.596359276
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3828497151
Short name T509
Test name
Test status
Simulation time 96303137596 ps
CPU time 3254.59 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 05:49:12 PM PDT 24
Peak memory 290020 kb
Host smart-358a9703-9bb8-4b5e-b80b-6bec5bba3e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828497151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3828497151
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.553712521
Short name T585
Test name
Test status
Simulation time 4680237905 ps
CPU time 49.78 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:49 PM PDT 24
Peak memory 249252 kb
Host smart-c9e9c242-7fa7-41a0-b05a-69fc7718c743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55371
2521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.553712521
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1275128965
Short name T549
Test name
Test status
Simulation time 2109085721 ps
CPU time 58.48 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:55:56 PM PDT 24
Peak memory 248908 kb
Host smart-34b54956-10bc-4a92-b24c-dc9270569f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12751
28965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1275128965
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.876751521
Short name T387
Test name
Test status
Simulation time 720574695 ps
CPU time 47.46 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:55:44 PM PDT 24
Peak memory 257276 kb
Host smart-1dc4e8d9-b383-4966-83d5-a071b26d9819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87675
1521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.876751521
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.834146178
Short name T634
Test name
Test status
Simulation time 9033627056 ps
CPU time 860.32 seconds
Started Jul 09 04:54:59 PM PDT 24
Finished Jul 09 05:09:21 PM PDT 24
Peak memory 273948 kb
Host smart-7ec4f90b-68f1-4bb3-b74a-f23c2e647b12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834146178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.834146178
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.4089682593
Short name T16
Test name
Test status
Simulation time 18840226830 ps
CPU time 773.97 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 05:07:53 PM PDT 24
Peak memory 273928 kb
Host smart-8d409f96-4b13-4a00-9dd2-6d0cf22d865c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089682593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4089682593
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3724270499
Short name T555
Test name
Test status
Simulation time 88546681516 ps
CPU time 242.37 seconds
Started Jul 09 04:55:00 PM PDT 24
Finished Jul 09 04:59:03 PM PDT 24
Peak memory 256796 kb
Host smart-d2a3bd83-e14c-4a05-b568-76c3295de89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37242
70499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3724270499
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2982449028
Short name T632
Test name
Test status
Simulation time 3778097238 ps
CPU time 60.67 seconds
Started Jul 09 04:54:54 PM PDT 24
Finished Jul 09 04:55:55 PM PDT 24
Peak memory 249304 kb
Host smart-bb80556c-deb4-475a-a460-be978cb70f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29824
49028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2982449028
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1658137268
Short name T328
Test name
Test status
Simulation time 19383868290 ps
CPU time 1206.55 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 273424 kb
Host smart-7f9bce9e-004f-4366-b49c-af8eecaa950b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658137268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1658137268
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1904803045
Short name T694
Test name
Test status
Simulation time 137325897937 ps
CPU time 2123.06 seconds
Started Jul 09 04:55:02 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 289716 kb
Host smart-ae940f11-79d4-4bb8-931d-dab9bbd7d0cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904803045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1904803045
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3643609110
Short name T564
Test name
Test status
Simulation time 11342971313 ps
CPU time 480.47 seconds
Started Jul 09 04:55:00 PM PDT 24
Finished Jul 09 05:03:01 PM PDT 24
Peak memory 257196 kb
Host smart-6a8cb6d5-a4ca-4a2c-9ed3-b5eb88378ce9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643609110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3643609110
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.794079222
Short name T22
Test name
Test status
Simulation time 418848153 ps
CPU time 27.55 seconds
Started Jul 09 04:54:54 PM PDT 24
Finished Jul 09 04:55:22 PM PDT 24
Peak memory 256528 kb
Host smart-289665a9-6a38-42bf-af4f-c4c728ccb27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79407
9222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.794079222
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2190198917
Short name T392
Test name
Test status
Simulation time 444953965 ps
CPU time 24.72 seconds
Started Jul 09 04:54:56 PM PDT 24
Finished Jul 09 04:55:21 PM PDT 24
Peak memory 248752 kb
Host smart-47890352-e6cd-4366-bdc7-3d5d62ff4558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21901
98917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2190198917
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1040836970
Short name T610
Test name
Test status
Simulation time 630688172 ps
CPU time 24.52 seconds
Started Jul 09 04:54:55 PM PDT 24
Finished Jul 09 04:55:20 PM PDT 24
Peak memory 257256 kb
Host smart-88cdb382-55b3-4790-b4eb-aabd2e190126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408
36970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1040836970
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.863018685
Short name T365
Test name
Test status
Simulation time 518760976 ps
CPU time 21.47 seconds
Started Jul 09 04:54:55 PM PDT 24
Finished Jul 09 04:55:17 PM PDT 24
Peak memory 256364 kb
Host smart-bc765f25-1b67-4a52-a2d9-b7e2e4c8a55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86301
8685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.863018685
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3000302607
Short name T596
Test name
Test status
Simulation time 14091989157 ps
CPU time 1295.55 seconds
Started Jul 09 04:54:59 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 282076 kb
Host smart-2b0945cc-d728-4acf-9d57-39b87dd3e754
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000302607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3000302607
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.959373137
Short name T433
Test name
Test status
Simulation time 3903109381 ps
CPU time 266.43 seconds
Started Jul 09 04:55:03 PM PDT 24
Finished Jul 09 04:59:30 PM PDT 24
Peak memory 257484 kb
Host smart-86d10d39-a914-4488-856c-2b4b013ea885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95937
3137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.959373137
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.966026739
Short name T438
Test name
Test status
Simulation time 56612871 ps
CPU time 4.62 seconds
Started Jul 09 04:55:03 PM PDT 24
Finished Jul 09 04:55:08 PM PDT 24
Peak memory 249152 kb
Host smart-8649e27d-36d7-4ae1-85ef-7e7b797f92af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96602
6739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.966026739
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.493692753
Short name T676
Test name
Test status
Simulation time 23543566501 ps
CPU time 1435.47 seconds
Started Jul 09 04:55:01 PM PDT 24
Finished Jul 09 05:18:57 PM PDT 24
Peak memory 273716 kb
Host smart-a24e1035-255f-4cc0-8ad7-03cce9b237ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493692753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.493692753
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.4077897782
Short name T384
Test name
Test status
Simulation time 11376776708 ps
CPU time 962.03 seconds
Started Jul 09 04:55:01 PM PDT 24
Finished Jul 09 05:11:04 PM PDT 24
Peak memory 289260 kb
Host smart-9071acf0-bb87-4350-b012-c03bc222e35c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077897782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4077897782
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2105967610
Short name T397
Test name
Test status
Simulation time 694324489 ps
CPU time 42.36 seconds
Started Jul 09 04:55:00 PM PDT 24
Finished Jul 09 04:55:44 PM PDT 24
Peak memory 257220 kb
Host smart-2d81df93-655b-4ffa-989c-fb06864904a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21059
67610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2105967610
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4183925772
Short name T519
Test name
Test status
Simulation time 4425620640 ps
CPU time 61.4 seconds
Started Jul 09 04:55:05 PM PDT 24
Finished Jul 09 04:56:07 PM PDT 24
Peak memory 257520 kb
Host smart-b22d0673-aab9-4ab0-9a77-f1583a987f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41839
25772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4183925772
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2042729731
Short name T213
Test name
Test status
Simulation time 1893803356 ps
CPU time 61.2 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:56:00 PM PDT 24
Peak memory 256420 kb
Host smart-5274c654-a79d-4ba1-b458-eade13d4eff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20427
29731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2042729731
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.30964283
Short name T358
Test name
Test status
Simulation time 2887791192 ps
CPU time 45.4 seconds
Started Jul 09 04:55:12 PM PDT 24
Finished Jul 09 04:55:58 PM PDT 24
Peak memory 257420 kb
Host smart-642689ab-6bbb-43ca-9cb9-90ac90988854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30964
283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.30964283
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.65635149
Short name T21
Test name
Test status
Simulation time 5706239630 ps
CPU time 122.48 seconds
Started Jul 09 04:55:03 PM PDT 24
Finished Jul 09 04:57:06 PM PDT 24
Peak memory 257340 kb
Host smart-6c5d21e3-e516-424a-9175-42b1569546ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65635149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_hand
ler_stress_all.65635149
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2063918349
Short name T94
Test name
Test status
Simulation time 13104443891 ps
CPU time 820.76 seconds
Started Jul 09 04:55:01 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 270272 kb
Host smart-de5d8a86-09b4-4b4b-95b5-2b0fa91e897a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063918349 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2063918349
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.361906159
Short name T123
Test name
Test status
Simulation time 43222723116 ps
CPU time 1384.86 seconds
Started Jul 09 04:54:59 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 273148 kb
Host smart-8f3841e7-2b3e-410a-a7d1-0c5ef069b841
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361906159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.361906159
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3616647247
Short name T702
Test name
Test status
Simulation time 170872877 ps
CPU time 5.16 seconds
Started Jul 09 04:55:04 PM PDT 24
Finished Jul 09 04:55:10 PM PDT 24
Peak memory 251616 kb
Host smart-66e89be3-548b-45e2-9af2-ffa6cff55e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
47247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3616647247
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1007459544
Short name T435
Test name
Test status
Simulation time 171495283 ps
CPU time 15.1 seconds
Started Jul 09 04:54:58 PM PDT 24
Finished Jul 09 04:55:15 PM PDT 24
Peak memory 256332 kb
Host smart-770c3c86-6114-40ed-974e-326180534df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10074
59544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1007459544
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2703900033
Short name T207
Test name
Test status
Simulation time 118895918231 ps
CPU time 1959.98 seconds
Started Jul 09 04:55:05 PM PDT 24
Finished Jul 09 05:27:46 PM PDT 24
Peak memory 286852 kb
Host smart-ce48ad25-44f8-4853-b835-ba370b09c36f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703900033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2703900033
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1153936099
Short name T309
Test name
Test status
Simulation time 5255909443 ps
CPU time 217.16 seconds
Started Jul 09 04:55:05 PM PDT 24
Finished Jul 09 04:58:42 PM PDT 24
Peak memory 248152 kb
Host smart-ad613ef2-f7d9-4f9b-8609-d630ec6272c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153936099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1153936099
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.899870400
Short name T529
Test name
Test status
Simulation time 83712088 ps
CPU time 9.85 seconds
Started Jul 09 04:54:59 PM PDT 24
Finished Jul 09 04:55:10 PM PDT 24
Peak memory 249124 kb
Host smart-8a91b037-be21-4e13-93cc-324f03e2d290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89987
0400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.899870400
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3575718727
Short name T657
Test name
Test status
Simulation time 649076543 ps
CPU time 39.31 seconds
Started Jul 09 04:54:58 PM PDT 24
Finished Jul 09 04:55:39 PM PDT 24
Peak memory 249148 kb
Host smart-a7121f68-34a2-4977-9410-b1bdfa5303f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35757
18727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3575718727
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3858853583
Short name T288
Test name
Test status
Simulation time 1075322614 ps
CPU time 21.51 seconds
Started Jul 09 04:55:04 PM PDT 24
Finished Jul 09 04:55:26 PM PDT 24
Peak memory 257272 kb
Host smart-25410001-632a-47e6-a957-87bd29bf0c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
53583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3858853583
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1049904587
Short name T419
Test name
Test status
Simulation time 90379109 ps
CPU time 4.41 seconds
Started Jul 09 04:54:57 PM PDT 24
Finished Jul 09 04:55:03 PM PDT 24
Peak memory 249660 kb
Host smart-e78a8730-6a0f-4bf5-97aa-819d58a49dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10499
04587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1049904587
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2880846046
Short name T54
Test name
Test status
Simulation time 172192212374 ps
CPU time 4910.99 seconds
Started Jul 09 04:55:08 PM PDT 24
Finished Jul 09 06:17:00 PM PDT 24
Peak memory 355812 kb
Host smart-9684b44b-d05c-439b-ae93-4bfe64937572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880846046 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2880846046
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3765415396
Short name T703
Test name
Test status
Simulation time 49730374716 ps
CPU time 2942.18 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 05:44:12 PM PDT 24
Peak memory 289172 kb
Host smart-61807991-3e4b-4584-a786-057fa5df0202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765415396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3765415396
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1893585423
Short name T193
Test name
Test status
Simulation time 3467194988 ps
CPU time 153.93 seconds
Started Jul 09 04:55:04 PM PDT 24
Finished Jul 09 04:57:39 PM PDT 24
Peak memory 256676 kb
Host smart-8d282d28-4f04-4b3a-8cdd-864a02303328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18935
85423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1893585423
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2089325727
Short name T381
Test name
Test status
Simulation time 417596422 ps
CPU time 19.38 seconds
Started Jul 09 04:55:10 PM PDT 24
Finished Jul 09 04:55:30 PM PDT 24
Peak memory 248564 kb
Host smart-14947177-f5a7-4fcf-8187-6e6c21eb13d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20893
25727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2089325727
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1857110552
Short name T648
Test name
Test status
Simulation time 61028817153 ps
CPU time 1115.03 seconds
Started Jul 09 04:55:02 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 273644 kb
Host smart-d3311a5e-7c73-4f6f-bd78-0a74d131a2c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857110552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1857110552
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1873722053
Short name T103
Test name
Test status
Simulation time 158412904739 ps
CPU time 1577.9 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 05:21:27 PM PDT 24
Peak memory 273836 kb
Host smart-4ab4780f-a01a-4c58-814c-3352cdc5fff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873722053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1873722053
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1101935914
Short name T127
Test name
Test status
Simulation time 177256109 ps
CPU time 7.66 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 04:55:17 PM PDT 24
Peak memory 249164 kb
Host smart-e36fe80c-75ce-47f1-b620-e3d7adaef40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019
35914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1101935914
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.80735546
Short name T452
Test name
Test status
Simulation time 654750891 ps
CPU time 44.42 seconds
Started Jul 09 04:55:07 PM PDT 24
Finished Jul 09 04:55:52 PM PDT 24
Peak memory 249112 kb
Host smart-45d88c17-42b7-4edf-bf77-c2ee986b884d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80735
546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.80735546
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3226757377
Short name T272
Test name
Test status
Simulation time 398628175 ps
CPU time 14.08 seconds
Started Jul 09 04:55:02 PM PDT 24
Finished Jul 09 04:55:16 PM PDT 24
Peak memory 249276 kb
Host smart-c896ca67-ad61-44f6-b3c1-00d58e8b52b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32267
57377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3226757377
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.4159786979
Short name T597
Test name
Test status
Simulation time 81370536 ps
CPU time 5.29 seconds
Started Jul 09 04:55:05 PM PDT 24
Finished Jul 09 04:55:10 PM PDT 24
Peak memory 252212 kb
Host smart-ff7688a5-f964-4c83-9d8d-349571a8c4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
86979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.4159786979
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3058934869
Short name T422
Test name
Test status
Simulation time 694759433 ps
CPU time 63.68 seconds
Started Jul 09 04:55:04 PM PDT 24
Finished Jul 09 04:56:09 PM PDT 24
Peak memory 257444 kb
Host smart-d121c4fd-e22a-4e2f-8466-07ccc2df55c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058934869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3058934869
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2828893123
Short name T57
Test name
Test status
Simulation time 28762213585 ps
CPU time 1722.43 seconds
Started Jul 09 04:55:10 PM PDT 24
Finished Jul 09 05:23:53 PM PDT 24
Peak memory 305856 kb
Host smart-c7abab93-42a0-47cf-b4e6-d99bc6d1a450
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828893123 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2828893123
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3521836859
Short name T52
Test name
Test status
Simulation time 77745560024 ps
CPU time 1454.24 seconds
Started Jul 09 04:55:03 PM PDT 24
Finished Jul 09 05:19:18 PM PDT 24
Peak memory 273876 kb
Host smart-a5cd4535-7308-4ad8-8d14-8e2d4eeb5ed3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521836859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3521836859
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2708193957
Short name T72
Test name
Test status
Simulation time 543921502 ps
CPU time 53.24 seconds
Started Jul 09 04:55:10 PM PDT 24
Finished Jul 09 04:56:03 PM PDT 24
Peak memory 256832 kb
Host smart-d4c79090-ab9f-4454-9072-61841c73a966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
93957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2708193957
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1800728767
Short name T616
Test name
Test status
Simulation time 1116344817 ps
CPU time 26.76 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 04:55:37 PM PDT 24
Peak memory 249120 kb
Host smart-06a37679-26fc-4ba9-b35f-cee6ed14282b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18007
28767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1800728767
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.552293135
Short name T573
Test name
Test status
Simulation time 89556659151 ps
CPU time 1045.3 seconds
Started Jul 09 04:55:07 PM PDT 24
Finished Jul 09 05:12:33 PM PDT 24
Peak memory 273744 kb
Host smart-6b9f66be-2c14-443f-b87f-fbd2a08e60e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552293135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.552293135
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.193628138
Short name T395
Test name
Test status
Simulation time 32487170642 ps
CPU time 2021.52 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 273620 kb
Host smart-88c417cf-e519-432b-b470-cc69c4932fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193628138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.193628138
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1562510372
Short name T239
Test name
Test status
Simulation time 198341206 ps
CPU time 13.93 seconds
Started Jul 09 04:55:04 PM PDT 24
Finished Jul 09 04:55:18 PM PDT 24
Peak memory 249128 kb
Host smart-c27be9f7-61ea-4899-a974-c13efdf4561d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
10372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1562510372
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2675830520
Short name T537
Test name
Test status
Simulation time 993923156 ps
CPU time 29.03 seconds
Started Jul 09 04:55:09 PM PDT 24
Finished Jul 09 04:55:38 PM PDT 24
Peak memory 256832 kb
Host smart-212dfca8-f671-4473-9dac-c2cf2c01f6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
30520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2675830520
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3307954206
Short name T571
Test name
Test status
Simulation time 151735091 ps
CPU time 18 seconds
Started Jul 09 04:55:03 PM PDT 24
Finished Jul 09 04:55:21 PM PDT 24
Peak memory 248600 kb
Host smart-cdd5a116-b595-4dad-a3b6-a3869a8b84c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33079
54206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3307954206
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2169862630
Short name T374
Test name
Test status
Simulation time 3997129103 ps
CPU time 57.96 seconds
Started Jul 09 04:55:03 PM PDT 24
Finished Jul 09 04:56:01 PM PDT 24
Peak memory 257096 kb
Host smart-02573cad-501d-41fb-b24a-48ec80bb62e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21698
62630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2169862630
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1362725553
Short name T92
Test name
Test status
Simulation time 183459375589 ps
CPU time 3354.26 seconds
Started Jul 09 04:55:06 PM PDT 24
Finished Jul 09 05:51:01 PM PDT 24
Peak memory 305828 kb
Host smart-e33aee6f-0ce8-446f-8246-bcf560bc4d22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362725553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1362725553
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1260045454
Short name T244
Test name
Test status
Simulation time 14127393834 ps
CPU time 866.06 seconds
Started Jul 09 04:55:08 PM PDT 24
Finished Jul 09 05:09:35 PM PDT 24
Peak memory 265808 kb
Host smart-85f0ebe1-0e89-4b46-a6fd-c1699fa52f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260045454 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1260045454
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2215694084
Short name T441
Test name
Test status
Simulation time 17946794103 ps
CPU time 964.6 seconds
Started Jul 09 04:55:11 PM PDT 24
Finished Jul 09 05:11:16 PM PDT 24
Peak memory 281540 kb
Host smart-6568a4d7-2e42-4b1d-876c-743fd55a0e7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215694084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2215694084
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3439022392
Short name T587
Test name
Test status
Simulation time 7971295100 ps
CPU time 185.64 seconds
Started Jul 09 04:55:14 PM PDT 24
Finished Jul 09 04:58:20 PM PDT 24
Peak memory 257004 kb
Host smart-0319f461-4259-4a46-86e5-7b5accf359ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
22392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3439022392
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1618610693
Short name T457
Test name
Test status
Simulation time 441252104 ps
CPU time 17.33 seconds
Started Jul 09 04:55:11 PM PDT 24
Finished Jul 09 04:55:29 PM PDT 24
Peak memory 248624 kb
Host smart-9010b16f-bf50-414b-8fe1-7facfd7944f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16186
10693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1618610693
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2141716605
Short name T641
Test name
Test status
Simulation time 15293002656 ps
CPU time 1589.19 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 05:21:44 PM PDT 24
Peak memory 290100 kb
Host smart-18dd3223-dc35-4715-8d62-c3cb4aad8e55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141716605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2141716605
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1461632564
Short name T268
Test name
Test status
Simulation time 90328565219 ps
CPU time 1491.26 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 05:20:05 PM PDT 24
Peak memory 273304 kb
Host smart-260ee427-978b-4165-a9b2-97a566bb3ec0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461632564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1461632564
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1507723627
Short name T305
Test name
Test status
Simulation time 27796825462 ps
CPU time 607.83 seconds
Started Jul 09 04:55:14 PM PDT 24
Finished Jul 09 05:05:26 PM PDT 24
Peak memory 249252 kb
Host smart-42c5d882-6fa5-4ef0-81a2-f87e0d669f75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507723627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1507723627
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4217603452
Short name T129
Test name
Test status
Simulation time 1260208922 ps
CPU time 36.85 seconds
Started Jul 09 04:55:07 PM PDT 24
Finished Jul 09 04:55:44 PM PDT 24
Peak memory 249184 kb
Host smart-e6f537d5-4f3c-4539-8714-230a4b5e33e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42176
03452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4217603452
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.226136419
Short name T611
Test name
Test status
Simulation time 3231514557 ps
CPU time 58.99 seconds
Started Jul 09 04:55:08 PM PDT 24
Finished Jul 09 04:56:08 PM PDT 24
Peak memory 248976 kb
Host smart-8f57ec3b-2dcc-47e1-a559-1f6ff1c81d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22613
6419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.226136419
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1538542870
Short name T577
Test name
Test status
Simulation time 1169236285 ps
CPU time 9.79 seconds
Started Jul 09 04:55:14 PM PDT 24
Finished Jul 09 04:55:24 PM PDT 24
Peak memory 255544 kb
Host smart-0683416c-ea82-4a4c-b0a9-0f5af6f0de8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15385
42870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1538542870
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2272510792
Short name T559
Test name
Test status
Simulation time 332163610 ps
CPU time 13.8 seconds
Started Jul 09 04:55:07 PM PDT 24
Finished Jul 09 04:55:21 PM PDT 24
Peak memory 256276 kb
Host smart-5fb68e86-1b93-4d23-9688-865820772760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22725
10792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2272510792
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.188501924
Short name T700
Test name
Test status
Simulation time 1231848150824 ps
CPU time 8297.8 seconds
Started Jul 09 04:55:14 PM PDT 24
Finished Jul 09 07:13:33 PM PDT 24
Peak memory 347492 kb
Host smart-7757c676-e2c2-4025-8c52-d71cb63d396d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188501924 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.188501924
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3713915390
Short name T229
Test name
Test status
Simulation time 37588885 ps
CPU time 2.88 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 04:54:19 PM PDT 24
Peak memory 249380 kb
Host smart-e0090cf6-9bba-40f4-b245-4bba64153028
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3713915390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3713915390
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1716475939
Short name T426
Test name
Test status
Simulation time 320982096420 ps
CPU time 1918.68 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 05:26:15 PM PDT 24
Peak memory 282160 kb
Host smart-b3231246-c92a-49a3-ad9b-489299e18f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716475939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1716475939
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.995673713
Short name T646
Test name
Test status
Simulation time 3983794659 ps
CPU time 41.87 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 04:54:58 PM PDT 24
Peak memory 249272 kb
Host smart-3193fd3a-084a-497d-a5bc-b7c81c249696
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=995673713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.995673713
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2411546629
Short name T111
Test name
Test status
Simulation time 1883045319 ps
CPU time 141.18 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 04:56:38 PM PDT 24
Peak memory 256868 kb
Host smart-7ebd5768-065f-4cdb-b883-988676c944b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
46629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2411546629
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.799285142
Short name T533
Test name
Test status
Simulation time 208363874 ps
CPU time 21.09 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 04:54:44 PM PDT 24
Peak memory 248672 kb
Host smart-def25fa5-9fd3-4603-b738-d192cdbbc907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79928
5142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.799285142
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2174611307
Short name T291
Test name
Test status
Simulation time 38421228740 ps
CPU time 2003.16 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 05:27:42 PM PDT 24
Peak memory 290208 kb
Host smart-e54abe26-268c-4c62-aa40-28521ac92445
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174611307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2174611307
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.765003935
Short name T515
Test name
Test status
Simulation time 33604956930 ps
CPU time 2321.53 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 05:32:58 PM PDT 24
Peak memory 288232 kb
Host smart-8658f8d5-c6a8-4ff6-8c32-bbcdaf5a37d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765003935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.765003935
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3044461187
Short name T294
Test name
Test status
Simulation time 26395362828 ps
CPU time 299.61 seconds
Started Jul 09 04:54:14 PM PDT 24
Finished Jul 09 04:59:15 PM PDT 24
Peak memory 249124 kb
Host smart-f3b65728-806f-4a30-8d95-9f11361ecfbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044461187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3044461187
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4040944611
Short name T377
Test name
Test status
Simulation time 1264265692 ps
CPU time 9.91 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:28 PM PDT 24
Peak memory 249124 kb
Host smart-56336687-e8c4-4b77-94ab-fcac3a94f823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409
44611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4040944611
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.710078843
Short name T530
Test name
Test status
Simulation time 180381585 ps
CPU time 25.61 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:39 PM PDT 24
Peak memory 248692 kb
Host smart-c8c18eb9-b1a8-4506-8b11-859c6078031f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71007
8843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.710078843
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2293253319
Short name T40
Test name
Test status
Simulation time 803251131 ps
CPU time 27.05 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:41 PM PDT 24
Peak memory 271604 kb
Host smart-9d1f19a5-5e9d-4f00-b3b3-c2686536a251
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2293253319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2293253319
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2091014548
Short name T498
Test name
Test status
Simulation time 7975268427 ps
CPU time 57.79 seconds
Started Jul 09 04:54:12 PM PDT 24
Finished Jul 09 04:55:11 PM PDT 24
Peak memory 257196 kb
Host smart-61eb906d-fc82-40ad-8809-1a64fdc8a7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20910
14548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2091014548
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2832603917
Short name T436
Test name
Test status
Simulation time 277397676 ps
CPU time 16.01 seconds
Started Jul 09 04:54:14 PM PDT 24
Finished Jul 09 04:54:31 PM PDT 24
Peak memory 255440 kb
Host smart-406594b6-4f24-4240-94e1-9e3947a628e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
03917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2832603917
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3519240727
Short name T652
Test name
Test status
Simulation time 22569471903 ps
CPU time 640.92 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 05:05:55 PM PDT 24
Peak memory 273952 kb
Host smart-24855276-075a-4115-9727-2760336df515
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519240727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3519240727
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3617882813
Short name T582
Test name
Test status
Simulation time 24949094118 ps
CPU time 121.58 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 04:57:16 PM PDT 24
Peak memory 257524 kb
Host smart-1d299fac-4112-415c-8b5e-92c023031de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
82813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3617882813
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2464345211
Short name T351
Test name
Test status
Simulation time 267490052 ps
CPU time 16.6 seconds
Started Jul 09 04:55:10 PM PDT 24
Finished Jul 09 04:55:27 PM PDT 24
Peak memory 255400 kb
Host smart-d430ea2d-9c9b-4ff9-b9a1-6dffc85f58e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24643
45211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2464345211
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2364840221
Short name T83
Test name
Test status
Simulation time 15420756167 ps
CPU time 1180.87 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 284372 kb
Host smart-24c82807-8922-4256-a218-6a0518fd988d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364840221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2364840221
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3674589522
Short name T8
Test name
Test status
Simulation time 26319907757 ps
CPU time 604.47 seconds
Started Jul 09 04:55:19 PM PDT 24
Finished Jul 09 05:05:24 PM PDT 24
Peak memory 266740 kb
Host smart-05d83c39-7a17-4b5d-934b-4861138e9b1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674589522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3674589522
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4268756200
Short name T254
Test name
Test status
Simulation time 5147481484 ps
CPU time 212.82 seconds
Started Jul 09 04:55:11 PM PDT 24
Finished Jul 09 04:58:45 PM PDT 24
Peak memory 249280 kb
Host smart-f259096a-5575-410a-be96-503d7a563042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268756200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4268756200
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1624562803
Short name T273
Test name
Test status
Simulation time 767127320 ps
CPU time 46.66 seconds
Started Jul 09 04:55:14 PM PDT 24
Finished Jul 09 04:56:01 PM PDT 24
Peak memory 249160 kb
Host smart-10bee422-b1fa-494d-890e-453e51f78b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
62803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1624562803
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4167568377
Short name T360
Test name
Test status
Simulation time 663266366 ps
CPU time 7.05 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 04:55:20 PM PDT 24
Peak memory 254668 kb
Host smart-febb004f-eb94-4870-a7c7-5a888ab0dfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41675
68377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4167568377
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3730578923
Short name T284
Test name
Test status
Simulation time 398503383 ps
CPU time 24.91 seconds
Started Jul 09 04:55:13 PM PDT 24
Finished Jul 09 04:55:39 PM PDT 24
Peak memory 249156 kb
Host smart-74eb7b00-0655-404e-a0c4-84a4a0d5f6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
78923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3730578923
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2286215787
Short name T349
Test name
Test status
Simulation time 152962107 ps
CPU time 12.65 seconds
Started Jul 09 04:55:11 PM PDT 24
Finished Jul 09 04:55:24 PM PDT 24
Peak memory 255772 kb
Host smart-76921fc1-d7ed-422f-8edc-d25c18a6fd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
15787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2286215787
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3056468574
Short name T390
Test name
Test status
Simulation time 14652843355 ps
CPU time 1494.19 seconds
Started Jul 09 04:55:17 PM PDT 24
Finished Jul 09 05:20:12 PM PDT 24
Peak memory 290184 kb
Host smart-b5c5fd86-4771-4256-b9f7-5614e580ec3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056468574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3056468574
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2293497026
Short name T487
Test name
Test status
Simulation time 1985285045 ps
CPU time 161.7 seconds
Started Jul 09 04:55:17 PM PDT 24
Finished Jul 09 04:57:59 PM PDT 24
Peak memory 256640 kb
Host smart-e72ecf41-6888-4cb4-88b0-33aacee4e81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22934
97026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2293497026
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2891280447
Short name T507
Test name
Test status
Simulation time 2749107732 ps
CPU time 55.09 seconds
Started Jul 09 04:55:17 PM PDT 24
Finished Jul 09 04:56:13 PM PDT 24
Peak memory 257068 kb
Host smart-6fcc8d29-da14-4c30-ba3a-255e1555074f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28912
80447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2891280447
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1635219933
Short name T331
Test name
Test status
Simulation time 114081527921 ps
CPU time 1989.53 seconds
Started Jul 09 04:55:15 PM PDT 24
Finished Jul 09 05:28:25 PM PDT 24
Peak memory 273728 kb
Host smart-ac0a89b2-f9a2-40fb-b9ad-c948506593f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635219933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1635219933
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.633213327
Short name T692
Test name
Test status
Simulation time 27545278361 ps
CPU time 1202.09 seconds
Started Jul 09 04:55:17 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 267584 kb
Host smart-acbf6d1b-7cee-496a-87e6-6eb89ba04a16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633213327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.633213327
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1729152068
Short name T673
Test name
Test status
Simulation time 1845013714 ps
CPU time 83.51 seconds
Started Jul 09 04:55:15 PM PDT 24
Finished Jul 09 04:56:40 PM PDT 24
Peak memory 255428 kb
Host smart-3fbb0e2c-cfef-4ca9-bf1f-aaead1686b42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729152068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1729152068
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2377607006
Short name T417
Test name
Test status
Simulation time 997257234 ps
CPU time 37.85 seconds
Started Jul 09 04:55:16 PM PDT 24
Finished Jul 09 04:55:55 PM PDT 24
Peak memory 256572 kb
Host smart-7143f03d-4564-44ff-b5c5-ecbb3619b73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
07006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2377607006
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3806952377
Short name T445
Test name
Test status
Simulation time 84698780 ps
CPU time 17.83 seconds
Started Jul 09 04:55:17 PM PDT 24
Finished Jul 09 04:55:36 PM PDT 24
Peak memory 249040 kb
Host smart-b9fde031-fdfb-4302-9773-41276a5a9559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38069
52377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3806952377
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.145153351
Short name T262
Test name
Test status
Simulation time 585508902 ps
CPU time 23.45 seconds
Started Jul 09 04:55:15 PM PDT 24
Finished Jul 09 04:55:39 PM PDT 24
Peak memory 255360 kb
Host smart-b68be517-e134-4dde-bd0f-7b961b7f3e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14515
3351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.145153351
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3292398782
Short name T630
Test name
Test status
Simulation time 743768322 ps
CPU time 48.55 seconds
Started Jul 09 04:55:18 PM PDT 24
Finished Jul 09 04:56:07 PM PDT 24
Peak memory 249100 kb
Host smart-95a2ae89-bc0d-4bda-949d-559ca465b562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32923
98782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3292398782
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2311063621
Short name T517
Test name
Test status
Simulation time 2843442348 ps
CPU time 173.85 seconds
Started Jul 09 04:55:16 PM PDT 24
Finished Jul 09 04:58:11 PM PDT 24
Peak memory 257404 kb
Host smart-17472da8-4099-4cd8-8a5e-06af96116a17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311063621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2311063621
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1740502931
Short name T495
Test name
Test status
Simulation time 156111071610 ps
CPU time 1985.58 seconds
Started Jul 09 04:55:18 PM PDT 24
Finished Jul 09 05:28:24 PM PDT 24
Peak memory 286168 kb
Host smart-6aa67832-0fdd-48cf-a469-dbcb55be1563
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740502931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1740502931
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1214194921
Short name T385
Test name
Test status
Simulation time 3626360512 ps
CPU time 165.35 seconds
Started Jul 09 04:55:15 PM PDT 24
Finished Jul 09 04:58:01 PM PDT 24
Peak memory 257556 kb
Host smart-f27bd4a7-f4a8-47e1-8bcb-47eb8787e0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
94921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1214194921
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3642289469
Short name T428
Test name
Test status
Simulation time 229504635 ps
CPU time 16.78 seconds
Started Jul 09 04:55:16 PM PDT 24
Finished Jul 09 04:55:33 PM PDT 24
Peak memory 249080 kb
Host smart-c8673a74-d071-494f-a28c-06a56262e5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
89469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3642289469
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2096367086
Short name T677
Test name
Test status
Simulation time 14759772864 ps
CPU time 1148.49 seconds
Started Jul 09 04:55:16 PM PDT 24
Finished Jul 09 05:14:26 PM PDT 24
Peak memory 289624 kb
Host smart-bc753914-30df-4965-8f26-b0c6b5277778
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096367086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2096367086
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1661925106
Short name T401
Test name
Test status
Simulation time 52931583564 ps
CPU time 2940.12 seconds
Started Jul 09 04:55:21 PM PDT 24
Finished Jul 09 05:44:22 PM PDT 24
Peak memory 288912 kb
Host smart-5fecf25c-5d32-42f7-88f0-105070b2849f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661925106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1661925106
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.659584812
Short name T301
Test name
Test status
Simulation time 105083356393 ps
CPU time 304.75 seconds
Started Jul 09 04:55:17 PM PDT 24
Finished Jul 09 05:00:22 PM PDT 24
Peak memory 249268 kb
Host smart-c85408d3-bca3-4877-90e9-6e7cc653d13c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659584812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.659584812
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.231318898
Short name T205
Test name
Test status
Simulation time 2320006924 ps
CPU time 42.61 seconds
Started Jul 09 04:55:18 PM PDT 24
Finished Jul 09 04:56:01 PM PDT 24
Peak memory 256828 kb
Host smart-0129574f-8bb0-4730-865c-a1a0e8caea2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23131
8898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.231318898
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.863217914
Short name T356
Test name
Test status
Simulation time 905427695 ps
CPU time 54.93 seconds
Started Jul 09 04:55:19 PM PDT 24
Finished Jul 09 04:56:15 PM PDT 24
Peak memory 257336 kb
Host smart-9fef0267-6b4e-4eeb-b127-9a06e8eaeb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86321
7914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.863217914
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3032717504
Short name T541
Test name
Test status
Simulation time 2857156023 ps
CPU time 43.58 seconds
Started Jul 09 04:55:16 PM PDT 24
Finished Jul 09 04:56:01 PM PDT 24
Peak memory 257016 kb
Host smart-9bdc8c37-81d4-4e3e-a1ae-874fc3d99402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327
17504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3032717504
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2936816486
Short name T372
Test name
Test status
Simulation time 4250514825 ps
CPU time 38.17 seconds
Started Jul 09 04:55:19 PM PDT 24
Finished Jul 09 04:55:58 PM PDT 24
Peak memory 257548 kb
Host smart-69c93ff1-51d8-4eba-8ef1-e6232ad35df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29368
16486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2936816486
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.78743045
Short name T246
Test name
Test status
Simulation time 1508592894345 ps
CPU time 7378.33 seconds
Started Jul 09 04:55:23 PM PDT 24
Finished Jul 09 06:58:23 PM PDT 24
Peak memory 322796 kb
Host smart-0a738c89-aac9-43f5-bea1-d1a5483eb475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78743045 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.78743045
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3372635916
Short name T525
Test name
Test status
Simulation time 53740779044 ps
CPU time 1255.38 seconds
Started Jul 09 04:55:21 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 290012 kb
Host smart-78624ffd-5080-457c-9404-6ace204c8f0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372635916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3372635916
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.604383680
Short name T28
Test name
Test status
Simulation time 387581775 ps
CPU time 6.39 seconds
Started Jul 09 04:55:20 PM PDT 24
Finished Jul 09 04:55:27 PM PDT 24
Peak memory 255208 kb
Host smart-59c174a6-fa0b-4de0-80d8-fca7f5a23502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60438
3680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.604383680
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2182311461
Short name T670
Test name
Test status
Simulation time 596548165 ps
CPU time 21.24 seconds
Started Jul 09 04:55:20 PM PDT 24
Finished Jul 09 04:55:42 PM PDT 24
Peak memory 249540 kb
Host smart-69a51cb3-6cd0-44a0-be56-660d20c71e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21823
11461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2182311461
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.593335209
Short name T325
Test name
Test status
Simulation time 14103438066 ps
CPU time 1115.16 seconds
Started Jul 09 04:55:26 PM PDT 24
Finished Jul 09 05:14:02 PM PDT 24
Peak memory 273136 kb
Host smart-1c0eac44-109c-41c7-b633-cd9829c40884
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593335209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.593335209
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3064952134
Short name T546
Test name
Test status
Simulation time 30646635801 ps
CPU time 2023.3 seconds
Started Jul 09 04:55:25 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 286288 kb
Host smart-288554cf-9540-40df-97d8-22975899d039
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064952134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3064952134
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4197500041
Short name T310
Test name
Test status
Simulation time 10180704125 ps
CPU time 429.85 seconds
Started Jul 09 04:55:28 PM PDT 24
Finished Jul 09 05:02:39 PM PDT 24
Peak memory 249244 kb
Host smart-936e8a73-5034-423c-9ebc-4bde8fe34f76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197500041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4197500041
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1029723830
Short name T59
Test name
Test status
Simulation time 3774870511 ps
CPU time 53.57 seconds
Started Jul 09 04:55:21 PM PDT 24
Finished Jul 09 04:56:15 PM PDT 24
Peak memory 256648 kb
Host smart-42674a1e-c7d5-4434-b34b-0940ac2191ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10297
23830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1029723830
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1515985450
Short name T64
Test name
Test status
Simulation time 1911126884 ps
CPU time 58.26 seconds
Started Jul 09 04:55:23 PM PDT 24
Finished Jul 09 04:56:22 PM PDT 24
Peak memory 250284 kb
Host smart-4b559d28-92f0-4cf3-bf5a-c817394713e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
85450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1515985450
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1619213668
Short name T125
Test name
Test status
Simulation time 214804968 ps
CPU time 35.01 seconds
Started Jul 09 04:55:21 PM PDT 24
Finished Jul 09 04:55:56 PM PDT 24
Peak memory 249084 kb
Host smart-84fb446c-d05c-4245-bd15-d5f59e5d065b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16192
13668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1619213668
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.830213880
Short name T557
Test name
Test status
Simulation time 3949228609 ps
CPU time 33.25 seconds
Started Jul 09 04:55:21 PM PDT 24
Finished Jul 09 04:55:55 PM PDT 24
Peak memory 249708 kb
Host smart-154a9265-9c26-4fd6-a71a-19970617310f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83021
3880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.830213880
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2657483986
Short name T539
Test name
Test status
Simulation time 2291970068 ps
CPU time 259.95 seconds
Started Jul 09 04:55:26 PM PDT 24
Finished Jul 09 04:59:47 PM PDT 24
Peak memory 257392 kb
Host smart-6b245cd8-50d9-4682-af51-2d4c317c74c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657483986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2657483986
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.498737433
Short name T701
Test name
Test status
Simulation time 202921177413 ps
CPU time 3219.72 seconds
Started Jul 09 04:55:24 PM PDT 24
Finished Jul 09 05:49:05 PM PDT 24
Peak memory 290208 kb
Host smart-8c6632d6-f946-48c9-8cfa-ae0ef104ee8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498737433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.498737433
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2342422066
Short name T348
Test name
Test status
Simulation time 2471141494 ps
CPU time 136.75 seconds
Started Jul 09 04:55:23 PM PDT 24
Finished Jul 09 04:57:41 PM PDT 24
Peak memory 257436 kb
Host smart-bcf37dab-24e0-461d-992d-78c138001554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
22066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2342422066
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.985353393
Short name T560
Test name
Test status
Simulation time 343646632 ps
CPU time 3.73 seconds
Started Jul 09 04:55:30 PM PDT 24
Finished Jul 09 04:55:35 PM PDT 24
Peak memory 240896 kb
Host smart-d40f0a4b-9b36-4bee-ab1a-14e0d94ac5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98535
3393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.985353393
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.144758119
Short name T322
Test name
Test status
Simulation time 11417093659 ps
CPU time 881.71 seconds
Started Jul 09 04:55:23 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 272812 kb
Host smart-c83f0d99-b7cd-432f-92b7-54b732b4e4e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144758119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.144758119
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1799180013
Short name T462
Test name
Test status
Simulation time 33753899455 ps
CPU time 867.15 seconds
Started Jul 09 04:55:24 PM PDT 24
Finished Jul 09 05:09:52 PM PDT 24
Peak memory 273904 kb
Host smart-f60023c3-c000-4749-b8cc-373b5ff42289
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799180013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1799180013
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.71170401
Short name T116
Test name
Test status
Simulation time 5480105506 ps
CPU time 235.23 seconds
Started Jul 09 04:55:28 PM PDT 24
Finished Jul 09 04:59:23 PM PDT 24
Peak memory 249080 kb
Host smart-cd155e0d-b7a0-43f9-9f15-0bdc3cd5f240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71170401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.71170401
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1863322975
Short name T556
Test name
Test status
Simulation time 257927294 ps
CPU time 18.36 seconds
Started Jul 09 04:55:26 PM PDT 24
Finished Jul 09 04:55:45 PM PDT 24
Peak memory 256572 kb
Host smart-8c4254b8-0d7b-40de-9dbf-72a5f98d092b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18633
22975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1863322975
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2416154623
Short name T660
Test name
Test status
Simulation time 1996665404 ps
CPU time 36.12 seconds
Started Jul 09 04:55:26 PM PDT 24
Finished Jul 09 04:56:02 PM PDT 24
Peak memory 257392 kb
Host smart-29fbc485-3354-43d0-9ae4-88a59fa0c884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24161
54623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2416154623
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2427260425
Short name T49
Test name
Test status
Simulation time 932572401 ps
CPU time 34.1 seconds
Started Jul 09 04:55:25 PM PDT 24
Finished Jul 09 04:56:00 PM PDT 24
Peak memory 257296 kb
Host smart-f8128b7a-0659-4839-89a3-773eed1094e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
60425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2427260425
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2069956619
Short name T600
Test name
Test status
Simulation time 34988530548 ps
CPU time 864.79 seconds
Started Jul 09 04:55:32 PM PDT 24
Finished Jul 09 05:09:57 PM PDT 24
Peak memory 273884 kb
Host smart-a2dbcd4c-bdc6-4a38-9092-411b95a1b635
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069956619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2069956619
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.98737114
Short name T521
Test name
Test status
Simulation time 10372992018 ps
CPU time 480.12 seconds
Started Jul 09 04:55:34 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 273224 kb
Host smart-3dd91acb-7412-4919-a042-e8c3b1018952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98737114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.98737114
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1700916873
Short name T354
Test name
Test status
Simulation time 2037254238 ps
CPU time 64.14 seconds
Started Jul 09 04:55:28 PM PDT 24
Finished Jul 09 04:56:33 PM PDT 24
Peak memory 257352 kb
Host smart-ff72a2e0-f052-4531-a037-d71d5d1ea5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17009
16873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1700916873
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2523142320
Short name T534
Test name
Test status
Simulation time 2492832996 ps
CPU time 17.22 seconds
Started Jul 09 04:55:30 PM PDT 24
Finished Jul 09 04:55:48 PM PDT 24
Peak memory 256696 kb
Host smart-1311c488-763a-4748-91f6-9dd0ac6dce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25231
42320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2523142320
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4288449167
Short name T421
Test name
Test status
Simulation time 9765088472 ps
CPU time 1102.55 seconds
Started Jul 09 04:55:28 PM PDT 24
Finished Jul 09 05:13:51 PM PDT 24
Peak memory 289656 kb
Host smart-8493883b-dfc3-4fc3-bd9f-7de2bf17eb54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288449167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4288449167
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2811291045
Short name T614
Test name
Test status
Simulation time 7904048472 ps
CPU time 242 seconds
Started Jul 09 04:55:30 PM PDT 24
Finished Jul 09 04:59:33 PM PDT 24
Peak memory 249132 kb
Host smart-3e3803bf-cf79-45e5-9f51-195a22a54e8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811291045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2811291045
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1639899043
Short name T575
Test name
Test status
Simulation time 2004703849 ps
CPU time 21.28 seconds
Started Jul 09 04:55:28 PM PDT 24
Finished Jul 09 04:55:50 PM PDT 24
Peak memory 255804 kb
Host smart-61fc218a-3e23-478f-97c7-2466359693de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16398
99043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1639899043
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4217323602
Short name T102
Test name
Test status
Simulation time 1433889127 ps
CPU time 54.27 seconds
Started Jul 09 04:55:30 PM PDT 24
Finished Jul 09 04:56:24 PM PDT 24
Peak memory 256836 kb
Host smart-3d3eba7e-b3d0-4df9-aaf4-e5fe9db657f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42173
23602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4217323602
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2577815201
Short name T483
Test name
Test status
Simulation time 575251353 ps
CPU time 32.45 seconds
Started Jul 09 04:55:29 PM PDT 24
Finished Jul 09 04:56:02 PM PDT 24
Peak memory 257428 kb
Host smart-76a5bb48-2c2a-4410-8012-f086f83ac190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25778
15201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2577815201
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.532107734
Short name T60
Test name
Test status
Simulation time 175382842346 ps
CPU time 2574.76 seconds
Started Jul 09 04:55:28 PM PDT 24
Finished Jul 09 05:38:24 PM PDT 24
Peak memory 288332 kb
Host smart-a82791db-d108-4013-bcba-744a194c94c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532107734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.532107734
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2155975405
Short name T115
Test name
Test status
Simulation time 205344082122 ps
CPU time 5054.2 seconds
Started Jul 09 04:55:29 PM PDT 24
Finished Jul 09 06:19:44 PM PDT 24
Peak memory 332176 kb
Host smart-92e16645-3327-4682-a15b-4d1827414a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155975405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2155975405
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3469529118
Short name T474
Test name
Test status
Simulation time 13025176615 ps
CPU time 1278.7 seconds
Started Jul 09 04:55:37 PM PDT 24
Finished Jul 09 05:16:57 PM PDT 24
Peak memory 290172 kb
Host smart-5da998fa-1909-4fc2-a364-dceb7e8c6c7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469529118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3469529118
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1778975409
Short name T27
Test name
Test status
Simulation time 328692833 ps
CPU time 4.92 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 04:55:41 PM PDT 24
Peak memory 240412 kb
Host smart-fe28dc9b-5e15-4acf-aa4c-2f125cb9bceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17789
75409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1778975409
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3365111717
Short name T544
Test name
Test status
Simulation time 574981223 ps
CPU time 11.28 seconds
Started Jul 09 04:55:32 PM PDT 24
Finished Jul 09 04:55:43 PM PDT 24
Peak memory 256192 kb
Host smart-132d732d-c692-4bed-b679-c723a87be022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33651
11717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3365111717
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.378031026
Short name T386
Test name
Test status
Simulation time 166626931405 ps
CPU time 2500.74 seconds
Started Jul 09 04:55:33 PM PDT 24
Finished Jul 09 05:37:14 PM PDT 24
Peak memory 283252 kb
Host smart-27c40735-36a9-4cc1-864a-cb9f3181f521
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378031026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.378031026
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2620851135
Short name T608
Test name
Test status
Simulation time 12783920371 ps
CPU time 536.2 seconds
Started Jul 09 04:55:33 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 249232 kb
Host smart-cfb108d4-102d-4a3a-b340-426ffc94e368
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620851135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2620851135
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3194585483
Short name T3
Test name
Test status
Simulation time 764708680 ps
CPU time 33.08 seconds
Started Jul 09 04:55:35 PM PDT 24
Finished Jul 09 04:56:08 PM PDT 24
Peak memory 256872 kb
Host smart-f1a31830-58ec-4487-9d5a-c18f59b65582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31945
85483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3194585483
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2827989135
Short name T503
Test name
Test status
Simulation time 499253908 ps
CPU time 33.24 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 04:56:09 PM PDT 24
Peak memory 256760 kb
Host smart-82ae8a20-3beb-40cc-aeba-f5e2e9864cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28279
89135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2827989135
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4004515232
Short name T468
Test name
Test status
Simulation time 112595317 ps
CPU time 7.52 seconds
Started Jul 09 04:55:32 PM PDT 24
Finished Jul 09 04:55:40 PM PDT 24
Peak memory 254268 kb
Host smart-0e8815db-770c-4d01-adc1-38d269f39f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40045
15232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4004515232
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2339882348
Short name T128
Test name
Test status
Simulation time 552893622 ps
CPU time 26.78 seconds
Started Jul 09 04:55:33 PM PDT 24
Finished Jul 09 04:56:01 PM PDT 24
Peak memory 249140 kb
Host smart-2b4f0a46-aa12-423b-8d99-3e050f3c206b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
82348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2339882348
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1089690315
Short name T592
Test name
Test status
Simulation time 1099087205 ps
CPU time 62 seconds
Started Jul 09 04:55:34 PM PDT 24
Finished Jul 09 04:56:37 PM PDT 24
Peak memory 257468 kb
Host smart-8bb60559-896c-4627-b99c-1bd2d73940c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089690315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1089690315
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3832887356
Short name T56
Test name
Test status
Simulation time 147123526679 ps
CPU time 1303.2 seconds
Started Jul 09 04:55:34 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 287524 kb
Host smart-b1c7ef60-a458-4995-87d3-a6d046ab2fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832887356 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3832887356
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1757520316
Short name T368
Test name
Test status
Simulation time 51304511115 ps
CPU time 1375.52 seconds
Started Jul 09 04:55:32 PM PDT 24
Finished Jul 09 05:18:29 PM PDT 24
Peak memory 289528 kb
Host smart-4e9db4fb-c42d-4c3b-b26e-fb3a85f04fdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757520316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1757520316
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.996733820
Short name T29
Test name
Test status
Simulation time 14573202130 ps
CPU time 186.41 seconds
Started Jul 09 04:55:35 PM PDT 24
Finished Jul 09 04:58:42 PM PDT 24
Peak memory 257488 kb
Host smart-bdec3e5c-c667-428c-8446-237912b510e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99673
3820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.996733820
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3783171447
Short name T31
Test name
Test status
Simulation time 266122294 ps
CPU time 18.31 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 04:55:55 PM PDT 24
Peak memory 249152 kb
Host smart-d1822fe6-8cff-4a2e-aa27-3bd813f7dddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
71447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3783171447
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1646200515
Short name T574
Test name
Test status
Simulation time 8334494806 ps
CPU time 773.35 seconds
Started Jul 09 04:55:39 PM PDT 24
Finished Jul 09 05:08:32 PM PDT 24
Peak memory 273052 kb
Host smart-baf6809d-07f8-43d9-98fa-de7885f60383
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646200515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1646200515
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3961724822
Short name T448
Test name
Test status
Simulation time 59572877161 ps
CPU time 3511.63 seconds
Started Jul 09 04:55:35 PM PDT 24
Finished Jul 09 05:54:07 PM PDT 24
Peak memory 289960 kb
Host smart-088cf712-d36e-4c72-873b-70da3b720e3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961724822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3961724822
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.804382625
Short name T477
Test name
Test status
Simulation time 354661342 ps
CPU time 34.74 seconds
Started Jul 09 04:55:35 PM PDT 24
Finished Jul 09 04:56:11 PM PDT 24
Peak memory 249084 kb
Host smart-23fd9ca8-e42a-445b-911d-d06332f72f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80438
2625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.804382625
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.765449490
Short name T455
Test name
Test status
Simulation time 43596678 ps
CPU time 4.21 seconds
Started Jul 09 04:55:32 PM PDT 24
Finished Jul 09 04:55:37 PM PDT 24
Peak memory 240464 kb
Host smart-72001067-2e6a-4e5a-a335-23674c1e68be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76544
9490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.765449490
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1464197091
Short name T51
Test name
Test status
Simulation time 776729945 ps
CPU time 19.96 seconds
Started Jul 09 04:55:33 PM PDT 24
Finished Jul 09 04:55:54 PM PDT 24
Peak memory 248644 kb
Host smart-7e65f853-bccb-457c-8ca8-888ea14b9a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14641
97091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1464197091
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2096018070
Short name T684
Test name
Test status
Simulation time 54826153 ps
CPU time 4.07 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 04:55:41 PM PDT 24
Peak memory 251428 kb
Host smart-f05d42e4-91b1-49da-830c-1646ce3950d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20960
18070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2096018070
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1161843695
Short name T61
Test name
Test status
Simulation time 34070336593 ps
CPU time 1271.33 seconds
Started Jul 09 04:55:37 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 289964 kb
Host smart-27372e16-46c0-4ade-9053-2539efe53800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161843695 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1161843695
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2837446213
Short name T668
Test name
Test status
Simulation time 82283564199 ps
CPU time 1387.91 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 273408 kb
Host smart-ab734975-5b3b-4614-a462-ae2d0b21ae00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837446213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2837446213
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2722705970
Short name T671
Test name
Test status
Simulation time 1533418642 ps
CPU time 57.38 seconds
Started Jul 09 04:55:40 PM PDT 24
Finished Jul 09 04:56:38 PM PDT 24
Peak memory 257372 kb
Host smart-a78f59fa-c9f7-4f89-a31e-530353d16b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
05970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2722705970
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1525826188
Short name T590
Test name
Test status
Simulation time 1150416609 ps
CPU time 25.6 seconds
Started Jul 09 04:55:38 PM PDT 24
Finished Jul 09 04:56:04 PM PDT 24
Peak memory 256904 kb
Host smart-abc66b26-d3d9-4968-bf77-6a9424d5f12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15258
26188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1525826188
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4265942288
Short name T326
Test name
Test status
Simulation time 95419055039 ps
CPU time 1564.75 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 05:21:42 PM PDT 24
Peak memory 273292 kb
Host smart-c95d27a7-fab5-41ab-963c-127fa7b8bdea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265942288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4265942288
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3418551257
Short name T476
Test name
Test status
Simulation time 35746660230 ps
CPU time 1972.78 seconds
Started Jul 09 04:55:41 PM PDT 24
Finished Jul 09 05:28:34 PM PDT 24
Peak memory 285640 kb
Host smart-5a88c2e6-6b71-4868-a607-bfbffdef4e33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418551257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3418551257
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1554072270
Short name T5
Test name
Test status
Simulation time 10763886078 ps
CPU time 80.58 seconds
Started Jul 09 04:55:38 PM PDT 24
Finished Jul 09 04:56:59 PM PDT 24
Peak memory 255352 kb
Host smart-a3f6d6c3-4072-47a1-af59-79eb909b3c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554072270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1554072270
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2497017674
Short name T686
Test name
Test status
Simulation time 54343986 ps
CPU time 7.3 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 04:55:44 PM PDT 24
Peak memory 249424 kb
Host smart-b5434395-74a9-40a0-becf-cfad8893ebb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24970
17674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2497017674
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2177181717
Short name T500
Test name
Test status
Simulation time 2402177740 ps
CPU time 46.81 seconds
Started Jul 09 04:55:37 PM PDT 24
Finished Jul 09 04:56:24 PM PDT 24
Peak memory 249372 kb
Host smart-a34ab980-9ee5-4c73-b718-60e7cad48c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771
81717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2177181717
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3962248647
Short name T561
Test name
Test status
Simulation time 690987394 ps
CPU time 19.47 seconds
Started Jul 09 04:55:37 PM PDT 24
Finished Jul 09 04:55:57 PM PDT 24
Peak memory 248412 kb
Host smart-6b50078a-02e3-4bc1-ae3e-fceec7c0bf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39622
48647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3962248647
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.342284202
Short name T461
Test name
Test status
Simulation time 142579579 ps
CPU time 13.17 seconds
Started Jul 09 04:55:36 PM PDT 24
Finished Jul 09 04:55:50 PM PDT 24
Peak memory 249148 kb
Host smart-565e4c0a-323f-4477-9c66-1f797b23bebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
4202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.342284202
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3644937131
Short name T562
Test name
Test status
Simulation time 576050652847 ps
CPU time 2892.31 seconds
Started Jul 09 04:55:41 PM PDT 24
Finished Jul 09 05:43:54 PM PDT 24
Peak memory 290212 kb
Host smart-1616e5b3-6d2d-46c8-ac4f-1e3f58b9b77c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644937131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3644937131
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1808877205
Short name T485
Test name
Test status
Simulation time 24964008896 ps
CPU time 1371.6 seconds
Started Jul 09 04:55:40 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 290380 kb
Host smart-d1af2302-0f0f-4566-b8a7-d721e78d1bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808877205 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1808877205
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3686839455
Short name T113
Test name
Test status
Simulation time 17773114174 ps
CPU time 1609.46 seconds
Started Jul 09 04:55:42 PM PDT 24
Finished Jul 09 05:22:32 PM PDT 24
Peak memory 290056 kb
Host smart-d8829876-e2ba-4c9e-acee-aef54d84e4b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686839455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3686839455
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3403808719
Short name T538
Test name
Test status
Simulation time 9566448713 ps
CPU time 61.1 seconds
Started Jul 09 04:55:42 PM PDT 24
Finished Jul 09 04:56:44 PM PDT 24
Peak memory 257476 kb
Host smart-6ed38f17-df69-479c-98d0-3af700dba275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
08719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3403808719
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.506290260
Short name T524
Test name
Test status
Simulation time 959141042 ps
CPU time 18.18 seconds
Started Jul 09 04:55:43 PM PDT 24
Finished Jul 09 04:56:02 PM PDT 24
Peak memory 248732 kb
Host smart-141e31f5-76eb-4815-bbff-166a926a3e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50629
0260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.506290260
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.789306883
Short name T316
Test name
Test status
Simulation time 35295947101 ps
CPU time 1529.12 seconds
Started Jul 09 04:55:46 PM PDT 24
Finished Jul 09 05:21:16 PM PDT 24
Peak memory 290124 kb
Host smart-44540b48-b171-4c2c-92b0-4db1e8d56768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789306883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.789306883
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1288814177
Short name T639
Test name
Test status
Simulation time 50587093743 ps
CPU time 1172.63 seconds
Started Jul 09 04:55:47 PM PDT 24
Finished Jul 09 05:15:21 PM PDT 24
Peak memory 273964 kb
Host smart-d063392a-38ff-420c-845d-07c7d61ce877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288814177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1288814177
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2748436196
Short name T526
Test name
Test status
Simulation time 33905772326 ps
CPU time 113.86 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 04:57:45 PM PDT 24
Peak memory 256096 kb
Host smart-6b11a167-871b-4c41-b153-065c73a45755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748436196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2748436196
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2761800020
Short name T622
Test name
Test status
Simulation time 1400935923 ps
CPU time 24.31 seconds
Started Jul 09 04:55:43 PM PDT 24
Finished Jul 09 04:56:07 PM PDT 24
Peak memory 255816 kb
Host smart-3dd38643-6e7c-4860-8fcc-7ad9b8a536c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
00020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2761800020
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.329641172
Short name T696
Test name
Test status
Simulation time 7924189783 ps
CPU time 39.28 seconds
Started Jul 09 04:55:40 PM PDT 24
Finished Jul 09 04:56:19 PM PDT 24
Peak memory 256396 kb
Host smart-cb03bfb4-2521-4ba2-9ffa-89b40af4843f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32964
1172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.329641172
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3161046315
Short name T603
Test name
Test status
Simulation time 871371599 ps
CPU time 25.56 seconds
Started Jul 09 04:55:40 PM PDT 24
Finished Jul 09 04:56:07 PM PDT 24
Peak memory 256320 kb
Host smart-15eff54e-0c50-4860-85a1-b3b14b808c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
46315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3161046315
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4213922397
Short name T424
Test name
Test status
Simulation time 1166138921 ps
CPU time 66.95 seconds
Started Jul 09 04:55:41 PM PDT 24
Finished Jul 09 04:56:49 PM PDT 24
Peak memory 257332 kb
Host smart-cec8b6fb-6de4-4a0d-aba3-d88368014373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42139
22397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4213922397
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2562297681
Short name T293
Test name
Test status
Simulation time 446230739825 ps
CPU time 2524.69 seconds
Started Jul 09 04:55:49 PM PDT 24
Finished Jul 09 05:37:54 PM PDT 24
Peak memory 289660 kb
Host smart-c200e1b7-d7f1-4e5a-abc3-93729ea10d50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562297681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2562297681
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2702631814
Short name T245
Test name
Test status
Simulation time 46148354761 ps
CPU time 1480.95 seconds
Started Jul 09 04:55:46 PM PDT 24
Finished Jul 09 05:20:27 PM PDT 24
Peak memory 288968 kb
Host smart-bab97694-483e-4bb5-8a99-54b0c436e8e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702631814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2702631814
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1189653951
Short name T227
Test name
Test status
Simulation time 20730802 ps
CPU time 2.79 seconds
Started Jul 09 04:54:18 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 249460 kb
Host smart-294c1a2f-f738-41d0-a43c-578305876858
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1189653951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1189653951
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3091099931
Short name T120
Test name
Test status
Simulation time 183869561401 ps
CPU time 2857.07 seconds
Started Jul 09 04:54:14 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 287176 kb
Host smart-614f8aa8-55a9-421f-a977-82f981266631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091099931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3091099931
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1016924115
Short name T369
Test name
Test status
Simulation time 1168614669 ps
CPU time 15.83 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 04:54:35 PM PDT 24
Peak memory 249064 kb
Host smart-d12b9162-74fb-4d44-93b6-bb61b656965f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1016924115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1016924115
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2935992491
Short name T581
Test name
Test status
Simulation time 4903679364 ps
CPU time 153.65 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:56:57 PM PDT 24
Peak memory 256872 kb
Host smart-accae86a-1b96-49e0-8874-35323bc4edd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29359
92491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2935992491
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2579622817
Short name T121
Test name
Test status
Simulation time 3876175591 ps
CPU time 45.05 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:59 PM PDT 24
Peak memory 256780 kb
Host smart-696770d2-bbe7-4032-a780-96c178583a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
22817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2579622817
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.476920931
Short name T658
Test name
Test status
Simulation time 24335271449 ps
CPU time 1320.6 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 05:16:18 PM PDT 24
Peak memory 286548 kb
Host smart-174875f7-cb98-40b6-8b20-15b147021036
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476920931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.476920931
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2025230822
Short name T38
Test name
Test status
Simulation time 27145585913 ps
CPU time 723 seconds
Started Jul 09 04:54:18 PM PDT 24
Finished Jul 09 05:06:22 PM PDT 24
Peak memory 273400 kb
Host smart-9e38692c-5479-4344-b446-8ed99bec8070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025230822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2025230822
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3374288924
Short name T598
Test name
Test status
Simulation time 10557953872 ps
CPU time 419.96 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 05:01:23 PM PDT 24
Peak memory 249068 kb
Host smart-3a73080c-f970-4d69-8034-f50dd1ee4de2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374288924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3374288924
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2712443324
Short name T248
Test name
Test status
Simulation time 421364706 ps
CPU time 26.83 seconds
Started Jul 09 04:54:15 PM PDT 24
Finished Jul 09 04:54:42 PM PDT 24
Peak memory 256936 kb
Host smart-ca947b41-4983-48d2-9faa-54534746267a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27124
43324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2712443324
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1534399234
Short name T264
Test name
Test status
Simulation time 923810817 ps
CPU time 26.16 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:45 PM PDT 24
Peak memory 248684 kb
Host smart-486303cd-b79a-4f56-bb3a-cae3ef49f68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15343
99234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1534399234
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1834679799
Short name T642
Test name
Test status
Simulation time 174057308 ps
CPU time 11.13 seconds
Started Jul 09 04:54:13 PM PDT 24
Finished Jul 09 04:54:25 PM PDT 24
Peak memory 248708 kb
Host smart-3404eab9-dc8a-49cd-a1aa-62f08134998b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18346
79799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1834679799
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2727749168
Short name T425
Test name
Test status
Simulation time 531485169 ps
CPU time 32.17 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:50 PM PDT 24
Peak memory 257172 kb
Host smart-52cf87e6-69a3-4a1a-9ec2-d09e78bd5da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27277
49168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2727749168
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2067969363
Short name T411
Test name
Test status
Simulation time 30108968903 ps
CPU time 489.53 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 05:02:29 PM PDT 24
Peak memory 257488 kb
Host smart-6f999a6d-9ca6-449f-a0f0-77cd731ae202
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067969363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2067969363
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2406620236
Short name T488
Test name
Test status
Simulation time 46347146925 ps
CPU time 4655.49 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 06:11:54 PM PDT 24
Peak memory 334196 kb
Host smart-e1b706e7-52e0-4c4a-a588-f37f996e97cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406620236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2406620236
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.882437692
Short name T578
Test name
Test status
Simulation time 85936816169 ps
CPU time 1346.07 seconds
Started Jul 09 04:55:45 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 265684 kb
Host smart-b5dddead-e65d-4e3e-a3d0-8af8b1c3d29e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882437692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.882437692
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.606302156
Short name T350
Test name
Test status
Simulation time 775291407 ps
CPU time 74.38 seconds
Started Jul 09 04:55:47 PM PDT 24
Finished Jul 09 04:57:02 PM PDT 24
Peak memory 256736 kb
Host smart-f0f60d80-3db2-4c93-a444-8b681fd320d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60630
2156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.606302156
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1115292089
Short name T626
Test name
Test status
Simulation time 323936004 ps
CPU time 8.62 seconds
Started Jul 09 04:55:47 PM PDT 24
Finished Jul 09 04:55:56 PM PDT 24
Peak memory 249096 kb
Host smart-5b701223-24fe-496d-ad5a-782eafd6bc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11152
92089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1115292089
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1007697184
Short name T19
Test name
Test status
Simulation time 33485109268 ps
CPU time 1578.55 seconds
Started Jul 09 04:55:45 PM PDT 24
Finished Jul 09 05:22:05 PM PDT 24
Peak memory 289596 kb
Host smart-c4f95a82-4832-4508-8995-bf75b66840d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007697184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1007697184
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1506099812
Short name T402
Test name
Test status
Simulation time 62072137619 ps
CPU time 1537.4 seconds
Started Jul 09 04:55:46 PM PDT 24
Finished Jul 09 05:21:24 PM PDT 24
Peak memory 285960 kb
Host smart-29861045-28ec-4ddf-9577-263f8b13a91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506099812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1506099812
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2995601567
Short name T306
Test name
Test status
Simulation time 9942385739 ps
CPU time 405.47 seconds
Started Jul 09 04:55:45 PM PDT 24
Finished Jul 09 05:02:31 PM PDT 24
Peak memory 256656 kb
Host smart-f035d9ed-69b3-4fc5-bfde-2e647721b95a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995601567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2995601567
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3084683850
Short name T375
Test name
Test status
Simulation time 31260961 ps
CPU time 4.23 seconds
Started Jul 09 04:55:47 PM PDT 24
Finished Jul 09 04:55:51 PM PDT 24
Peak memory 249104 kb
Host smart-468b8ebc-6feb-4eb0-805b-2508670c3857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30846
83850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3084683850
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.102630691
Short name T527
Test name
Test status
Simulation time 261779725 ps
CPU time 9.99 seconds
Started Jul 09 04:55:46 PM PDT 24
Finished Jul 09 04:55:56 PM PDT 24
Peak memory 248716 kb
Host smart-b42d1166-9db2-46ab-85b2-9dcbe909fc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10263
0691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.102630691
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3401088205
Short name T414
Test name
Test status
Simulation time 114372192 ps
CPU time 15.06 seconds
Started Jul 09 04:55:45 PM PDT 24
Finished Jul 09 04:56:00 PM PDT 24
Peak memory 256528 kb
Host smart-38c7d146-c0b9-4859-8f6a-9daf9821d070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
88205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3401088205
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2333227160
Short name T678
Test name
Test status
Simulation time 1254250258 ps
CPU time 43.71 seconds
Started Jul 09 04:55:46 PM PDT 24
Finished Jul 09 04:56:31 PM PDT 24
Peak memory 257284 kb
Host smart-3d76b657-ebd4-406e-b084-19abd53d9ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
27160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2333227160
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2196765155
Short name T653
Test name
Test status
Simulation time 18673711673 ps
CPU time 678.31 seconds
Started Jul 09 04:55:50 PM PDT 24
Finished Jul 09 05:07:08 PM PDT 24
Peak memory 273700 kb
Host smart-b0cce3c5-35fd-4e41-b727-59825d6a0442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196765155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2196765155
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1924250341
Short name T463
Test name
Test status
Simulation time 12228659321 ps
CPU time 326.9 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 05:01:19 PM PDT 24
Peak memory 257000 kb
Host smart-cce141a0-f7bf-44a3-8e7d-62c2a0286285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19242
50341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1924250341
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.737876364
Short name T464
Test name
Test status
Simulation time 1535042446 ps
CPU time 26.55 seconds
Started Jul 09 04:55:50 PM PDT 24
Finished Jul 09 04:56:17 PM PDT 24
Peak memory 248704 kb
Host smart-1d45f2da-b1d6-410d-a5b6-9ef5038993bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73787
6364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.737876364
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1226757702
Short name T296
Test name
Test status
Simulation time 31233403550 ps
CPU time 730.46 seconds
Started Jul 09 04:55:49 PM PDT 24
Finished Jul 09 05:08:00 PM PDT 24
Peak memory 273716 kb
Host smart-4c7704be-922a-428a-bc9f-aa76d862b8f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226757702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1226757702
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1623287855
Short name T437
Test name
Test status
Simulation time 270616541353 ps
CPU time 2241.75 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 05:33:14 PM PDT 24
Peak memory 289612 kb
Host smart-2a9b0693-14fc-46ab-99b7-5867edc58f18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623287855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1623287855
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2052038176
Short name T295
Test name
Test status
Simulation time 13087032278 ps
CPU time 492.51 seconds
Started Jul 09 04:55:48 PM PDT 24
Finished Jul 09 05:04:01 PM PDT 24
Peak memory 249032 kb
Host smart-065fa079-132b-4d1b-929b-3affd8994d2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052038176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2052038176
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2810423386
Short name T126
Test name
Test status
Simulation time 35963367 ps
CPU time 3.11 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 04:55:55 PM PDT 24
Peak memory 240892 kb
Host smart-77eddfe5-256d-413b-926c-4ea45238977f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28104
23386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2810423386
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3254458323
Short name T599
Test name
Test status
Simulation time 1095671491 ps
CPU time 59.1 seconds
Started Jul 09 04:55:56 PM PDT 24
Finished Jul 09 04:56:56 PM PDT 24
Peak memory 249184 kb
Host smart-f5b78d2b-c95f-4655-93aa-322765001928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32544
58323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3254458323
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2173774445
Short name T259
Test name
Test status
Simulation time 738897337 ps
CPU time 17.43 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 04:56:09 PM PDT 24
Peak memory 249664 kb
Host smart-985cdddc-c531-43b7-8703-a37248e74e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21737
74445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2173774445
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2436052542
Short name T690
Test name
Test status
Simulation time 19444006787 ps
CPU time 1910.61 seconds
Started Jul 09 04:55:48 PM PDT 24
Finished Jul 09 05:27:40 PM PDT 24
Peak memory 301700 kb
Host smart-863a4d55-2d8e-49cc-a796-fb8edbb2294e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436052542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2436052542
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.750917278
Short name T371
Test name
Test status
Simulation time 26426394161 ps
CPU time 1395.09 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 05:19:18 PM PDT 24
Peak memory 289896 kb
Host smart-6fdc160c-3cde-407b-9d58-e92ebd1fcf1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750917278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.750917278
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1722151928
Short name T656
Test name
Test status
Simulation time 1355474635 ps
CPU time 39.86 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 04:56:47 PM PDT 24
Peak memory 256856 kb
Host smart-4f7c011a-0479-42fb-a9a3-ca9f0cafbe5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17221
51928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1722151928
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4246189969
Short name T75
Test name
Test status
Simulation time 5152928579 ps
CPU time 76.44 seconds
Started Jul 09 04:55:53 PM PDT 24
Finished Jul 09 04:57:10 PM PDT 24
Peak memory 249224 kb
Host smart-49231dd5-b025-4e26-85bb-96ba8ea17768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
89969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4246189969
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3286226764
Short name T520
Test name
Test status
Simulation time 40165624004 ps
CPU time 839.38 seconds
Started Jul 09 04:55:53 PM PDT 24
Finished Jul 09 05:09:53 PM PDT 24
Peak memory 265820 kb
Host smart-5ec2350f-c724-4020-96c1-42071ba0cfe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286226764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3286226764
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1802747963
Short name T97
Test name
Test status
Simulation time 22640889190 ps
CPU time 1055.91 seconds
Started Jul 09 04:55:54 PM PDT 24
Finished Jul 09 05:13:30 PM PDT 24
Peak memory 283832 kb
Host smart-520be0df-1ab1-4a8d-8bde-cbb933178b28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802747963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1802747963
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4179333072
Short name T502
Test name
Test status
Simulation time 3668145326 ps
CPU time 148.44 seconds
Started Jul 09 04:55:55 PM PDT 24
Finished Jul 09 04:58:24 PM PDT 24
Peak memory 249156 kb
Host smart-7ef23d5a-b562-4a15-8c21-fb9d7b3c9fb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179333072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4179333072
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.395842701
Short name T484
Test name
Test status
Simulation time 6391767121 ps
CPU time 39.34 seconds
Started Jul 09 04:55:52 PM PDT 24
Finished Jul 09 04:56:32 PM PDT 24
Peak memory 249304 kb
Host smart-75a2b42a-06f4-47da-bed6-ca7caf089d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39584
2701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.395842701
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.856812770
Short name T266
Test name
Test status
Simulation time 3837281199 ps
CPU time 61.07 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 04:56:52 PM PDT 24
Peak memory 249280 kb
Host smart-ba337e25-2617-4aca-8cab-3bc23e9e5b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85681
2770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.856812770
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1020770557
Short name T501
Test name
Test status
Simulation time 8111344634 ps
CPU time 28.7 seconds
Started Jul 09 04:55:56 PM PDT 24
Finished Jul 09 04:56:25 PM PDT 24
Peak memory 256580 kb
Host smart-b69744c3-cc58-4088-b2d1-b966602c7395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
70557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1020770557
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3235660559
Short name T6
Test name
Test status
Simulation time 390494195 ps
CPU time 32.76 seconds
Started Jul 09 04:55:51 PM PDT 24
Finished Jul 09 04:56:24 PM PDT 24
Peak memory 257288 kb
Host smart-e40aeddb-0876-4c1b-b4f8-e4dd03b3dfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
60559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3235660559
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4196644866
Short name T276
Test name
Test status
Simulation time 12097258024 ps
CPU time 807.47 seconds
Started Jul 09 04:55:55 PM PDT 24
Finished Jul 09 05:09:24 PM PDT 24
Peak memory 265684 kb
Host smart-8a3163e4-ad8b-476c-8d86-3da19ccfc640
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196644866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4196644866
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2593570235
Short name T379
Test name
Test status
Simulation time 71288048235 ps
CPU time 1109.99 seconds
Started Jul 09 04:56:01 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 273300 kb
Host smart-aa922ff4-25c1-4d1e-a4f7-a93d5319343c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593570235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2593570235
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3352691220
Short name T662
Test name
Test status
Simulation time 2082636724 ps
CPU time 100.03 seconds
Started Jul 09 04:56:01 PM PDT 24
Finished Jul 09 04:57:42 PM PDT 24
Peak memory 256844 kb
Host smart-d173e586-73be-4bcd-a9eb-1e0726c025c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33526
91220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3352691220
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3280702664
Short name T606
Test name
Test status
Simulation time 2383664929 ps
CPU time 23.69 seconds
Started Jul 09 04:56:01 PM PDT 24
Finished Jul 09 04:56:25 PM PDT 24
Peak memory 249232 kb
Host smart-c8cc53df-a8f0-4550-b1ef-f08316e76f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32807
02664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3280702664
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1771525475
Short name T256
Test name
Test status
Simulation time 27548496545 ps
CPU time 1808.39 seconds
Started Jul 09 04:56:00 PM PDT 24
Finished Jul 09 05:26:10 PM PDT 24
Peak memory 272960 kb
Host smart-8cf42157-34ea-417c-a316-6ee9db0201f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771525475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1771525475
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3183390369
Short name T494
Test name
Test status
Simulation time 40735449233 ps
CPU time 1424.93 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 05:19:56 PM PDT 24
Peak memory 273016 kb
Host smart-b7a008cf-79d3-42db-b45a-d016b34e0a78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183390369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3183390369
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3356153300
Short name T682
Test name
Test status
Simulation time 44079428631 ps
CPU time 533.84 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 05:05:28 PM PDT 24
Peak memory 249172 kb
Host smart-add57f0c-cd63-4b2c-8225-d10c94ba0432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356153300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3356153300
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2537233118
Short name T359
Test name
Test status
Simulation time 2406309003 ps
CPU time 31.18 seconds
Started Jul 09 04:55:55 PM PDT 24
Finished Jul 09 04:56:27 PM PDT 24
Peak memory 256544 kb
Host smart-bc1088c9-7080-4703-98d1-22d39e923557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
33118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2537233118
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.420693674
Short name T689
Test name
Test status
Simulation time 953555243 ps
CPU time 29.97 seconds
Started Jul 09 04:55:54 PM PDT 24
Finished Jul 09 04:56:25 PM PDT 24
Peak memory 256688 kb
Host smart-8874baa2-b0ca-45a2-bf84-7338246a2e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42069
3674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.420693674
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1623604852
Short name T576
Test name
Test status
Simulation time 2141738414 ps
CPU time 41.89 seconds
Started Jul 09 04:55:58 PM PDT 24
Finished Jul 09 04:56:40 PM PDT 24
Peak memory 249196 kb
Host smart-fdbb017c-4a05-4eca-b570-ebb70fcfbf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16236
04852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1623604852
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2690985299
Short name T383
Test name
Test status
Simulation time 341838602 ps
CPU time 22.5 seconds
Started Jul 09 04:55:55 PM PDT 24
Finished Jul 09 04:56:19 PM PDT 24
Peak memory 256028 kb
Host smart-1a6b4514-cd83-4b16-a564-090e8ee9ff4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26909
85299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2690985299
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2103357440
Short name T513
Test name
Test status
Simulation time 111070393584 ps
CPU time 1969.3 seconds
Started Jul 09 04:55:58 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 289672 kb
Host smart-a67151bf-5a32-41ba-9f25-6143bdd70d30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103357440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2103357440
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3566497526
Short name T409
Test name
Test status
Simulation time 11563729375 ps
CPU time 1304.8 seconds
Started Jul 09 04:56:07 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 289360 kb
Host smart-0d226677-1632-44c9-8d2b-f8d2d8b41246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566497526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3566497526
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1137831478
Short name T482
Test name
Test status
Simulation time 28958877659 ps
CPU time 146.04 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 04:58:28 PM PDT 24
Peak memory 251400 kb
Host smart-1b0f40d8-7251-4fa2-8c77-678e203bc90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
31478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1137831478
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2574637067
Short name T458
Test name
Test status
Simulation time 1490467362 ps
CPU time 25.24 seconds
Started Jul 09 04:55:57 PM PDT 24
Finished Jul 09 04:56:23 PM PDT 24
Peak memory 248508 kb
Host smart-75783069-4792-4c34-a8cd-b1cfcbae6d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25746
37067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2574637067
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2567833286
Short name T236
Test name
Test status
Simulation time 81263966130 ps
CPU time 1600.02 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 05:22:42 PM PDT 24
Peak memory 290056 kb
Host smart-93a79dd7-3545-4f11-b06e-e767e07f3e22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567833286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2567833286
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1931665158
Short name T569
Test name
Test status
Simulation time 120172411289 ps
CPU time 1622.72 seconds
Started Jul 09 04:56:07 PM PDT 24
Finished Jul 09 05:23:11 PM PDT 24
Peak memory 283512 kb
Host smart-1f704fcd-72b9-4e9e-a546-ee6cbec677fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931665158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1931665158
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4252455979
Short name T470
Test name
Test status
Simulation time 32710643070 ps
CPU time 307.96 seconds
Started Jul 09 04:56:04 PM PDT 24
Finished Jul 09 05:01:12 PM PDT 24
Peak memory 248616 kb
Host smart-56fe4f1d-aaf1-402b-ad84-1e1b26e2c1c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252455979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4252455979
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3110679672
Short name T563
Test name
Test status
Simulation time 320718946 ps
CPU time 30.29 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 04:56:33 PM PDT 24
Peak memory 256684 kb
Host smart-61670f65-f789-4252-9bbb-36dca2c19ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31106
79672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3110679672
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1127421283
Short name T84
Test name
Test status
Simulation time 11537665859 ps
CPU time 38.53 seconds
Started Jul 09 04:55:59 PM PDT 24
Finished Jul 09 04:56:37 PM PDT 24
Peak memory 249284 kb
Host smart-96b3e17b-4e64-4b4b-a47a-0bdf17d81f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274
21283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1127421283
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2998846284
Short name T124
Test name
Test status
Simulation time 315553210 ps
CPU time 29.6 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 04:56:41 PM PDT 24
Peak memory 248900 kb
Host smart-bc35bd78-6b9c-46ea-b783-eccc1d13077e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
46284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2998846284
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3689439512
Short name T471
Test name
Test status
Simulation time 134136434 ps
CPU time 16.72 seconds
Started Jul 09 04:56:00 PM PDT 24
Finished Jul 09 04:56:17 PM PDT 24
Peak memory 256140 kb
Host smart-54f15f75-14bb-4cb7-a690-fbd4088cd992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
39512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3689439512
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4147555734
Short name T65
Test name
Test status
Simulation time 22212905302 ps
CPU time 1281.25 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 273444 kb
Host smart-2436ffd0-15d4-4e3e-9924-986202b03d90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147555734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4147555734
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3845898770
Short name T672
Test name
Test status
Simulation time 13227374992 ps
CPU time 193.86 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 04:59:16 PM PDT 24
Peak memory 256672 kb
Host smart-bf32254a-2a70-4548-ac54-dabee4e4c574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458
98770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3845898770
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1821902240
Short name T475
Test name
Test status
Simulation time 1891426865 ps
CPU time 35.21 seconds
Started Jul 09 04:56:07 PM PDT 24
Finished Jul 09 04:56:43 PM PDT 24
Peak memory 256880 kb
Host smart-a0b1af1a-3388-413d-8361-cc0e417e4640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18219
02240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1821902240
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.746171942
Short name T565
Test name
Test status
Simulation time 12015831081 ps
CPU time 1105.51 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 05:14:28 PM PDT 24
Peak memory 289948 kb
Host smart-18059a5a-49d3-456a-9ebb-ab00ac861b30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746171942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.746171942
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1483881891
Short name T528
Test name
Test status
Simulation time 40365210329 ps
CPU time 867.54 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 05:10:39 PM PDT 24
Peak memory 267552 kb
Host smart-81175477-3549-4bf9-b56f-91ad0999bcfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483881891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1483881891
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2985625687
Short name T353
Test name
Test status
Simulation time 442246604 ps
CPU time 8.78 seconds
Started Jul 09 04:56:01 PM PDT 24
Finished Jul 09 04:56:10 PM PDT 24
Peak memory 251804 kb
Host smart-5a25f92c-c851-4c69-8ee1-f11237743e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29856
25687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2985625687
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1474365413
Short name T238
Test name
Test status
Simulation time 591740908 ps
CPU time 52.03 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 04:57:03 PM PDT 24
Peak memory 248848 kb
Host smart-aed6cdf3-7a13-428b-a801-5a28dcf82a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14743
65413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1474365413
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4205590210
Short name T688
Test name
Test status
Simulation time 394927459 ps
CPU time 24.97 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 04:56:28 PM PDT 24
Peak memory 256680 kb
Host smart-6b515abf-ee69-45c7-af4f-5842f52c2e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
90210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4205590210
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4023244198
Short name T376
Test name
Test status
Simulation time 212484758 ps
CPU time 6.77 seconds
Started Jul 09 04:56:02 PM PDT 24
Finished Jul 09 04:56:10 PM PDT 24
Peak memory 249276 kb
Host smart-909b04a8-84f1-4096-9db6-bb3f96735f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232
44198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4023244198
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1056862386
Short name T122
Test name
Test status
Simulation time 36468730615 ps
CPU time 2507.74 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 05:37:56 PM PDT 24
Peak memory 290312 kb
Host smart-2eac5e33-0ef2-4ec4-a191-8a4445ec4f89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056862386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1056862386
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2375071054
Short name T252
Test name
Test status
Simulation time 29186892396 ps
CPU time 1714.68 seconds
Started Jul 09 04:56:05 PM PDT 24
Finished Jul 09 05:24:40 PM PDT 24
Peak memory 283868 kb
Host smart-21bb99a6-28d7-44ba-9b8a-da30eb8f7254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375071054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2375071054
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.4224043670
Short name T505
Test name
Test status
Simulation time 2830532464 ps
CPU time 127.32 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 04:58:15 PM PDT 24
Peak memory 256756 kb
Host smart-2539ed86-0455-4799-987a-50e881f1fdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42240
43670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.4224043670
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4141694811
Short name T391
Test name
Test status
Simulation time 1092209929 ps
CPU time 11.69 seconds
Started Jul 09 04:56:07 PM PDT 24
Finished Jul 09 04:56:20 PM PDT 24
Peak memory 255832 kb
Host smart-bce8f793-bc8c-4df3-bd7a-8771500329a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
94811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4141694811
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2628954541
Short name T697
Test name
Test status
Simulation time 14381935301 ps
CPU time 1123.67 seconds
Started Jul 09 04:56:11 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 283608 kb
Host smart-569e806b-e004-4991-a5dd-5280bee1328d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628954541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2628954541
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1997189274
Short name T413
Test name
Test status
Simulation time 29129845955 ps
CPU time 1736.51 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 05:25:12 PM PDT 24
Peak memory 286892 kb
Host smart-bfa4f372-f9be-43ec-9a7a-c1ce26856e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997189274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1997189274
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1621514651
Short name T540
Test name
Test status
Simulation time 2945240195 ps
CPU time 126.25 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 04:58:13 PM PDT 24
Peak memory 249268 kb
Host smart-756c5a0c-5413-440c-9357-f41df3226abb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621514651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1621514651
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3363609632
Short name T617
Test name
Test status
Simulation time 522574464 ps
CPU time 34.84 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 04:56:42 PM PDT 24
Peak memory 256916 kb
Host smart-629cbf30-f3cf-4651-b67c-39344aab543b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636
09632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3363609632
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2055695394
Short name T612
Test name
Test status
Simulation time 1729005019 ps
CPU time 47.03 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 04:56:54 PM PDT 24
Peak memory 249128 kb
Host smart-5f8994e5-10a5-48f5-9ca0-58327f010dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
95394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2055695394
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3299152765
Short name T197
Test name
Test status
Simulation time 3241678202 ps
CPU time 47.37 seconds
Started Jul 09 04:56:07 PM PDT 24
Finished Jul 09 04:56:55 PM PDT 24
Peak memory 249316 kb
Host smart-c563b4c1-5431-4cce-ae0f-b36a52eb3e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32991
52765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3299152765
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2059268238
Short name T352
Test name
Test status
Simulation time 1097973187 ps
CPU time 17.61 seconds
Started Jul 09 04:56:06 PM PDT 24
Finished Jul 09 04:56:25 PM PDT 24
Peak memory 256068 kb
Host smart-6c955fb3-25ce-4f1f-8dd5-80be068d4ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20592
68238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2059268238
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1845320964
Short name T654
Test name
Test status
Simulation time 80349413349 ps
CPU time 1447.83 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 05:20:23 PM PDT 24
Peak memory 273536 kb
Host smart-0246dd8d-3a4f-4f69-ab9a-aa2d97d06327
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845320964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1845320964
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3562540600
Short name T361
Test name
Test status
Simulation time 13033671431 ps
CPU time 165.18 seconds
Started Jul 09 04:56:12 PM PDT 24
Finished Jul 09 04:58:57 PM PDT 24
Peak memory 256596 kb
Host smart-4cae4869-b027-4b73-a25d-11861c593943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35625
40600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3562540600
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2944313148
Short name T88
Test name
Test status
Simulation time 1815161077 ps
CPU time 24.74 seconds
Started Jul 09 04:56:12 PM PDT 24
Finished Jul 09 04:56:37 PM PDT 24
Peak memory 248692 kb
Host smart-819de3c6-9940-4b67-9f15-d4eed6c6d8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
13148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2944313148
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3758809654
Short name T664
Test name
Test status
Simulation time 40343322889 ps
CPU time 868.76 seconds
Started Jul 09 04:56:09 PM PDT 24
Finished Jul 09 05:10:39 PM PDT 24
Peak memory 273060 kb
Host smart-850c7cc3-1bd4-4b37-a44c-92ef4fffb77f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758809654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3758809654
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3587010954
Short name T78
Test name
Test status
Simulation time 36406163906 ps
CPU time 2032.68 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 273824 kb
Host smart-c5f31d02-d08b-4246-9041-29b090b1972c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587010954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3587010954
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3200164139
Short name T647
Test name
Test status
Simulation time 11346013000 ps
CPU time 477.66 seconds
Started Jul 09 04:56:11 PM PDT 24
Finished Jul 09 05:04:09 PM PDT 24
Peak memory 257524 kb
Host smart-2c05ec2f-546f-4f10-b1dc-756de40f491e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200164139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3200164139
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2475116610
Short name T269
Test name
Test status
Simulation time 1395436694 ps
CPU time 36.78 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 04:56:52 PM PDT 24
Peak memory 256608 kb
Host smart-672d54a3-7eaa-48d4-a00e-ffa51be3fb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751
16610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2475116610
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1779183767
Short name T196
Test name
Test status
Simulation time 712848418 ps
CPU time 50.46 seconds
Started Jul 09 04:56:12 PM PDT 24
Finished Jul 09 04:57:03 PM PDT 24
Peak memory 256572 kb
Host smart-a7ebf760-6177-4b55-a8ff-5954f669606e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791
83767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1779183767
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2517719195
Short name T514
Test name
Test status
Simulation time 1601452339 ps
CPU time 52.69 seconds
Started Jul 09 04:56:12 PM PDT 24
Finished Jul 09 04:57:06 PM PDT 24
Peak memory 249092 kb
Host smart-3b338d13-6d81-4284-905e-363009332049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25177
19195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2517719195
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2237849453
Short name T493
Test name
Test status
Simulation time 512907119 ps
CPU time 31.42 seconds
Started Jul 09 04:56:10 PM PDT 24
Finished Jul 09 04:56:43 PM PDT 24
Peak memory 257312 kb
Host smart-0f3b4a68-c5e8-4ee6-acc5-7edfb1fd059c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22378
49453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2237849453
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1572490596
Short name T604
Test name
Test status
Simulation time 37119439777 ps
CPU time 2287.79 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 05:34:23 PM PDT 24
Peak memory 289456 kb
Host smart-c2bd20fd-c9b5-4ab1-aaea-b2658d0fbeba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572490596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1572490596
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2935350508
Short name T439
Test name
Test status
Simulation time 15976147494 ps
CPU time 761.97 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 05:08:58 PM PDT 24
Peak memory 282156 kb
Host smart-31b78e60-7a58-4e1a-b463-2ee5949306e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935350508 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2935350508
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2221104620
Short name T542
Test name
Test status
Simulation time 20427063701 ps
CPU time 1130.53 seconds
Started Jul 09 04:56:15 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 272864 kb
Host smart-f55579aa-8a4e-4624-8365-3e452202f74f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221104620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2221104620
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.757897402
Short name T394
Test name
Test status
Simulation time 2889171040 ps
CPU time 99.96 seconds
Started Jul 09 04:56:16 PM PDT 24
Finished Jul 09 04:57:56 PM PDT 24
Peak memory 256728 kb
Host smart-60047c49-d411-40c7-8708-f8556c700db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75789
7402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.757897402
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2340372565
Short name T347
Test name
Test status
Simulation time 953405054 ps
CPU time 65.42 seconds
Started Jul 09 04:56:15 PM PDT 24
Finished Jul 09 04:57:21 PM PDT 24
Peak memory 249180 kb
Host smart-22d6e64d-15c4-48d4-b791-84ff8afe689d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23403
72565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2340372565
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2044620328
Short name T373
Test name
Test status
Simulation time 30327002576 ps
CPU time 1741.84 seconds
Started Jul 09 04:56:15 PM PDT 24
Finished Jul 09 05:25:18 PM PDT 24
Peak memory 273580 kb
Host smart-cf7e29da-acf4-415d-b927-1dff4e9ac9b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044620328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2044620328
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1032305137
Short name T303
Test name
Test status
Simulation time 69029616007 ps
CPU time 356.83 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 05:02:13 PM PDT 24
Peak memory 249280 kb
Host smart-66de9147-0c1f-4e62-bef9-a8a21bc82a65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032305137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1032305137
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1692700744
Short name T550
Test name
Test status
Simulation time 261465542 ps
CPU time 17.32 seconds
Started Jul 09 04:56:14 PM PDT 24
Finished Jul 09 04:56:32 PM PDT 24
Peak memory 249164 kb
Host smart-518daf2d-0748-4568-8225-6f0e7c6a043f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
00744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1692700744
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1599811905
Short name T69
Test name
Test status
Simulation time 106602125 ps
CPU time 10.82 seconds
Started Jul 09 04:56:15 PM PDT 24
Finished Jul 09 04:56:27 PM PDT 24
Peak memory 249192 kb
Host smart-c3155d98-3dd1-4e0d-a5a7-327bb0d41f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15998
11905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1599811905
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3372115249
Short name T698
Test name
Test status
Simulation time 1551588448 ps
CPU time 27.3 seconds
Started Jul 09 04:56:16 PM PDT 24
Finished Jul 09 04:56:44 PM PDT 24
Peak memory 257236 kb
Host smart-4f273147-fa4a-4f82-8865-d60ff90707c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
15249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3372115249
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.948389273
Short name T107
Test name
Test status
Simulation time 6537749586 ps
CPU time 226.41 seconds
Started Jul 09 04:56:17 PM PDT 24
Finished Jul 09 05:00:04 PM PDT 24
Peak memory 257560 kb
Host smart-bd35c43f-252e-46fb-b7e9-ae9ce3833878
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948389273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.948389273
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1830569354
Short name T683
Test name
Test status
Simulation time 49298481194 ps
CPU time 1153.9 seconds
Started Jul 09 04:56:24 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 286520 kb
Host smart-0e84d370-e98b-48f7-a5b4-b657667423a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830569354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1830569354
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.715716582
Short name T620
Test name
Test status
Simulation time 13069117198 ps
CPU time 154.68 seconds
Started Jul 09 04:56:19 PM PDT 24
Finished Jul 09 04:58:54 PM PDT 24
Peak memory 257468 kb
Host smart-3750ffee-5d67-4d8d-b877-7c3357a70532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71571
6582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.715716582
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2478732314
Short name T76
Test name
Test status
Simulation time 793651695 ps
CPU time 24.16 seconds
Started Jul 09 04:56:19 PM PDT 24
Finished Jul 09 04:56:44 PM PDT 24
Peak memory 249164 kb
Host smart-adb3af8d-8f80-4bb8-9f06-0eceb1110c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24787
32314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2478732314
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.615734400
Short name T586
Test name
Test status
Simulation time 38629073980 ps
CPU time 2404.3 seconds
Started Jul 09 04:56:18 PM PDT 24
Finished Jul 09 05:36:23 PM PDT 24
Peak memory 287156 kb
Host smart-c571a247-ae73-49ce-a3c9-120fff99f530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615734400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.615734400
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1819730667
Short name T693
Test name
Test status
Simulation time 30552087212 ps
CPU time 1248.25 seconds
Started Jul 09 04:56:18 PM PDT 24
Finished Jul 09 05:17:07 PM PDT 24
Peak memory 289292 kb
Host smart-18f764fc-038a-47d8-9a12-c39497bcae95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819730667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1819730667
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1152398564
Short name T628
Test name
Test status
Simulation time 12026933188 ps
CPU time 128.36 seconds
Started Jul 09 04:56:19 PM PDT 24
Finished Jul 09 04:58:27 PM PDT 24
Peak memory 249084 kb
Host smart-71907c22-74fd-4ff8-b8d0-2b9148781a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152398564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1152398564
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1105346421
Short name T258
Test name
Test status
Simulation time 221221348 ps
CPU time 10.4 seconds
Started Jul 09 04:56:19 PM PDT 24
Finished Jul 09 04:56:30 PM PDT 24
Peak memory 249152 kb
Host smart-99349dbe-12b4-413f-9426-a6962b711b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11053
46421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1105346421
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1112442268
Short name T250
Test name
Test status
Simulation time 1151249156 ps
CPU time 25.45 seconds
Started Jul 09 04:56:19 PM PDT 24
Finished Jul 09 04:56:45 PM PDT 24
Peak memory 256464 kb
Host smart-fc2e03ba-c9bb-4d46-ad21-bb5994f5dae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11124
42268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1112442268
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2829035713
Short name T580
Test name
Test status
Simulation time 211639410 ps
CPU time 13.34 seconds
Started Jul 09 04:56:24 PM PDT 24
Finished Jul 09 04:56:37 PM PDT 24
Peak memory 248680 kb
Host smart-89045417-5b6e-44a1-99a4-3ff866ba69ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28290
35713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2829035713
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.967557481
Short name T271
Test name
Test status
Simulation time 1211480594 ps
CPU time 29.13 seconds
Started Jul 09 04:56:19 PM PDT 24
Finished Jul 09 04:56:49 PM PDT 24
Peak memory 256440 kb
Host smart-ffbf9235-ef8b-4f47-97e8-5515aba65eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96755
7481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.967557481
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1973850325
Short name T4
Test name
Test status
Simulation time 7642377122 ps
CPU time 166.17 seconds
Started Jul 09 04:56:22 PM PDT 24
Finished Jul 09 04:59:09 PM PDT 24
Peak memory 257568 kb
Host smart-f779482f-29d6-4e44-83c3-cf54509da2d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973850325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1973850325
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2259338061
Short name T26
Test name
Test status
Simulation time 16307099789 ps
CPU time 819.21 seconds
Started Jul 09 04:56:23 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 287296 kb
Host smart-6248cbcc-447b-4244-8017-a31af8ee2ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259338061 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2259338061
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1146276384
Short name T1
Test name
Test status
Simulation time 228859641 ps
CPU time 3.86 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:21 PM PDT 24
Peak memory 249496 kb
Host smart-4efc7f09-a596-4efd-a323-60c8325769fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1146276384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1146276384
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1053897838
Short name T46
Test name
Test status
Simulation time 136497991946 ps
CPU time 2171.75 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 282024 kb
Host smart-e1ae6b38-38c1-48f0-9009-b73784610123
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053897838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1053897838
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.525630505
Short name T398
Test name
Test status
Simulation time 1298543425 ps
CPU time 6.5 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 04:54:29 PM PDT 24
Peak memory 249108 kb
Host smart-7a687fe6-ec67-4687-9365-1329a26567c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=525630505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.525630505
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3935130077
Short name T508
Test name
Test status
Simulation time 2057940770 ps
CPU time 82.71 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 04:55:43 PM PDT 24
Peak memory 256616 kb
Host smart-a1b2988d-90cb-4e43-a265-d0c239344d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39351
30077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3935130077
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3761657266
Short name T404
Test name
Test status
Simulation time 3167959283 ps
CPU time 40.86 seconds
Started Jul 09 04:54:20 PM PDT 24
Finished Jul 09 04:55:02 PM PDT 24
Peak memory 257544 kb
Host smart-756e1269-7896-4e43-8672-44886c5d8594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37616
57266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3761657266
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2468605603
Short name T297
Test name
Test status
Simulation time 223504811043 ps
CPU time 2199.79 seconds
Started Jul 09 04:54:18 PM PDT 24
Finished Jul 09 05:30:59 PM PDT 24
Peak memory 273772 kb
Host smart-c76c918b-9805-455c-aa6e-cb73d5f85dd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468605603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2468605603
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.921301022
Short name T451
Test name
Test status
Simulation time 37623064411 ps
CPU time 1137.07 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 05:13:15 PM PDT 24
Peak memory 285692 kb
Host smart-989c097a-3d72-4ec6-95c9-0ca8f63c03c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921301022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.921301022
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1985895500
Short name T510
Test name
Test status
Simulation time 9900218118 ps
CPU time 407.8 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 05:01:06 PM PDT 24
Peak memory 249344 kb
Host smart-6419731e-ea09-4221-b32c-b8a57bd0cdcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985895500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1985895500
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2551292518
Short name T584
Test name
Test status
Simulation time 721900138 ps
CPU time 35.43 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 257228 kb
Host smart-cbb09324-a346-426f-bbe7-959dceaf193a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512
92518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2551292518
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.23572600
Short name T456
Test name
Test status
Simulation time 587614787 ps
CPU time 39.11 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:57 PM PDT 24
Peak memory 257364 kb
Host smart-a9e0227b-acb3-4788-9a91-7c7f572fc443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23572
600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.23572600
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3859380154
Short name T280
Test name
Test status
Simulation time 3646007385 ps
CPU time 55.21 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 04:55:12 PM PDT 24
Peak memory 257428 kb
Host smart-a391a3fe-7d38-416a-8e50-aed5203c97eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38593
80154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3859380154
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1976164965
Short name T453
Test name
Test status
Simulation time 846390133 ps
CPU time 50.31 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 04:55:07 PM PDT 24
Peak memory 257404 kb
Host smart-69d4d02d-80b7-496f-b88e-84e5a2f0fda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19761
64965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1976164965
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3646423864
Short name T423
Test name
Test status
Simulation time 1603874452 ps
CPU time 128.08 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 04:56:25 PM PDT 24
Peak memory 257380 kb
Host smart-40c82b1f-681c-411d-8abc-8c5af3c30ed4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646423864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3646423864
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1050235929
Short name T234
Test name
Test status
Simulation time 258878702 ps
CPU time 3.15 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 04:54:26 PM PDT 24
Peak memory 249348 kb
Host smart-e9a68ed8-716e-46a2-b6de-fe9fa80d529a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1050235929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1050235929
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3974042108
Short name T649
Test name
Test status
Simulation time 13143253210 ps
CPU time 823.13 seconds
Started Jul 09 04:54:16 PM PDT 24
Finished Jul 09 05:08:00 PM PDT 24
Peak memory 273884 kb
Host smart-b9d55440-e6b3-4640-944a-6b6043cd514d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974042108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3974042108
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2160637841
Short name T469
Test name
Test status
Simulation time 778804127 ps
CPU time 19.28 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 04:54:39 PM PDT 24
Peak memory 249048 kb
Host smart-8cf1c54b-8795-4657-a1b2-ac75a8afafcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2160637841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2160637841
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3879205469
Short name T621
Test name
Test status
Simulation time 718081549 ps
CPU time 38.37 seconds
Started Jul 09 04:54:18 PM PDT 24
Finished Jul 09 04:54:57 PM PDT 24
Peak memory 256952 kb
Host smart-d3b9fafd-918c-4354-b70a-b76cf1920819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38792
05469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3879205469
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.918960878
Short name T449
Test name
Test status
Simulation time 8285450861 ps
CPU time 69.82 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:55:28 PM PDT 24
Peak memory 257480 kb
Host smart-12da9c50-a34f-45dc-9470-ff3de4b61f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91896
0878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.918960878
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2883296442
Short name T330
Test name
Test status
Simulation time 138417459682 ps
CPU time 1664.48 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 05:22:02 PM PDT 24
Peak memory 273756 kb
Host smart-848e05ad-341a-4407-8ecc-3f1fe409a223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883296442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2883296442
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.566520477
Short name T643
Test name
Test status
Simulation time 91976019623 ps
CPU time 1782.51 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 05:24:06 PM PDT 24
Peak memory 273612 kb
Host smart-89404dd3-70f3-4d09-bdbc-57930926c6d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566520477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.566520477
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3350647327
Short name T43
Test name
Test status
Simulation time 18624826456 ps
CPU time 388.1 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 05:00:52 PM PDT 24
Peak memory 255916 kb
Host smart-c17c8ad7-d80e-438d-89c2-131c093c30b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350647327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3350647327
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2257087745
Short name T434
Test name
Test status
Simulation time 891158005 ps
CPU time 44.92 seconds
Started Jul 09 04:54:20 PM PDT 24
Finished Jul 09 04:55:06 PM PDT 24
Peak memory 250136 kb
Host smart-fc9e9f7f-57a3-4321-841a-ca0e36454ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
87745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2257087745
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1629832933
Short name T680
Test name
Test status
Simulation time 1046039261 ps
CPU time 37.75 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:54:56 PM PDT 24
Peak memory 256912 kb
Host smart-c85e059c-0fbf-4ec3-9567-9cea095c7713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
32933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1629832933
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.437434087
Short name T287
Test name
Test status
Simulation time 2141786530 ps
CPU time 63.92 seconds
Started Jul 09 04:54:17 PM PDT 24
Finished Jul 09 04:55:22 PM PDT 24
Peak memory 257380 kb
Host smart-3cd50788-782c-46d6-b2c0-f10a892fd7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43743
4087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.437434087
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1391976368
Short name T270
Test name
Test status
Simulation time 1070215554 ps
CPU time 26.7 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:54:50 PM PDT 24
Peak memory 257080 kb
Host smart-b8030846-5da4-48b1-9311-d19caae5eb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
76368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1391976368
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3934527726
Short name T282
Test name
Test status
Simulation time 33135581538 ps
CPU time 1774.54 seconds
Started Jul 09 04:54:24 PM PDT 24
Finished Jul 09 05:23:59 PM PDT 24
Peak memory 283012 kb
Host smart-988593fb-bfdb-42d0-9bd0-4249beb0352b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934527726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3934527726
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.141902814
Short name T53
Test name
Test status
Simulation time 34455434734 ps
CPU time 2094.93 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 05:29:18 PM PDT 24
Peak memory 289692 kb
Host smart-3b7d62ad-cc35-46e4-9ec3-48c570176c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141902814 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.141902814
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1951857129
Short name T225
Test name
Test status
Simulation time 23738427 ps
CPU time 2.18 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 04:54:22 PM PDT 24
Peak memory 249432 kb
Host smart-210232d6-1a43-402a-90c6-ba949ec08610
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1951857129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1951857129
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1085521247
Short name T594
Test name
Test status
Simulation time 140055468541 ps
CPU time 1985.81 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 273724 kb
Host smart-bb99ada0-7349-48a9-ad4b-d9657aed28e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085521247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1085521247
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.752936700
Short name T644
Test name
Test status
Simulation time 1226821099 ps
CPU time 18.2 seconds
Started Jul 09 04:54:21 PM PDT 24
Finished Jul 09 04:54:40 PM PDT 24
Peak memory 249124 kb
Host smart-d2fac6db-23b9-44a9-9ea2-02002f83fe53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=752936700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.752936700
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2673167853
Short name T274
Test name
Test status
Simulation time 460224854 ps
CPU time 34.51 seconds
Started Jul 09 04:54:24 PM PDT 24
Finished Jul 09 04:54:59 PM PDT 24
Peak memory 248548 kb
Host smart-e57c0fb1-651c-4639-a0f8-e4f286197bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
67853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2673167853
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3521336777
Short name T42
Test name
Test status
Simulation time 453408304 ps
CPU time 30.51 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 249180 kb
Host smart-543710aa-5366-46c1-9e55-fd126caecfc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35213
36777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3521336777
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.58344407
Short name T547
Test name
Test status
Simulation time 86593909215 ps
CPU time 737.77 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 05:06:40 PM PDT 24
Peak memory 273856 kb
Host smart-f8a8aa76-2468-442c-bf59-52617979ab26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58344407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.58344407
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1723975553
Short name T329
Test name
Test status
Simulation time 51914854746 ps
CPU time 1854.53 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 05:25:14 PM PDT 24
Peak memory 274104 kb
Host smart-1b51c047-3aa9-4e26-a877-2fd51ca9d4a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723975553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1723975553
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.722742654
Short name T298
Test name
Test status
Simulation time 9459831865 ps
CPU time 425.17 seconds
Started Jul 09 04:54:19 PM PDT 24
Finished Jul 09 05:01:25 PM PDT 24
Peak memory 249204 kb
Host smart-812d49d7-6373-4803-9e21-bec3ab6cd099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722742654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.722742654
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4284432462
Short name T407
Test name
Test status
Simulation time 197746358 ps
CPU time 10.55 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:54:34 PM PDT 24
Peak memory 254676 kb
Host smart-b0d2b8c3-e243-41fa-817d-8a51f62c8307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
32462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4284432462
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2603768371
Short name T388
Test name
Test status
Simulation time 937818095 ps
CPU time 31.84 seconds
Started Jul 09 04:54:18 PM PDT 24
Finished Jul 09 04:54:51 PM PDT 24
Peak memory 249124 kb
Host smart-1ea449f9-f636-4ba6-a158-b72244f1c092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26037
68371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2603768371
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.446128410
Short name T523
Test name
Test status
Simulation time 205631736 ps
CPU time 6.21 seconds
Started Jul 09 04:54:21 PM PDT 24
Finished Jul 09 04:54:28 PM PDT 24
Peak memory 241048 kb
Host smart-63f86f0a-360e-41ae-923c-eac496709f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44612
8410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.446128410
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3202822781
Short name T195
Test name
Test status
Simulation time 684603121 ps
CPU time 49.89 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:55:14 PM PDT 24
Peak memory 257252 kb
Host smart-fee13f59-1e35-4db8-bad7-be28bf6f3829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32028
22781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3202822781
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3340247729
Short name T249
Test name
Test status
Simulation time 579914817 ps
CPU time 29.83 seconds
Started Jul 09 04:54:20 PM PDT 24
Finished Jul 09 04:54:50 PM PDT 24
Peak memory 249164 kb
Host smart-02da5d92-e825-409b-9497-9829831c08d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340247729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3340247729
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3727978039
Short name T189
Test name
Test status
Simulation time 23757363999 ps
CPU time 2469.02 seconds
Started Jul 09 04:54:20 PM PDT 24
Finished Jul 09 05:35:30 PM PDT 24
Peak memory 305848 kb
Host smart-448455e2-e881-404e-a648-9e2c6d86a945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727978039 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3727978039
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.886157101
Short name T68
Test name
Test status
Simulation time 53574469 ps
CPU time 3.45 seconds
Started Jul 09 04:54:21 PM PDT 24
Finished Jul 09 04:54:25 PM PDT 24
Peak memory 249440 kb
Host smart-bfb65ef1-0b43-4c46-b203-9ca7c5e8f239
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=886157101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.886157101
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1822073290
Short name T406
Test name
Test status
Simulation time 16000556880 ps
CPU time 1597.56 seconds
Started Jul 09 04:54:20 PM PDT 24
Finished Jul 09 05:20:59 PM PDT 24
Peak memory 289444 kb
Host smart-4cab9fba-d725-4427-9caa-d30bac22d107
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822073290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1822073290
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2055779175
Short name T418
Test name
Test status
Simulation time 2217790627 ps
CPU time 13.7 seconds
Started Jul 09 04:54:21 PM PDT 24
Finished Jul 09 04:54:35 PM PDT 24
Peak memory 249172 kb
Host smart-2516df02-393a-49f1-9855-3f81a87a11ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2055779175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2055779175
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.851085734
Short name T432
Test name
Test status
Simulation time 1769108509 ps
CPU time 144.11 seconds
Started Jul 09 04:54:32 PM PDT 24
Finished Jul 09 04:56:56 PM PDT 24
Peak memory 257392 kb
Host smart-10e2aa01-1950-4172-9154-36a7c26d339d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85108
5734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.851085734
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2863002784
Short name T440
Test name
Test status
Simulation time 348340960 ps
CPU time 31.8 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:54:56 PM PDT 24
Peak memory 248780 kb
Host smart-3b44f585-2724-4872-9f61-6e6554f8625f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630
02784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2863002784
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1250120795
Short name T324
Test name
Test status
Simulation time 78822554883 ps
CPU time 2620.17 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 05:38:06 PM PDT 24
Peak memory 290208 kb
Host smart-45cdeb99-9d92-415b-91ce-9e6bfb440d74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250120795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1250120795
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.553373778
Short name T496
Test name
Test status
Simulation time 136513406937 ps
CPU time 1997.2 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 05:27:41 PM PDT 24
Peak memory 273812 kb
Host smart-30cbc839-7d1f-43c5-b989-b35cc0ab124b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553373778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.553373778
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2862872970
Short name T637
Test name
Test status
Simulation time 6867617764 ps
CPU time 292.4 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:59:16 PM PDT 24
Peak memory 248092 kb
Host smart-b31f00df-ad13-4231-b6f9-71cfd757bbd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862872970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2862872970
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3577233278
Short name T357
Test name
Test status
Simulation time 203440502 ps
CPU time 15.22 seconds
Started Jul 09 04:54:20 PM PDT 24
Finished Jul 09 04:54:36 PM PDT 24
Peak memory 256792 kb
Host smart-35d0ab70-6da4-48e7-b133-dd60f06c29c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
33278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3577233278
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3066365503
Short name T261
Test name
Test status
Simulation time 521767907 ps
CPU time 10.08 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:54:44 PM PDT 24
Peak memory 248724 kb
Host smart-aa93ec33-3bb5-4039-b93a-bc33ed3ec45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30663
65503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3066365503
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1147747030
Short name T651
Test name
Test status
Simulation time 10164870862 ps
CPU time 61.25 seconds
Started Jul 09 04:54:33 PM PDT 24
Finished Jul 09 04:55:35 PM PDT 24
Peak memory 257472 kb
Host smart-0b0f3df7-97d4-4adb-9861-c881b54b7042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
47030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1147747030
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2936590257
Short name T410
Test name
Test status
Simulation time 2868047781 ps
CPU time 44.94 seconds
Started Jul 09 04:54:31 PM PDT 24
Finished Jul 09 04:55:17 PM PDT 24
Peak memory 257464 kb
Host smart-496a8493-5aa3-405f-94ae-b9c36058639a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29365
90257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2936590257
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4080286664
Short name T478
Test name
Test status
Simulation time 1207582044 ps
CPU time 28.81 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 04:54:53 PM PDT 24
Peak memory 257440 kb
Host smart-d9c87385-2972-45f8-9369-0a57573a7795
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080286664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4080286664
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.936056556
Short name T41
Test name
Test status
Simulation time 116662687 ps
CPU time 3.16 seconds
Started Jul 09 04:54:24 PM PDT 24
Finished Jul 09 04:54:28 PM PDT 24
Peak memory 249364 kb
Host smart-308e9bd4-a42e-4116-9764-5b1e33e1d005
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=936056556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.936056556
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.101684494
Short name T263
Test name
Test status
Simulation time 46032494560 ps
CPU time 1542.84 seconds
Started Jul 09 04:54:24 PM PDT 24
Finished Jul 09 05:20:08 PM PDT 24
Peak memory 273664 kb
Host smart-7e93c355-1e64-4105-84b6-27d4cc37d08e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101684494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.101684494
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.59899282
Short name T415
Test name
Test status
Simulation time 1704529551 ps
CPU time 12.47 seconds
Started Jul 09 04:54:27 PM PDT 24
Finished Jul 09 04:54:40 PM PDT 24
Peak memory 249144 kb
Host smart-3d9d6442-fec1-4642-8103-4a011db850a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=59899282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.59899282
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.289978159
Short name T609
Test name
Test status
Simulation time 4581955321 ps
CPU time 70.91 seconds
Started Jul 09 04:54:24 PM PDT 24
Finished Jul 09 04:55:36 PM PDT 24
Peak memory 257024 kb
Host smart-ea1700e8-ab6e-47fb-bdb6-5aa815a7bd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28997
8159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.289978159
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2587438443
Short name T48
Test name
Test status
Simulation time 274975151 ps
CPU time 33.69 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 04:55:00 PM PDT 24
Peak memory 257120 kb
Host smart-3584860b-c4b5-4a89-b1db-0f007d099dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25874
38443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2587438443
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3188241747
Short name T554
Test name
Test status
Simulation time 48173168231 ps
CPU time 1000.98 seconds
Started Jul 09 04:54:23 PM PDT 24
Finished Jul 09 05:11:05 PM PDT 24
Peak memory 269696 kb
Host smart-87204678-c95e-46ed-9fb9-1688c4b61e77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188241747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3188241747
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1339917925
Short name T532
Test name
Test status
Simulation time 109863452913 ps
CPU time 1143.64 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 05:13:39 PM PDT 24
Peak memory 273556 kb
Host smart-1d3f9a03-2ec5-4ba4-b2f0-b9aaa3e714f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339917925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1339917925
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2593680917
Short name T192
Test name
Test status
Simulation time 40838010571 ps
CPU time 386.21 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 05:01:01 PM PDT 24
Peak memory 248148 kb
Host smart-1a1daa19-ed32-4d86-a90a-0ba77b6ca542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593680917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2593680917
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1795021959
Short name T416
Test name
Test status
Simulation time 66798968 ps
CPU time 5.12 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 04:54:31 PM PDT 24
Peak memory 249260 kb
Host smart-61029f60-b322-4c68-88f4-04be4732cf1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17950
21959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1795021959
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2401038876
Short name T24
Test name
Test status
Simulation time 1728285147 ps
CPU time 21.72 seconds
Started Jul 09 04:54:34 PM PDT 24
Finished Jul 09 04:54:56 PM PDT 24
Peak memory 249212 kb
Host smart-b745dfa9-032a-4848-ad13-55f759728b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24010
38876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2401038876
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2840269633
Short name T366
Test name
Test status
Simulation time 1070448615 ps
CPU time 64.68 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 04:55:30 PM PDT 24
Peak memory 256616 kb
Host smart-cbeb4e9f-6cfa-4c1f-8237-74b0d9546edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28402
69633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2840269633
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2750298532
Short name T396
Test name
Test status
Simulation time 1082980808 ps
CPU time 59.88 seconds
Started Jul 09 04:54:22 PM PDT 24
Finished Jul 09 04:55:22 PM PDT 24
Peak memory 256292 kb
Host smart-bcbbcf4e-2927-4789-9956-f026ef859921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27502
98532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2750298532
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3519309135
Short name T362
Test name
Test status
Simulation time 7918576606 ps
CPU time 511.94 seconds
Started Jul 09 04:54:25 PM PDT 24
Finished Jul 09 05:02:58 PM PDT 24
Peak memory 257488 kb
Host smart-6d1b02dd-4ba9-4d90-aa08-fda71b475c07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519309135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3519309135
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3964884567
Short name T208
Test name
Test status
Simulation time 190569489831 ps
CPU time 3827.05 seconds
Started Jul 09 04:54:27 PM PDT 24
Finished Jul 09 05:58:16 PM PDT 24
Peak memory 322512 kb
Host smart-8d3652ba-b17f-4e22-8600-f1286bf0d1ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964884567 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3964884567
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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