Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T195,T196
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14785	0	0
DisabledNoTrigBkwd_A	2147483647	865174	0	0
DisabledNoTrigFwd_A	2147483647	1598907630	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14785	0	0
T8	83946	0	0	0
T9	731994	0	0	0
T14	946085	0	0	0
T19	47437	0	0	0
T22	4783	0	0	0
T25	25538	0	0	0
T29	352784	0	0	0
T44	3819	428	0	0
T45	49709	0	0	0
T46	3772	0	0	0
T47	7019	0	0	0
T52	365909	0	0	0
T174	0	463	0	0
T178	0	1338	0	0
T195	0	609	0	0
T196	3883	1173	0	0
T197	3638	1334	0	0
T198	0	1375	0	0
T199	0	204	0	0
T200	0	926	0	0
T201	0	686	0	0
T202	0	567	0	0
T203	0	514	0	0
T204	0	303	0	0
T205	0	712	0	0
T206	0	354	0	0
T207	0	994	0	0
T208	0	1128	0	0
T209	0	406	0	0
T210	0	944	0	0
T211	0	327	0	0
T212	9241	0	0	0
T213	625407	0	0	0
T214	6668	0	0	0
T215	150904	0	0	0
T216	37224	0	0	0
T217	24969	0	0	0
T218	19275	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	865174	0	0
T1	3591112	4412	0	0
T2	2978276	874	0	0
T3	6516	0	0	0
T4	498720	10	0	0
T5	1970820	4306	0	0
T6	3232944	1325	0	0
T7	3896920	8	0	0
T13	1041340	11	0	0
T16	92400	15	0	0
T17	101332	31	0	0
T18	0	70	0	0
T19	0	31	0	0
T22	0	1	0	0
T25	0	55	0	0
T43	0	308	0	0
T44	0	2	0	0
T45	0	21	0	0
T46	0	9	0	0
T47	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1598907630	0	0
T1	3591112	2086139	0	0
T2	2978276	2126745	0	0
T3	6516	6120	0	0
T4	498720	1438561	0	0
T5	1970820	1024707	0	0
T6	3232944	2425193	0	0
T7	3896920	1193758	0	0
T13	1041340	1036424	0	0
T16	92400	39643	0	0
T17	101332	74930	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T195,T202
1	1	Covered	T1,T2,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709467207	1604	0	0
DisabledNoTrigBkwd_A	709467207	283450	0	0
DisabledNoTrigFwd_A	709467207	373641446	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1604	0	0
T8	83946	0	0	0
T9	731994	0	0	0
T14	946085	0	0	0
T19	47437	0	0	0
T22	4783	0	0	0
T25	25538	0	0	0
T44	3819	428	0	0
T45	49709	0	0	0
T46	3772	0	0	0
T47	7019	0	0	0
T195	0	609	0	0
T202	0	567	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	283450	0	0
T1	897778	1459	0	0
T2	744569	89	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	8	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	24	0	0
T19	0	6	0	0
T25	0	55	0	0
T44	0	2	0	0
T45	0	11	0	0
T46	0	9	0	0
T47	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	373641446	0	0
T1	897778	442862	0	0
T2	744569	577070	0	0
T3	1629	1530	0	0
T4	124680	582	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	110551	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	23844	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T198,T207
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709467207	4411	0	0
DisabledNoTrigBkwd_A	709467207	172285	0	0
DisabledNoTrigFwd_A	709467207	400036897	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	4411	0	0
T29	352784	0	0	0
T52	365909	0	0	0
T174	0	463	0	0
T196	3883	1173	0	0
T198	0	1375	0	0
T207	0	994	0	0
T209	0	406	0	0
T212	9241	0	0	0
T213	625407	0	0	0
T214	6668	0	0	0
T215	150904	0	0	0
T216	37224	0	0	0
T217	24969	0	0	0
T218	19275	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	172285	0	0
T1	897778	2207	0	0
T2	744569	581	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1625	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	3	0	0
T16	23100	10	0	0
T17	25333	3	0	0
T18	0	19	0	0
T19	0	5	0	0
T45	0	3	0	0
T47	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	400036897	0	0
T1	897778	288733	0	0
T2	744569	304248	0	0
T3	1629	1530	0	0
T4	124680	919790	0	0
T5	492705	14785	0	0
T6	808236	806938	0	0
T7	974230	974152	0	0
T13	260335	259184	0	0
T16	23100	6996	0	0
T17	25333	23637	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T201,T204
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709467207	4932	0	0
DisabledNoTrigBkwd_A	709467207	212577	0	0
DisabledNoTrigFwd_A	709467207	394639675	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	4932	0	0
T73	349255	0	0	0
T74	58656	0	0	0
T91	47848	0	0	0
T178	0	1338	0	0
T187	48084	0	0	0
T188	75492	0	0	0
T189	4548	0	0	0
T190	738049	0	0	0
T191	439827	0	0	0
T197	3638	1334	0	0
T201	0	686	0	0
T204	0	303	0	0
T210	0	944	0	0
T211	0	327	0	0
T219	21145	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	212577	0	0
T1	897778	656	0	0
T2	744569	17	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	2679	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	5	0	0
T17	25333	28	0	0
T19	0	13	0	0
T22	0	1	0	0
T43	0	144	0	0
T45	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	394639675	0	0
T1	897778	479370	0	0
T2	744569	678530	0	0
T3	1629	1530	0	0
T4	124680	124133	0	0
T5	492705	25190	0	0
T6	808236	805612	0	0
T7	974230	107009	0	0
T13	260335	260328	0	0
T16	23100	2596	0	0
T17	25333	2170	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T200,T203
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709467207	3838	0	0
DisabledNoTrigBkwd_A	709467207	196862	0	0
DisabledNoTrigFwd_A	709467207	430589612	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	3838	0	0
T83	894041	0	0	0
T92	488418	0	0	0
T199	3500	204	0	0
T200	1766	926	0	0
T203	0	514	0	0
T205	0	712	0	0
T206	0	354	0	0
T208	0	1128	0	0
T220	114172	0	0	0
T221	79305	0	0	0
T222	225827	0	0	0
T223	25808	0	0	0
T224	164084	0	0	0
T225	77354	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	196862	0	0
T1	897778	90	0	0
T2	744569	187	0	0
T3	1629	0	0	0
T4	124680	10	0	0
T5	492705	2	0	0
T6	808236	1324	0	0
T7	974230	0	0	0
T13	260335	8	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	27	0	0
T19	0	7	0	0
T43	0	164	0	0
T45	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	430589612	0	0
T1	897778	875174	0	0
T2	744569	566897	0	0
T3	1629	1530	0	0
T4	124680	394056	0	0
T5	492705	492035	0	0
T6	808236	4485	0	0
T7	974230	2046	0	0
T13	260335	256584	0	0
T16	23100	7040	0	0
T17	25333	25279	0	0