Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T13 Yes T5,T6,T13 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T6 Yes T5,T13,T8 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T13,T8 Yes T4,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T13,T8,T49 Yes T13,T8,T49 INPUT
ping_ok_o Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T8,T49 Yes T8,T227,T52 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T227,T52 Yes T13,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T194,T26 Yes T8,T194,T26 INPUT
ping_ok_o Yes Yes T8,T26,T31 Yes T8,T26,T31 OUTPUT
integ_fail_o Yes Yes T2,T17,T13 Yes T2,T17,T13 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T194,T26 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T8,T194,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T13 Yes T5,T6,T13 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T6 Yes T13,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T26 Yes T4,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T8 Yes T4,T5,T8 INPUT
ping_ok_o Yes Yes T5,T8,T228 Yes T5,T8,T228 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T8 Yes T8,T28,T52 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T28,T52 Yes T4,T5,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T13 Yes T5,T6,T13 OUTPUT
integ_fail_o Yes Yes T1,T2,T13 Yes T1,T2,T13 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T6 Yes T5,T13,T8 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T13,T8 Yes T4,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T13,T23,T27 Yes T13,T23,T27 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T7 Yes T5,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T26 Yes T4,T5,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T49 Yes T5,T8,T49 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T2,T13,T23 Yes T2,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T49 Yes T5,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T26 Yes T5,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T13,T8,T23 Yes T13,T8,T23 INPUT
ping_ok_o Yes Yes T13,T8,T23 Yes T13,T8,T23 OUTPUT
integ_fail_o Yes Yes T6,T13,T23 Yes T6,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T8,T23 Yes T8,T23,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T23,T49 Yes T13,T8,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T8,T49 Yes T4,T8,T49 INPUT
ping_ok_o Yes Yes T8,T49,T26 Yes T8,T49,T26 OUTPUT
integ_fail_o Yes Yes T1,T13,T23 Yes T1,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T8,T49 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T4,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T14,T8 Yes T5,T14,T8 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T14,T8 Yes T5,T8,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T15 Yes T5,T14,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T7 Yes T5,T13,T7 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T6,T13,T48 Yes T6,T13,T48 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T7 Yes T8,T49,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T28 Yes T5,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T8 Yes T5,T6,T8 INPUT
ping_ok_o Yes Yes T5,T6,T8 Yes T5,T6,T8 OUTPUT
integ_fail_o Yes Yes T1,T6,T17 Yes T1,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T8 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T5,T6,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T49 Yes T5,T8,T49 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T49 Yes T8,T24,T82 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T24,T82 Yes T5,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T5,T48 Yes T1,T5,T48 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T8,T15,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T15,T49 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T14 Yes T4,T7,T14 INPUT
ping_ok_o Yes Yes T8,T31,T229 Yes T8,T31,T229 OUTPUT
integ_fail_o Yes Yes T2,T6,T48 Yes T2,T6,T48 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T7,T14 Yes T8,T31,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T31,T28 Yes T4,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T13,T8,T49 Yes T13,T8,T49 INPUT
ping_ok_o Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T50,T24 Yes T1,T50,T24 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T8,T49 Yes T8,T49,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T26 Yes T13,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T9 Yes T5,T13,T9 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T5,T17,T23 Yes T5,T17,T23 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T9 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T5,T13,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T2,T49 Yes T1,T2,T49 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T5,T8,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T31 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T49 Yes T5,T8,T49 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T14,T8 Yes T5,T14,T8 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T14,T8 Yes T5,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T26 Yes T5,T14,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T5,T17 Yes T1,T5,T17 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T5,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T26 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T15 Yes T5,T8,T15 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T6,T13,T23 Yes T6,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T15 Yes T5,T8,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T15 Yes T5,T8,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T14,T8 Yes T4,T14,T8 INPUT
ping_ok_o Yes Yes T8,T26,T61 Yes T8,T26,T61 OUTPUT
integ_fail_o Yes Yes T1,T17,T13 Yes T1,T17,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T14,T8 Yes T8,T26,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T28 Yes T4,T14,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T8,T49 Yes T7,T8,T49 INPUT
ping_ok_o Yes Yes T8,T49,T230 Yes T8,T49,T230 OUTPUT
integ_fail_o Yes Yes T2,T5,T13 Yes T2,T5,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T49 Yes T8,T49,T52 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T52 Yes T7,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T8 Yes T5,T13,T8 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T5,T13,T23 Yes T5,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T8 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T5,T13,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T5,T8,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T31 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T15 Yes T5,T8,T15 INPUT
ping_ok_o Yes Yes T5,T8,T23 Yes T5,T8,T23 OUTPUT
integ_fail_o Yes Yes T6,T48,T23 Yes T6,T48,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T15 Yes T5,T8,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T23 Yes T5,T8,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T49,T26 Yes T8,T49,T26 INPUT
ping_ok_o Yes Yes T8,T49,T26 Yes T8,T49,T26 OUTPUT
integ_fail_o Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T49,T26 Yes T8,T26,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T28 Yes T8,T49,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T15 Yes T5,T8,T15 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T5,T6,T13 Yes T5,T6,T13 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T15 Yes T8,T49,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T26 Yes T5,T8,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T26 Yes T5,T8,T26 INPUT
ping_ok_o Yes Yes T5,T8,T26 Yes T5,T8,T26 OUTPUT
integ_fail_o Yes Yes T2,T6,T17 Yes T2,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T26 Yes T5,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T26 Yes T5,T8,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T5,T8,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T49 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T9 Yes T5,T13,T9 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T9 Yes T8,T23,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T23,T26 Yes T5,T13,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T8 Yes T5,T13,T8 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T5,T17 Yes T1,T5,T17 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T8 Yes T13,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T26 Yes T5,T13,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T194 Yes T5,T8,T194 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T13,T26,T27 Yes T13,T26,T27 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T194 Yes T5,T8,T194 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T194 Yes T5,T8,T194 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T9,T8 Yes T5,T9,T8 INPUT
ping_ok_o Yes Yes T5,T8,T82 Yes T5,T8,T82 OUTPUT
integ_fail_o Yes Yes T2,T49,T31 Yes T2,T49,T31 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T9,T8 Yes T5,T8,T71 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T71 Yes T5,T9,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T49,T31 Yes T8,T49,T31 INPUT
ping_ok_o Yes Yes T8,T49,T31 Yes T8,T49,T31 OUTPUT
integ_fail_o Yes Yes T2,T13,T31 Yes T2,T13,T31 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T49,T31 Yes T8,T31,T79 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T31,T79 Yes T8,T49,T31 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T9 Yes T5,T13,T9 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T9 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T5,T13,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T8 Yes T5,T6,T8 OUTPUT
integ_fail_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T6 Yes T8,T31,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T31,T28 Yes T4,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T13,T8,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T23 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T8,T49 Yes T4,T8,T49 INPUT
ping_ok_o Yes Yes T8,T49,T26 Yes T8,T49,T26 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T8,T49 Yes T8,T26,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T28 Yes T4,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T14 Yes T5,T13,T14 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T26,T31,T231 Yes T26,T31,T231 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T14 Yes T8,T23,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T23,T26 Yes T5,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T8 Yes T5,T13,T8 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T5,T17,T23 Yes T5,T17,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T8 Yes T13,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T26 Yes T5,T13,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T15 Yes T5,T8,T15 INPUT
ping_ok_o Yes Yes T5,T8,T26 Yes T5,T8,T26 OUTPUT
integ_fail_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T15 Yes T5,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T26 Yes T5,T8,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T15 Yes T5,T8,T15 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T5,T13 Yes T1,T5,T13 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T15 Yes T5,T8,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T49 Yes T5,T8,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T13,T9 Yes T4,T13,T9 INPUT
ping_ok_o Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T6,T17 Yes T1,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T9 Yes T8,T49,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T26 Yes T4,T13,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T13,T8,T49 Yes T13,T8,T49 INPUT
ping_ok_o Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
integ_fail_o Yes Yes T2,T6,T13 Yes T2,T6,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T8,T49 Yes T13,T8,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T28 Yes T13,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T13,T8 Yes T4,T13,T8 INPUT
ping_ok_o Yes Yes T13,T8,T26 Yes T13,T8,T26 OUTPUT
integ_fail_o Yes Yes T5,T6,T13 Yes T5,T6,T13 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T8 Yes T8,T26,T229 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T229 Yes T4,T13,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T8,T23,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T23,T26 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T8 Yes T5,T13,T8 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T2,T23,T49 Yes T2,T23,T49 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T8 Yes T8,T23,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T23,T26 Yes T5,T13,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T2,T13,T49 Yes T2,T13,T49 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T13 Yes T5,T8,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T31 Yes T4,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T6,T13,T9 Yes T6,T13,T9 INPUT
ping_ok_o Yes Yes T6,T13,T8 Yes T6,T13,T8 OUTPUT
integ_fail_o Yes Yes T1,T2,T23 Yes T1,T2,T23 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T13,T9 Yes T6,T8,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T8,T26 Yes T6,T13,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T13,T8,T49 Yes T13,T8,T49 INPUT
ping_ok_o Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T2,T48 Yes T1,T2,T48 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T13,T8 Yes T5,T13,T8 INPUT
ping_ok_o Yes Yes T5,T13,T8 Yes T5,T13,T8 OUTPUT
integ_fail_o Yes Yes T2,T6,T17 Yes T2,T6,T17 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T8 Yes T8,T49,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T26 Yes T5,T13,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T8 Yes T4,T7,T8 INPUT
ping_ok_o Yes Yes T8,T49,T26 Yes T8,T49,T26 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T7,T8 Yes T8,T49,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T49,T26 Yes T4,T7,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T13,T8,T61 Yes T13,T8,T61 INPUT
ping_ok_o Yes Yes T13,T8,T61 Yes T13,T8,T61 OUTPUT
integ_fail_o Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T8,T232 Yes T13,T8,T52 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T8,T52 Yes T13,T8,T232 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T7,T8 Yes T5,T7,T8 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T17,T13,T23 Yes T17,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T8 Yes T8,T26,T231 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T231 Yes T5,T7,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T13,T9 Yes T4,T13,T9 INPUT
ping_ok_o Yes Yes T13,T8,T49 Yes T13,T8,T49 OUTPUT
integ_fail_o Yes Yes T5,T17,T23 Yes T5,T17,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T9 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T4,T13,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T7,T14 Yes T5,T7,T14 INPUT
ping_ok_o Yes Yes T5,T8,T23 Yes T5,T8,T23 OUTPUT
integ_fail_o Yes Yes T5,T6,T23 Yes T5,T6,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T14 Yes T5,T8,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T8,T23 Yes T5,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T6,T8 Yes T1,T6,T8 INPUT
ping_ok_o Yes Yes T1,T6,T8 Yes T1,T6,T8 OUTPUT
integ_fail_o Yes Yes T2,T13,T23 Yes T2,T13,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T6,T8 Yes T1,T8,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T49 Yes T1,T6,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T8 Yes T1,T5,T8 INPUT
ping_ok_o Yes Yes T1,T5,T8 Yes T1,T5,T8 OUTPUT
integ_fail_o Yes Yes T6,T13,T49 Yes T6,T13,T49 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T8 Yes T1,T5,T8 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T5,T8 Yes T1,T5,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T7,T14 Yes T5,T7,T14 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T14 Yes T7,T8,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T8,T49 Yes T5,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T8 Yes T1,T5,T8 INPUT
ping_ok_o Yes Yes T1,T5,T8 Yes T1,T5,T8 OUTPUT
integ_fail_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T8 Yes T1,T8,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T23 Yes T1,T5,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T26,T31 Yes T8,T26,T31 INPUT
ping_ok_o Yes Yes T8,T26,T31 Yes T8,T26,T31 OUTPUT
integ_fail_o Yes Yes T17,T50,T27 Yes T17,T50,T27 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T26,T31 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T8,T26,T31 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T8,T49 Yes T5,T8,T49 INPUT
ping_ok_o Yes Yes T5,T8,T49 Yes T5,T8,T49 OUTPUT
integ_fail_o Yes Yes T2,T5,T13 Yes T2,T5,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T49 Yes T8,T26,T31 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T26,T31 Yes T5,T8,T49 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

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