Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T5,T18
1	0	Covered	T2,T5,T19

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T19

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T20,T21
1	1	Covered	T1,T5,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T2,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T22,T23,T24
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T2,T25,T26
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T27,T28,T29
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T26,T30,T24
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T5
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T6
TimeoutSt->Phase0St	172	Covered	T1,T2,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T31,T24
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T25,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T30,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	847	0	0
CheckAccumTrig0_A	2147483647	2472	0	0
CheckAccumTrig1_A	2147483647	122	0	0
CheckClr_A	2147483647	1174	0	0
CheckEn_A	2147483647	1256611147	0	0
CheckPhase0_A	2147483647	2829	0	0
CheckPhase1_A	2147483647	2761	0	0
CheckPhase2_A	2147483647	2710	0	0
CheckPhase3_A	2147483647	2656	0	0
CheckTimeout0_A	2147483647	6189	0	0
CheckTimeoutSt1_A	2147483647	627764	0	0
CheckTimeoutSt2_A	2147483647	5770	0	0
CheckTimeoutStTrig_A	2147483647	286	0	0
ErrorStAllEscAsserted_A	2147483647	4267	0	0
ErrorStIsTerminal_A	2147483647	3547	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	847	0	0
T10	103736	126	0	0
T11	0	138	0	0
T12	0	128	0	0
T32	0	168	0	0
T33	0	287	0	0
T34	32524	0	0	0
T35	155868	0	0	0
T36	1209408	0	0	0
T37	1000268	0	0	0
T38	2437372	0	0	0
T39	103604	0	0	0
T40	43400	0	0	0
T41	501552	0	0	0
T42	493604	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T1	3591112	11	0	0
T2	2978276	16	0	0
T3	6516	0	0	0
T4	498720	1	0	0
T5	1970820	2	0	0
T6	3232944	1	0	0
T7	3896920	1	0	0
T13	1041340	2	0	0
T14	0	1	0	0
T16	92400	5	0	0
T17	101332	2	0	0
T18	0	2	0	0
T19	0	3	0	0
T23	0	2	0	0
T25	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0
T47	0	4	0	0
T48	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122	0	0
T2	744569	1	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	985410	1	0	0
T6	1616472	0	0	0
T7	1948460	0	0	0
T8	83946	0	0	0
T9	731994	0	0	0
T13	520670	0	0	0
T14	946085	0	0	0
T16	46200	0	0	0
T17	50666	0	0	0
T18	73524	0	0	0
T19	94874	1	0	0
T22	4783	1	0	0
T25	25538	0	0	0
T26	0	3	0	0
T28	0	3	0	0
T29	0	1	0	0
T31	0	3	0	0
T38	0	8	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	0	0	0
T46	3772	0	0	0
T47	7019	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1174	0	0
T1	1795556	6	0	0
T2	2978276	5	0	0
T3	6516	0	0	0
T4	498720	0	0	0
T5	1970820	1	0	0
T6	3232944	0	0	0
T7	3896920	0	0	0
T13	1041340	0	0	0
T16	92400	3	0	0
T17	101332	1	0	0
T18	73524	1	0	0
T19	0	5	0	0
T22	0	1	0	0
T23	0	2	0	0
T25	0	2	0	0
T26	0	20	0	0
T27	0	3	0	0
T30	0	1	0	0
T31	0	5	0	0
T45	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T61	0	6	0	0
T62	0	2	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256611147	0	0
T1	3591112	2044390	0	0
T2	2978276	1593225	0	0
T3	6516	6116	0	0
T4	498720	1302151	0	0
T5	1970820	526010	0	0
T6	3232944	1621892	0	0
T7	3896920	1193757	0	0
T13	1041340	532036	0	0
T16	92400	39642	0	0
T17	101332	72727	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2829	0	0
T1	3591112	15	0	0
T2	2978276	17	0	0
T3	6516	0	0	0
T4	498720	1	0	0
T5	1970820	4	0	0
T6	3232944	2	0	0
T7	3896920	1	0	0
T13	1041340	2	0	0
T16	92400	5	0	0
T17	101332	2	0	0
T18	0	5	0	0
T19	0	8	0	0
T25	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2761	0	0
T1	3591112	15	0	0
T2	2978276	16	0	0
T3	6516	0	0	0
T4	498720	1	0	0
T5	1970820	4	0	0
T6	3232944	2	0	0
T7	3896920	1	0	0
T13	1041340	2	0	0
T16	92400	5	0	0
T17	101332	2	0	0
T18	0	5	0	0
T19	0	8	0	0
T25	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2710	0	0
T1	3591112	15	0	0
T2	2978276	15	0	0
T3	6516	0	0	0
T4	498720	1	0	0
T5	1970820	4	0	0
T6	3232944	2	0	0
T7	3896920	1	0	0
T13	1041340	2	0	0
T16	92400	5	0	0
T17	101332	2	0	0
T18	0	5	0	0
T19	0	8	0	0
T25	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2656	0	0
T1	3591112	15	0	0
T2	2978276	15	0	0
T3	6516	0	0	0
T4	498720	1	0	0
T5	1970820	4	0	0
T6	3232944	2	0	0
T7	3896920	1	0	0
T13	1041340	2	0	0
T16	92400	5	0	0
T17	101332	2	0	0
T18	0	5	0	0
T19	0	8	0	0
T25	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6189	0	0
T1	1795556	7	0	0
T2	2233707	12	0	0
T3	4887	0	0	0
T4	374040	0	0	0
T5	1478115	2	0	0
T6	3232944	2	0	0
T7	3896920	0	0	0
T13	1041340	0	0	0
T16	92400	2	0	0
T17	101332	1	0	0
T18	73524	9	0	0
T19	47437	7	0	0
T22	0	3	0	0
T23	0	75	0	0
T26	0	27	0	0
T27	0	3	0	0
T31	0	4	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T64	0	8	0	0
T65	0	7	0	0
T66	0	19	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	627764	0	0
T1	1795556	1454	0	0
T2	2233707	479	0	0
T3	4887	0	0	0
T4	374040	0	0	0
T5	1478115	35	0	0
T6	3232944	104	0	0
T7	3896920	0	0	0
T13	1041340	0	0	0
T16	92400	286	0	0
T17	101332	606	0	0
T18	73524	696	0	0
T19	47437	843	0	0
T22	0	255	0	0
T23	0	5609	0	0
T26	0	3885	0	0
T27	0	173	0	0
T31	0	363	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	301	0	0
T47	0	78	0	0
T49	0	22	0	0
T50	0	1	0	0
T64	0	561	0	0
T65	0	739	0	0
T66	0	3324	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5770	0	0
T1	1795556	3	0	0
T2	2233707	11	0	0
T3	4887	0	0	0
T4	374040	0	0	0
T5	1478115	0	0	0
T6	3232944	1	0	0
T7	3896920	0	0	0
T13	1041340	0	0	0
T16	92400	2	0	0
T17	101332	1	0	0
T18	73524	6	0	0
T19	47437	2	0	0
T22	0	2	0	0
T23	0	74	0	0
T26	0	19	0	0
T27	0	3	0	0
T30	0	1	0	0
T31	0	4	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	2	0	0
T47	0	1	0	0
T64	0	8	0	0
T65	0	6	0	0
T66	0	30	0	0
T67	0	11	0	0
T68	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	286	0	0
T1	1795556	4	0	0
T2	1489138	0	0	0
T3	3258	0	0	0
T4	249360	0	0	0
T5	1478115	1	0	0
T6	2424708	0	0	0
T7	2922690	0	0	0
T9	731994	0	0	0
T13	781005	0	0	0
T14	946085	0	0	0
T16	69300	0	0	0
T17	75999	0	0	0
T18	36762	1	0	0
T19	94874	3	0	0
T22	4783	0	0	0
T24	0	1	0	0
T25	25538	0	0	0
T26	0	5	0	0
T28	0	4	0	0
T29	0	4	0	0
T30	0	2	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	0	0	0
T46	3772	0	0	0
T47	7019	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T67	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	9	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4267	0	0
T10	103736	718	0	0
T11	0	759	0	0
T12	0	658	0	0
T32	0	696	0	0
T33	0	1436	0	0
T34	32524	0	0	0
T35	155868	0	0	0
T36	1209408	0	0	0
T37	1000268	0	0	0
T38	2437372	0	0	0
T39	103604	0	0	0
T40	43400	0	0	0
T41	501552	0	0	0
T42	493604	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3547	0	0
T10	103736	598	0	0
T11	0	639	0	0
T12	0	538	0	0
T32	0	576	0	0
T33	0	1196	0	0
T34	32524	0	0	0
T35	155868	0	0	0
T36	1209408	0	0	0
T37	1000268	0	0	0
T38	2437372	0	0	0
T39	103604	0	0	0
T40	43400	0	0	0
T41	501552	0	0	0
T42	493604	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3591112	3591080	0	0
T2	2978276	2975844	0	0
T3	6516	6120	0	0
T4	498720	498684	0	0
T5	1970820	1970788	0	0
T6	3232944	3232632	0	0
T7	3896920	3896608	0	0
T13	1041340	1041312	0	0
T16	92400	92044	0	0
T17	101332	101116	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3591112	3591080	0	0
T2	2978276	2975844	0	0
T3	6516	6120	0	0
T4	498720	498684	0	0
T5	1970820	1970788	0	0
T6	3232944	3232632	0	0
T7	3896920	3896608	0	0
T13	1041340	1041312	0	0
T16	92400	92044	0	0
T17	101332	101116	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T2,T7,T44
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T1,T18,T49
1	0	Covered	T2,T26,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Not Covered
1	1	Covered	T1,T18,T49

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T44,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T47

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T44
1	Covered	T2,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T2,T45,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T7
Phase1St	198	Covered	T1,T2,T7
Phase2St	215	Covered	T1,T2,T7
Phase3St	233	Covered	T1,T2,T7
TerminalSt	249	Covered	T1,T2,T7
TimeoutSt	159	Covered	T1,T2,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T7
IdleSt->TimeoutSt	159	Covered	T1,T2,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T24,T77
Phase0St->Phase1St	198	Covered	T1,T2,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T25,T26,T24
Phase1St->Phase2St	215	Covered	T1,T2,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T28,T29
Phase2St->Phase3St	233	Covered	T1,T2,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T24,T78
Phase3St->TerminalSt	249	Covered	T1,T2,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T17
TimeoutSt->Phase0St	172	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T77,T71
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T26,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T24,T78
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709467207	264	0	0
CheckAccumTrig0_A	709467207	880	0	0
CheckAccumTrig1_A	709467207	48	0	0
CheckClr_A	709467207	438	0	0
CheckEn_A	709311888	294615186	0	0
CheckPhase0_A	709467207	988	0	0
CheckPhase1_A	709467207	962	0	0
CheckPhase2_A	709467207	942	0	0
CheckPhase3_A	709467207	918	0	0
CheckTimeout0_A	709467207	1605	0	0
CheckTimeoutSt1_A	709467207	164849	0	0
CheckTimeoutSt2_A	709467207	1474	0	0
CheckTimeoutStTrig_A	709467207	80	0	0
ErrorStAllEscAsserted_A	709467207	1122	0	0
ErrorStIsTerminal_A	709467207	942	0	0
EscStateOut_A	709310162	709234386	0	0
u_state_regs_A	709467207	709314146	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	264	0	0
T10	25934	50	0	0
T11	0	29	0	0
T12	0	48	0	0
T32	0	54	0	0
T33	0	83	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	880	0	0
T1	897778	6	0	0
T2	744569	5	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	1	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	1	0	0
T19	0	2	0	0
T25	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	48	0	0
T2	744569	1	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	0	0	0
T26	0	1	0	0
T28	0	3	0	0
T29	0	1	0	0
T38	0	6	0	0
T50	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	438	0	0
T1	897778	5	0	0
T2	744569	1	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	0	2	0	0
T25	0	2	0	0
T26	0	10	0	0
T27	0	3	0	0
T45	0	1	0	0
T50	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709311888	294615186	0	0
T1	897778	422692	0	0
T2	744569	145997	0	0
T3	1629	1529	0	0
T4	124680	582	0	0
T5	492705	492697	0	0
T6	808236	808157	0	0
T7	974230	110551	0	0
T13	260335	260328	0	0
T16	23100	23010	0	0
T17	25333	23843	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	988	0	0
T1	897778	8	0	0
T2	744569	6	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	1	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T25	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	962	0	0
T1	897778	8	0	0
T2	744569	6	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	1	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T25	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	942	0	0
T1	897778	8	0	0
T2	744569	6	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	1	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T25	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	918	0	0
T1	897778	8	0	0
T2	744569	6	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	1	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T25	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1605	0	0
T1	897778	4	0	0
T2	744569	5	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	1	0	0
T18	0	2	0	0
T22	0	1	0	0
T23	0	25	0	0
T26	0	12	0	0
T49	0	1	0	0
T50	0	1	0	0
T65	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	164849	0	0
T1	897778	1089	0	0
T2	744569	156	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	606	0	0
T18	0	132	0	0
T22	0	127	0	0
T23	0	1944	0	0
T26	0	1244	0	0
T49	0	18	0	0
T50	0	1	0	0
T65	0	104	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1474	0	0
T1	897778	2	0	0
T2	744569	4	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	1	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	0	24	0	0
T26	0	8	0	0
T31	0	1	0	0
T65	0	1	0	0
T67	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	80	0	0
T1	897778	2	0	0
T2	744569	0	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	1	0	0
T26	0	3	0	0
T29	0	3	0	0
T30	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1122	0	0
T10	25934	178	0	0
T11	0	199	0	0
T12	0	180	0	0
T32	0	192	0	0
T33	0	373	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	942	0	0
T10	25934	148	0	0
T11	0	169	0	0
T12	0	150	0	0
T32	0	162	0	0
T33	0	313	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709310162	709234386	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	709314146	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T2,T4,T15
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T2,T5,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T18
0	1	Covered	T5,T19,T26
1	0	Covered	T5,T26,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T5,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T26,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T18
1	0	Not Covered
1	1	Covered	T5,T19,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T19,T47

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T18,T47,T27

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T13,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T5
Phase1St	198	Covered	T1,T2,T5
Phase2St	215	Covered	T1,T2,T5
Phase3St	233	Covered	T1,T2,T5
TerminalSt	249	Covered	T1,T2,T5
TimeoutSt	159	Covered	T2,T5,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T16
IdleSt->TimeoutSt	159	Covered	T2,T5,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T79,T80,T81
Phase0St->Phase1St	198	Covered	T1,T2,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T2,T31,T82
Phase1St->Phase2St	215	Covered	T1,T2,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T79,T83,T84
Phase2St->Phase3St	233	Covered	T1,T2,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T85,T86
Phase3St->TerminalSt	249	Covered	T1,T2,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T18,T19
TimeoutSt->Phase0St	172	Covered	T5,T19,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T87,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T31,T82
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T79,T83,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T85,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709467207	180	0	0
CheckAccumTrig0_A	709467207	543	0	0
CheckAccumTrig1_A	709467207	27	0	0
CheckClr_A	709467207	268	0	0
CheckEn_A	709311888	303209270	0	0
CheckPhase0_A	709467207	637	0	0
CheckPhase1_A	709467207	615	0	0
CheckPhase2_A	709467207	603	0	0
CheckPhase3_A	709467207	595	0	0
CheckTimeout0_A	709467207	886	0	0
CheckTimeoutSt1_A	709467207	108383	0	0
CheckTimeoutSt2_A	709467207	778	0	0
CheckTimeoutStTrig_A	709467207	79	0	0
ErrorStAllEscAsserted_A	709467207	1058	0	0
ErrorStIsTerminal_A	709467207	878	0	0
EscStateOut_A	709310162	709234386	0	0
u_state_regs_A	709467207	709314146	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	180	0	0
T10	25934	22	0	0
T11	0	34	0	0
T12	0	32	0	0
T32	0	36	0	0
T33	0	56	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	543	0	0
T1	897778	3	0	0
T2	744569	4	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	3	0	0
T17	25333	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	27	0	0
T5	492705	1	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	0	0	0
T19	47437	0	0	0
T26	0	2	0	0
T31	0	1	0	0
T38	0	1	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	268	0	0
T2	744569	2	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	1	0	0
T18	36762	0	0	0
T19	0	4	0	0
T26	0	6	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T61	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709311888	303209270	0	0
T1	897778	288731	0	0
T2	744569	254718	0	0
T3	1629	1529	0	0
T4	124680	919789	0	0
T5	492705	14785	0	0
T6	808236	806937	0	0
T7	974230	974151	0	0
T13	260335	8242	0	0
T16	23100	6996	0	0
T17	25333	21436	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	637	0	0
T1	897778	3	0	0
T2	744569	4	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	2	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	3	0	0
T17	25333	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T45	0	1	0	0
T47	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	615	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	2	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	3	0	0
T17	25333	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T45	0	1	0	0
T47	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	603	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	2	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	3	0	0
T17	25333	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T45	0	1	0	0
T47	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	595	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	2	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	3	0	0
T17	25333	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T45	0	1	0	0
T47	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	886	0	0
T2	744569	1	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	2	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	2	0	0
T19	0	5	0	0
T23	0	2	0	0
T26	0	12	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T64	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	108383	0	0
T2	744569	47	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	35	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	232	0	0
T19	0	812	0	0
T23	0	140	0	0
T26	0	1480	0	0
T27	0	131	0	0
T45	0	138	0	0
T47	0	78	0	0
T64	0	506	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	778	0	0
T2	744569	1	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	2	0	0
T19	0	2	0	0
T23	0	2	0	0
T26	0	9	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T64	0	7	0	0
T66	0	11	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	79	0	0
T5	492705	1	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	0	0	0
T19	47437	3	0	0
T24	0	1	0	0
T26	0	1	0	0
T28	0	4	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T67	0	1	0	0
T71	0	7	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1058	0	0
T10	25934	189	0	0
T11	0	187	0	0
T12	0	158	0	0
T32	0	181	0	0
T33	0	343	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	878	0	0
T10	25934	159	0	0
T11	0	157	0	0
T12	0	128	0	0
T32	0	151	0	0
T33	0	283	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709310162	709234386	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	709314146	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T1,T2,T16
1	1	0	Covered	T1,T2,T18
1	1	1	Covered	T1,T2,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T26,T30
1	0	Covered	T19,T22,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T22,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T20
1	1	Covered	T1,T26,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T1,T2,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T6,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T26,T61,T30

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T19,T45

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T6,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T5
Phase1St	198	Covered	T1,T2,T5
Phase2St	215	Covered	T1,T2,T5
Phase3St	233	Covered	T1,T2,T5
TerminalSt	249	Covered	T1,T2,T5
TimeoutSt	159	Covered	T1,T2,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T5
IdleSt->TimeoutSt	159	Covered	T1,T2,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T29,T52
Phase0St->Phase1St	198	Covered	T1,T2,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T61,T76,T89
Phase1St->Phase2St	215	Covered	T1,T2,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T52,T85,T90
Phase2St->Phase3St	233	Covered	T1,T2,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T91,T92
Phase3St->TerminalSt	249	Covered	T1,T2,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T23
TimeoutSt->Phase0St	172	Covered	T1,T19,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T93,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T61,T76,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T52,T85,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T91,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709467207	199	0	0
CheckAccumTrig0_A	709467207	547	0	0
CheckAccumTrig1_A	709467207	26	0	0
CheckClr_A	709467207	254	0	0
CheckEn_A	709311888	319884378	0	0
CheckPhase0_A	709467207	632	0	0
CheckPhase1_A	709467207	623	0	0
CheckPhase2_A	709467207	615	0	0
CheckPhase3_A	709467207	602	0	0
CheckTimeout0_A	709467207	2165	0	0
CheckTimeoutSt1_A	709467207	195037	0	0
CheckTimeoutSt2_A	709467207	2068	0	0
CheckTimeoutStTrig_A	709467207	67	0	0
ErrorStAllEscAsserted_A	709467207	1053	0	0
ErrorStIsTerminal_A	709467207	873	0	0
EscStateOut_A	709310162	709234386	0	0
u_state_regs_A	709467207	709314146	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	199	0	0
T10	25934	18	0	0
T11	0	32	0	0
T12	0	33	0	0
T32	0	26	0	0
T33	0	90	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	547	0	0
T1	897778	1	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	1	0	0
T23	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	26	0	0
T8	83946	0	0	0
T9	731994	0	0	0
T14	946085	0	0	0
T15	111192	0	0	0
T19	47437	1	0	0
T22	4783	1	0	0
T25	25538	0	0	0
T31	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	49709	0	0	0
T46	3772	0	0	0
T47	7019	0	0	0
T49	0	1	0	0
T57	0	1	0	0
T82	0	1	0	0
T85	0	1	0	0
T95	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	254	0	0
T1	897778	1	0	0
T2	744569	2	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	1	0	0
T17	25333	0	0	0
T22	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T31	0	5	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709311888	319884378	0	0
T1	897778	457794	0	0
T2	744569	678523	0	0
T3	1629	1529	0	0
T4	124680	124133	0	0
T5	492705	14794	0	0
T6	808236	2313	0	0
T7	974230	107009	0	0
T13	260335	260328	0	0
T16	23100	2596	0	0
T17	25333	2170	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	632	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	1	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	623	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	1	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	615	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	1	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	602	0	0
T1	897778	3	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	1	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	2165	0	0
T1	897778	3	0	0
T2	744569	6	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T23	0	47	0	0
T26	0	3	0	0
T31	0	4	0	0
T49	0	1	0	0
T64	0	1	0	0
T66	0	13	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	195037	0	0
T1	897778	365	0	0
T2	744569	276	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T19	0	7	0	0
T22	0	1	0	0
T23	0	3484	0	0
T26	0	1161	0	0
T31	0	363	0	0
T49	0	4	0	0
T64	0	55	0	0
T66	0	2272	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	2068	0	0
T1	897778	1	0	0
T2	744569	6	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T23	0	47	0	0
T26	0	2	0	0
T30	0	1	0	0
T31	0	2	0	0
T64	0	1	0	0
T66	0	13	0	0
T67	0	8	0	0
T68	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	67	0	0
T1	897778	2	0	0
T2	744569	0	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T51	0	1	0	0
T53	0	3	0	0
T71	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1053	0	0
T10	25934	180	0	0
T11	0	187	0	0
T12	0	178	0	0
T32	0	156	0	0
T33	0	352	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	873	0	0
T10	25934	150	0	0
T11	0	157	0	0
T12	0	148	0	0
T32	0	126	0	0
T33	0	292	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709310162	709234386	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	709314146	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T16
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T6,T16,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T18
0	1	Covered	T19,T65,T30
1	0	Covered	T6,T18,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T16,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T18,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T18
1	0	Covered	T21
1	1	Covered	T19,T65,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T18,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T19,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T4,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T45,T49

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T6,T16,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T6,T16,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T96,T97
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T62,T31,T97
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T2,T77,T38
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T30,T38
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T16,T18
TimeoutSt->Phase0St	172	Covered	T6,T18,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T96,T97
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T62,T31,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T77,T73
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T30,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T45,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709467207	204	0	0
CheckAccumTrig0_A	709467207	502	0	0
CheckAccumTrig1_A	709467207	21	0	0
CheckClr_A	709467207	214	0	0
CheckEn_A	709311888	338902313	0	0
CheckPhase0_A	709467207	572	0	0
CheckPhase1_A	709467207	561	0	0
CheckPhase2_A	709467207	550	0	0
CheckPhase3_A	709467207	541	0	0
CheckTimeout0_A	709467207	1533	0	0
CheckTimeoutSt1_A	709467207	159495	0	0
CheckTimeoutSt2_A	709467207	1450	0	0
CheckTimeoutStTrig_A	709467207	60	0	0
ErrorStAllEscAsserted_A	709467207	1034	0	0
ErrorStIsTerminal_A	709467207	854	0	0
EscStateOut_A	709310162	709234386	0	0
u_state_regs_A	709467207	709314146	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	204	0	0
T10	25934	36	0	0
T11	0	43	0	0
T12	0	15	0	0
T32	0	52	0	0
T33	0	58	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	502	0	0
T1	897778	1	0	0
T2	744569	4	0	0
T3	1629	0	0	0
T4	124680	1	0	0
T5	492705	1	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T14	0	1	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	21	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	2	0	0
T19	47437	0	0	0
T24	0	1	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	3	0	0
T103	0	1	0	0
T104	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	214	0	0
T2	744569	1	0	0
T3	1629	0	0	0
T4	124680	0	0	0
T5	492705	0	0	0
T6	808236	0	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	36762	1	0	0
T23	0	1	0	0
T26	0	5	0	0
T27	0	1	0	0
T30	0	1	0	0
T31	0	6	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709311888	338902313	0	0
T1	897778	875173	0	0
T2	744569	513987	0	0
T3	1629	1529	0	0
T4	124680	257647	0	0
T5	492705	3734	0	0
T6	808236	4485	0	0
T7	974230	2046	0	0
T13	260335	3138	0	0
T16	23100	7040	0	0
T17	25333	25278	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	572	0	0
T1	897778	1	0	0
T2	744569	4	0	0
T3	1629	0	0	0
T4	124680	1	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	561	0	0
T1	897778	1	0	0
T2	744569	4	0	0
T3	1629	0	0	0
T4	124680	1	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	550	0	0
T1	897778	1	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	1	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	541	0	0
T1	897778	1	0	0
T2	744569	3	0	0
T3	1629	0	0	0
T4	124680	1	0	0
T5	492705	1	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	1	0	0
T16	23100	0	0	0
T17	25333	0	0	0
T18	0	2	0	0
T19	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1533	0	0
T6	808236	2	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	0	0	0
T18	36762	5	0	0
T19	47437	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T27	0	1	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	1	0	0
T65	0	6	0	0
T66	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	159495	0	0
T6	808236	104	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	286	0	0
T17	25333	0	0	0
T18	36762	332	0	0
T19	47437	24	0	0
T22	0	127	0	0
T23	0	41	0	0
T27	0	42	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	163	0	0
T65	0	635	0	0
T66	0	1052	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1450	0	0
T6	808236	1	0	0
T7	974230	0	0	0
T13	260335	0	0	0
T16	23100	2	0	0
T17	25333	0	0	0
T18	36762	3	0	0
T19	47437	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T43	167206	0	0	0
T44	3819	0	0	0
T45	49709	1	0	0
T65	0	5	0	0
T66	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	60	0	0
T8	83946	0	0	0
T9	731994	0	0	0
T14	946085	0	0	0
T15	111192	0	0	0
T19	47437	1	0	0
T22	4783	0	0	0
T25	25538	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T45	49709	0	0	0
T46	3772	0	0	0
T47	7019	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T65	0	1	0	0
T73	0	4	0	0
T96	0	1	0	0
T105	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	1034	0	0
T10	25934	171	0	0
T11	0	186	0	0
T12	0	142	0	0
T32	0	167	0	0
T33	0	368	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	854	0	0
T10	25934	141	0	0
T11	0	156	0	0
T12	0	112	0	0
T32	0	137	0	0
T33	0	308	0	0
T34	8131	0	0	0
T35	38967	0	0	0
T36	302352	0	0	0
T37	250067	0	0	0
T38	609343	0	0	0
T39	25901	0	0	0
T40	10850	0	0	0
T41	125388	0	0	0
T42	123401	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709310162	709234386	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709467207	709314146	0	0
T1	897778	897770	0	0
T2	744569	743961	0	0
T3	1629	1530	0	0
T4	124680	124671	0	0
T5	492705	492697	0	0
T6	808236	808158	0	0
T7	974230	974152	0	0
T13	260335	260328	0	0
T16	23100	23011	0	0
T17	25333	25279	0	0