Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	72178	1			T4	11		T5	2772		T20	148
class_i[0x1]	60475	1			T4	5108		T5	36		T16	3945
class_i[0x2]	56885	1			T5	24		T48	48		T17	10
class_i[0x3]	34428	1			T4	9		T16	11		T48	372

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	55409	1			T4	1278		T5	678		T20	8
alert[0x1]	56303	1			T4	1245		T5	671		T20	5
alert[0x2]	55366	1			T4	1312		T5	757		T20	129
alert[0x3]	56888	1			T4	1293		T5	726		T20	6

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

223687

1

T4

5128

T5

2832

T20

148

esc_ping_fail

279

1

T10

7

T11

6

T12

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	55325	1			T4	1278		T5	678		T20	8
esc_integrity_fail	alert[0x1]	56236	1			T4	1245		T5	671		T20	5
esc_integrity_fail	alert[0x2]	55303	1			T4	1312		T5	757		T20	129
esc_integrity_fail	alert[0x3]	56823	1			T4	1293		T5	726		T20	6
esc_ping_fail	alert[0x0]	84	1			T10	2		T11	1		T12	1
esc_ping_fail	alert[0x1]	67	1			T10	1		T11	3		T302	1
esc_ping_fail	alert[0x2]	63	1			T10	1		T191	2		T305	3
esc_ping_fail	alert[0x3]	65	1			T10	3		T11	2		T12	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	72097	1			T4	11		T5	2772		T20	148
esc_integrity_fail	class_i[0x1]	60394	1			T4	5108		T5	36		T16	3945
esc_integrity_fail	class_i[0x2]	56832	1			T5	24		T48	48		T17	10
esc_integrity_fail	class_i[0x3]	34364	1			T4	9		T16	11		T48	372
esc_ping_fail	class_i[0x0]	81	1			T302	2		T191	4		T312	3
esc_ping_fail	class_i[0x1]	81	1			T10	7		T191	2		T305	6
esc_ping_fail	class_i[0x2]	53	1			T12	1		T237	2		T105	2
esc_ping_fail	class_i[0x3]	64	1			T11	6		T12	1		T305	1