Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	614671084	0	0	616
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	614671084	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	614671084	614501076	0	0
tb.dut.CheckAccuCntDw	0	0	616	616	0	0
tb.dut.CheckEscCntDw	0	0	616	616	0	0
tb.dut.CheckNAlerts	0	0	616	616	0	0
tb.dut.CheckNClasses	0	0	616	616	0	0
tb.dut.CheckNEscSev	0	0	616	616	0	0
tb.dut.CrashdumpKnownO_A	0	0	614671084	614501076	0	0
tb.dut.EdnKnownO_A	0	0	614671084	614501076	0	0
tb.dut.EscPKnownO_A	0	0	614671084	614501076	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	614671084	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	614671084	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	614671084	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	614671084	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	614671084	80	0	0
tb.dut.IrqAKnownO_A	0	0	614671084	614501076	0	0
tb.dut.IrqBKnownO_A	0	0	614671084	614501076	0	0
tb.dut.IrqCKnownO_A	0	0	614671084	614501076	0	0
tb.dut.IrqDKnownO_A	0	0	614671084	614501076	0	0
tb.dut.TlAReadyKnownO_A	0	0	614671084	614501076	0	0
tb.dut.TlDValidKnownO_A	0	0	614671084	614501076	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	640646672	2300613	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	640646672	13882	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	640646672	13091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	640646672	12395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	640646672	12863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	640646672	12440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	640646672	13685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	640646672	13524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	640646672	12749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	640646672	13024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	640646672	13155	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	640646672	13106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	640646672	13345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	640646672	13262	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	640646672	12409	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	640646672	13111	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	640646672	13326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	640646672	13023	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	640646672	12850	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	640646672	12710	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	640646672	12941	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	640646672	12946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	640646672	13847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	640646672	12447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	640646672	12610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	640646672	12524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	640646672	13272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	640646672	12455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	640646672	14574	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	640646672	13610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	640646672	13156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	640646672	14386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	640646672	12198	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	640646672	13005	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	640646672	12475	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	640646672	12745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	640646672	13293	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	640646672	12547	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	640646672	13592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	640646672	13197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	640646672	12363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	640646672	14154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	640646672	12305	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	640646672	13013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	640646672	12936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	640646672	12611	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	640646672	13969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	640646672	12829	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	640646672	13079	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	640646672	13737	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	640646672	13646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	640646672	13187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	640646672	13849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	640646672	12651	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	640646672	13799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	640646672	13738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	640646672	13630	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	640646672	13441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	640646672	13583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	640646672	13011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	640646672	13491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	640646672	13276	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	640646672	13866	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	640646672	12792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	640646672	13602	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	640646672	13078	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	640646672	13184	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	640646672	12581	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	640646672	12226	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	640646672	13809	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	640646672	23925	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	640646672	12643	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	640646672	12441	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	640646672	13175	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	640646672	13326	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	640646672	13180	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	640646672	12619	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	640646672	13464	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	640646672	13780	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	614671084	6244	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	614671084	212666	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	614671084	305602568	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	614671084	263	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	614671084	776	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	614671084	49	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	614671084	391	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	614069008	225835987	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	614671084	873	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	614671084	859	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	614671084	842	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	614671084	825	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	614671084	2453	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	614671084	206976	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	614671084	2344	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	614671084	60	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	614671084	1456	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	614671084	1216	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	614067008	613998612	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	616	616	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	614671084	614501076	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	614671084	4133	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	614671084	173190	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	614671084	355240905	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	614671084	243	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	614671084	449	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	614671084	17	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	614671084	176	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	614069008	280969517	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	614671084	502	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	614671084	496	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	614671084	489	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	614671084	481	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	614671084	1851	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	614671084	148424	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	614671084	1794	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	614671084	40	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	614671084	1463	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	614671084	1223	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	614067008	613998612	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	616	616	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	614671084	614501076	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	614671084	3605	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	614671084	169585	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	614671084	328591604	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	614671084	249	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	614671084	432	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	614671084	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	614671084	205	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	614069008	269838077	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	614671084	511	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	614671084	499	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	614671084	493	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	614671084	487	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	614671084	2223	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	614671084	183411	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	614671084	2136	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	614671084	63	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	614671084	1490	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	614671084	1250	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	614067008	613998612	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	616	616	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	614671084	614501076	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	614671084	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	614671084	3246	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	614671084	158558	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	614671084	347550177	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	614671084	295	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	614671084	453	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	614671084	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	614671084	221	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	614069008	287145829	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	614671084	513	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	614671084	505	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	614671084	491	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	614671084	483	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	614671084	1884	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	614671084	149437	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	614671084	1815	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	614671084	41	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	614671084	1469	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	614671084	1229	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	614067008	613998612	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	616	616	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	614671084	614501076	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	640646672	121602334	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	640646672	639976497	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	640646672	639976497	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	640646672	161079379	0	0
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