Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	154	1			T4	1		T5	2		T7	1
index[0x1]	145	1			T6	1		T25	1		T16	1
index[0x2]	184	1			T3	1		T6	1		T16	3
index[0x3]	159	1			T27	2		T5	3		T16	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	208	1			T3	1		T6	1		T25	1
lens_less_than_1000[1]	123	1			T4	1		T5	1		T48	1
lens_less_than_1000[2]	98	1			T24	1		T73	1		T34	1
lens_less_than_1000[3]	65	1			T6	1		T16	1		T50	4
lens_less_than_1000[4]	52	1			T5	1		T16	1		T216	1
lens_less_than_1000[5]	37	1			T49	1		T213	1		T82	1
lens_less_than_1000[6]	20	1			T24	2		T32	1		T54	1
lens_less_than_1000[7]	18	1			T5	1		T24	1		T74	1
lens_less_than_1000[8]	7	1			T52	1		T281	1		T129	1
lens_less_than_1000[9]	2	1			T282	1		T283	1		-	-
len_2	12	1			T30	1		T93	1		T32	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1] , index[0x2]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	51	1			T5	1		T7	1		T50	1
index[0x0]	lens_less_than_1000[1]	18	1			T4	1		T131	1		T80	1
index[0x0]	lens_less_than_1000[2]	16	1			T284	1		T111	1		T98	1
index[0x0]	lens_less_than_1000[3]	17	1			T50	1		T36	1		T285	1
index[0x0]	lens_less_than_1000[4]	19	1			T216	1		T286	1		T88	1
index[0x0]	lens_less_than_1000[5]	16	1			T82	1		T40	1		T287	1
index[0x0]	lens_less_than_1000[6]	1	1			T102	1		-	-		-	-
index[0x0]	lens_less_than_1000[7]	10	1			T5	1		T74	1		T113	1
index[0x0]	lens_less_than_1000[8]	1	1			T288	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T282	1		-	-		-	-
index[0x0]	len_2	4	1			T30	1		T93	1		T116	2
index[0x1]	lens_less_than_1000[0]	47	1			T25	1		T24	1		T34	2
index[0x1]	lens_less_than_1000[1]	29	1			T34	1		T36	1		T284	1
index[0x1]	lens_less_than_1000[2]	26	1			T91	1		T33	1		T218	1
index[0x1]	lens_less_than_1000[3]	13	1			T6	1		T211	1		T285	1
index[0x1]	lens_less_than_1000[4]	13	1			T16	1		T52	1		T92	1
index[0x1]	lens_less_than_1000[5]	3	1			T49	1		T289	1		T290	1
index[0x1]	lens_less_than_1000[6]	7	1			T32	1		T54	1		T291	1
index[0x1]	lens_less_than_1000[7]	3	1			T217	1		T292	1		T271	1
index[0x1]	lens_less_than_1000[8]	2	1			T281	1		T293	1		-	-
index[0x1]	len_2	2	1			T101	1		T294	1		-	-
index[0x2]	lens_less_than_1000[0]	53	1			T3	1		T6	1		T16	2
index[0x2]	lens_less_than_1000[1]	43	1			T87	4		T57	2		T58	1
index[0x2]	lens_less_than_1000[2]	39	1			T24	1		T73	1		T74	1
index[0x2]	lens_less_than_1000[3]	17	1			T16	1		T295	1		T244	1
index[0x2]	lens_less_than_1000[4]	12	1			T74	1		T54	1		T296	2
index[0x2]	lens_less_than_1000[5]	7	1			T213	1		T32	1		T116	1
index[0x2]	lens_less_than_1000[6]	6	1			T24	2		T118	1		T258	1
index[0x2]	lens_less_than_1000[7]	1	1			T297	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	2	1			T52	1		T298	1		-	-
index[0x2]	len_2	4	1			T101	1		T120	1		T263	1
index[0x3]	lens_less_than_1000[0]	57	1			T27	2		T5	1		T16	1
index[0x3]	lens_less_than_1000[1]	33	1			T5	1		T48	1		T75	2
index[0x3]	lens_less_than_1000[2]	17	1			T34	1		T40	1		T122	1
index[0x3]	lens_less_than_1000[3]	18	1			T50	3		T212	1		T88	1
index[0x3]	lens_less_than_1000[4]	8	1			T5	1		T40	1		T243	1
index[0x3]	lens_less_than_1000[5]	11	1			T41	1		T111	1		T63	2
index[0x3]	lens_less_than_1000[6]	6	1			T88	1		T276	1		T299	3
index[0x3]	lens_less_than_1000[7]	4	1			T24	1		T300	1		T113	1
index[0x3]	lens_less_than_1000[8]	2	1			T129	1		T116	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T283	1		-	-		-	-
index[0x3]	len_2	2	1			T32	1		T301	1		-	-