Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	60	1			T34	2		T82	2		T32	3
class_index[0x1]	40	1			T5	1		T30	1		T73	1
class_index[0x2]	63	1			T5	1		T16	1		T52	1
class_index[0x3]	41	1			T5	2		T74	2		T40	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	88	1			T5	2		T16	1		T30	1
intr_timeout_cnt[1]	35	1			T5	2		T32	1		T45	1
intr_timeout_cnt[2]	19	1			T74	2		T40	1		T87	1
intr_timeout_cnt[3]	13	1			T82	1		T58	1		T129	1
intr_timeout_cnt[4]	13	1			T36	1		T64	1		T256	1
intr_timeout_cnt[5]	7	1			T54	1		T257	1		T258	2
intr_timeout_cnt[6]	8	1			T32	1		T87	1		T100	1
intr_timeout_cnt[7]	11	1			T87	4		T257	1		T259	1
intr_timeout_cnt[8]	5	1			T32	1		T129	1		T103	1
intr_timeout_cnt[9]	5	1			T32	1		T100	1		T260	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	23	1			T34	2		T82	2		T32	1
class_index[0x0]	intr_timeout_cnt[1]	10	1			T45	1		T84	1		T88	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T261	1		T258	1		T262	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T63	1		T263	1		T264	1
class_index[0x0]	intr_timeout_cnt[4]	7	1			T36	1		T256	1		T265	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T257	1		T247	1		T266	2
class_index[0x0]	intr_timeout_cnt[6]	2	1			T32	1		T247	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	6	1			T87	4		T267	1		T268	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T32	1		T100	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	14	1			T30	1		T73	1		T40	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T5	1		T32	1		T83	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T74	1		T119	1		T269	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T58	1		T270	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T64	1		T271	1		T262	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T258	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T272	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	4	1			T129	1		T103	1		T109	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T260	1		T273	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	30	1			T5	1		T16	1		T52	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T86	1		T267	1		T274	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T74	1		T275	1		T276	2
class_index[0x2]	intr_timeout_cnt[3]	6	1			T82	1		T129	1		T109	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T262	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T258	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	6	1			T87	1		T100	1		T119	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T259	1		T277	2		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T32	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	21	1			T5	1		T74	2		T62	1
class_index[0x3]	intr_timeout_cnt[1]	7	1			T5	1		T85	1		T58	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T40	1		T87	1		T63	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T127	1		T268	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T263	1		T278	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T54	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T257	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T277	1		-	-		-	-