Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340778	1			T1	9		T2	230		T3	53
all_values[1]	340778	1			T1	9		T2	230		T3	53
all_values[2]	340778	1			T1	9		T2	230		T3	53
all_values[3]	340778	1			T1	9		T2	230		T3	53

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678832

1

T1

12

T2

403

T3

99

auto[1]

684280

1

T1

24

T2

517

T3

113

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

821379

1

T1

32

T2

858

T3

109

auto[1]

541733

1

T1

4

T2

62

T3

103

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96010	1			T1	2		T2	75		T3	14
all_values[0]	auto[0]	auto[1]	73592	1			T1	2		T2	28		T3	13
all_values[0]	auto[1]	auto[0]	97290	1			T1	3		T2	93		T3	13
all_values[0]	auto[1]	auto[1]	73886	1			T1	2		T2	34		T3	13
all_values[1]	auto[0]	auto[0]	105498	1			T1	6		T2	89		T3	10
all_values[1]	auto[0]	auto[1]	63976	1			T3	10		T6	10		T25	3
all_values[1]	auto[1]	auto[0]	107292	1			T1	3		T2	141		T3	17
all_values[1]	auto[1]	auto[1]	64012	1			T3	16		T6	8		T27	6
all_values[2]	auto[0]	auto[0]	103912	1			T1	2		T2	110		T3	15
all_values[2]	auto[0]	auto[1]	65680	1			T3	13		T6	9		T25	1
all_values[2]	auto[1]	auto[0]	105228	1			T1	7		T2	120		T3	13
all_values[2]	auto[1]	auto[1]	65958	1			T3	12		T6	9		T25	2
all_values[3]	auto[0]	auto[0]	102737	1			T2	101		T3	12		T6	11
all_values[3]	auto[0]	auto[1]	67427	1			T3	12		T6	10		T25	2
all_values[3]	auto[1]	auto[0]	103412	1			T1	9		T2	129		T3	15
all_values[3]	auto[1]	auto[1]	67202	1			T3	14		T6	8		T25	1