Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340778	1			T1	9		T2	230		T3	53
all_pins[1]	340778	1			T1	9		T2	230		T3	53
all_pins[2]	340778	1			T1	9		T2	230		T3	53
all_pins[3]	340778	1			T1	9		T2	230		T3	53

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1092054	1			T1	34		T2	886		T3	157
values[0x1]	271058	1			T1	2		T2	34		T3	55
transitions[0x0=>0x1]	181325	1			T1	2		T2	34		T3	28
transitions[0x1=>0x0]	181585	1			T1	2		T2	34		T3	28

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	266892	1			T1	7		T2	196		T3	40
all_pins[0]	values[0x1]	73886	1			T1	2		T2	34		T3	13
all_pins[0]	transitions[0x0=>0x1]	73329	1			T1	2		T2	34		T3	13
all_pins[0]	transitions[0x1=>0x0]	66905	1			T3	14		T6	8		T25	1
all_pins[1]	values[0x0]	276766	1			T1	9		T2	230		T3	37
all_pins[1]	values[0x1]	64012	1			T3	16		T6	8		T27	6
all_pins[1]	transitions[0x0=>0x1]	33966	1			T3	7		T6	4		T27	4
all_pins[1]	transitions[0x1=>0x0]	43840	1			T1	2		T2	34		T3	4
all_pins[2]	values[0x0]	274820	1			T1	9		T2	230		T3	41
all_pins[2]	values[0x1]	65958	1			T3	12		T6	9		T25	2
all_pins[2]	transitions[0x0=>0x1]	36526	1			T3	1		T6	5		T25	2
all_pins[2]	transitions[0x1=>0x0]	34580	1			T3	5		T6	4		T27	3
all_pins[3]	values[0x0]	273576	1			T1	9		T2	230		T3	39
all_pins[3]	values[0x1]	67202	1			T3	14		T6	8		T25	1
all_pins[3]	transitions[0x0=>0x1]	37504	1			T3	7		T6	2		T27	1
all_pins[3]	transitions[0x1=>0x0]	36260	1			T3	5		T6	3		T25	1