Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91070	1			T4	745		T16	1252		T9	187
accum_cnt_1000	218048	1			T4	709		T5	747		T7	1588
accum_cnt_100	24685	1			T3	8		T4	35		T5	69
accum_cnt_50	66953	1			T2	83		T3	41		T6	63
accum_cnt_10	158906	1			T2	49		T3	19		T6	33
accum_cnt_0	405453	1			T1	28		T2	420		T3	36

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	251552	1			T1	7		T2	138		T3	26
class_index[0x1]	251552	1			T1	7		T2	138		T3	26
class_index[0x2]	251552	1			T1	7		T2	138		T3	26
class_index[0x3]	251552	1			T1	7		T2	138		T3	26

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24333	1			T4	521		T16	508		T204	155
class_index[0x0]	accum_cnt_1000	58395	1			T4	479		T16	614		T48	3
class_index[0x0]	accum_cnt_100	7069	1			T4	23		T20	2		T16	28
class_index[0x0]	accum_cnt_50	20550	1			T2	83		T3	14		T6	16
class_index[0x0]	accum_cnt_10	43134	1			T2	49		T3	8		T6	8
class_index[0x0]	accum_cnt_0	86293	1			T1	7		T2	6		T3	4
class_index[0x1]	accum_cnt_2000	23706	1			T4	224		T16	253		T18	650
class_index[0x1]	accum_cnt_1000	46878	1			T4	230		T16	238		T8	1111
class_index[0x1]	accum_cnt_100	6240	1			T3	8		T4	12		T16	22
class_index[0x1]	accum_cnt_50	19835	1			T3	12		T6	17		T4	8
class_index[0x1]	accum_cnt_10	39157	1			T3	4		T6	8		T29	4
class_index[0x1]	accum_cnt_0	104784	1			T1	7		T2	138		T3	2
class_index[0x2]	accum_cnt_2000	20551	1			T9	187		T34	240		T52	316
class_index[0x2]	accum_cnt_1000	60364	1			T5	747		T7	709		T9	868
class_index[0x2]	accum_cnt_100	6214	1			T5	69		T7	159		T9	46
class_index[0x2]	accum_cnt_50	13270	1			T6	17		T5	56		T7	116
class_index[0x2]	accum_cnt_10	41238	1			T6	7		T25	4		T27	1
class_index[0x2]	accum_cnt_0	100611	1			T1	7		T2	138		T3	26
class_index[0x3]	accum_cnt_2000	22480	1			T16	491		T34	504		T96	450
class_index[0x3]	accum_cnt_1000	52411	1			T7	879		T16	625		T48	1
class_index[0x3]	accum_cnt_100	5162	1			T7	85		T16	34		T49	3
class_index[0x3]	accum_cnt_50	13298	1			T3	15		T6	13		T29	2
class_index[0x3]	accum_cnt_10	35377	1			T3	7		T6	10		T27	13
class_index[0x3]	accum_cnt_0	113765	1			T1	7		T2	138		T3	4