Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5435	1			T32	2		T33	4		T36	107
alert[0x1]	5243	1			T5	13		T34	187		T52	20
alert[0x2]	3478	1			T5	40		T10	1		T18	55
alert[0x3]	5064	1			T5	1353		T18	4		T80	4
alert[0x4]	2564	1			T18	447		T11	1		T35	39
alert[0x5]	3946	1			T5	267		T18	68		T11	2
alert[0x6]	7688	1			T8	1		T11	1		T80	27
alert[0x7]	9469	1			T10	1		T12	1		T34	29
alert[0x8]	9081	1			T8	1		T24	25		T34	28
alert[0x9]	1991	1			T34	48		T191	1		T80	20
alert[0xa]	4993	1			T5	12		T24	5		T18	25
alert[0xb]	8804	1			T24	10		T10	1		T34	31
alert[0xc]	10919	1			T11	1		T52	61		T80	19
alert[0xd]	2979	1			T5	26		T18	103		T74	47
alert[0xe]	3274	1			T18	954		T302	1		T34	64
alert[0xf]	2492	1			T10	1		T52	345		T32	3
alert[0x10]	4160	1			T5	123		T34	474		T52	99
alert[0x11]	4691	1			T5	44		T24	2		T34	26
alert[0x12]	1627	1			T5	34		T16	2		T18	333
alert[0x13]	12528	1			T5	58		T9	1		T10	1
alert[0x14]	4502	1			T5	5		T24	4		T18	21
alert[0x15]	10103	1			T18	14		T11	1		T12	1
alert[0x16]	7089	1			T7	1		T40	8		T303	49
alert[0x17]	10913	1			T12	1		T34	351		T52	377
alert[0x18]	4615	1			T5	29		T16	2		T10	1
alert[0x19]	10493	1			T5	18		T302	1		T35	110
alert[0x1a]	2859	1			T5	11		T10	1		T18	263
alert[0x1b]	2414	1			T24	1		T34	27		T52	1
alert[0x1c]	9138	1			T7	1		T18	218		T216	1
alert[0x1d]	4047	1			T11	1		T12	1		T52	62
alert[0x1e]	2579	1			T5	60		T16	4		T12	1
alert[0x1f]	5917	1			T5	19		T7	1		T16	1
alert[0x20]	10634	1			T18	149		T34	29		T191	1
alert[0x21]	10470	1			T18	51		T34	99		T74	45
alert[0x22]	9704	1			T5	832		T52	1460		T69	2
alert[0x23]	9872	1			T5	50		T18	18		T34	6505
alert[0x24]	6012	1			T69	1		T36	385		T304	1
alert[0x25]	6552	1			T5	27		T191	1		T74	3
alert[0x26]	3486	1			T10	2		T18	16		T191	2
alert[0x27]	4885	1			T35	39		T80	245		T36	61
alert[0x28]	8186	1			T5	62		T74	291		T217	2
alert[0x29]	5102	1			T34	3		T52	605		T33	16
alert[0x2a]	6001	1			T18	18		T11	1		T12	1
alert[0x2b]	6384	1			T18	54		T11	1		T12	1
alert[0x2c]	12283	1			T8	1		T18	171		T34	5800
alert[0x2d]	8291	1			T34	308		T80	15		T32	35
alert[0x2e]	3458	1			T18	19		T35	219		T80	3
alert[0x2f]	8916	1			T9	1		T18	305		T34	477
alert[0x30]	2326	1			T5	12		T16	1		T10	1
alert[0x31]	4115	1			T5	67		T18	46		T12	1
alert[0x32]	1984	1			T11	1		T74	1		T35	32
alert[0x33]	11487	1			T5	34		T24	2		T10	1
alert[0x34]	2764	1			T17	1		T52	24		T74	4
alert[0x35]	2479	1			T5	552		T12	2		T52	46
alert[0x36]	8683	1			T5	29		T34	171		T52	189
alert[0x37]	12481	1			T11	1		T52	4		T305	1
alert[0x38]	12414	1			T18	45		T11	1		T52	228
alert[0x39]	7406	1			T5	69		T10	1		T34	40
alert[0x3a]	5301	1			T16	3		T18	7		T34	13
alert[0x3b]	3117	1			T5	1		T24	2		T35	83
alert[0x3c]	10708	1			T17	3		T18	38		T11	1
alert[0x3d]	7043	1			T5	869		T10	1		T12	1
alert[0x3e]	3303	1			T34	469		T33	334		T54	4
alert[0x3f]	3398	1			T5	641		T17	12		T18	51
alert[0x40]	7643	1			T5	189		T17	1		T18	5

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	158174	1			T16	5		T24	51		T18	7968
class_i[0x1]	59760	1			T5	5546		T16	3		T8	3
class_i[0x2]	112922	1			T7	3		T17	10		T10	11
class_i[0x3]	81127	1			T16	5		T9	2		T17	8

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

411287

1

T5

5546

T16

13

T17

18

alert_ping_fail

696

1

T7

3

T8

3

T9

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5426	1			T32	2		T33	4		T36	107
alert_integrity_fail	alert[0x1]	5232	1			T5	13		T34	187		T52	20
alert_integrity_fail	alert[0x2]	3468	1			T5	40		T18	55		T34	225
alert_integrity_fail	alert[0x3]	5055	1			T5	1353		T18	4		T80	4
alert_integrity_fail	alert[0x4]	2551	1			T18	447		T35	39		T80	177
alert_integrity_fail	alert[0x5]	3929	1			T5	267		T18	68		T34	67
alert_integrity_fail	alert[0x6]	7675	1			T80	27		T33	55		T84	3
alert_integrity_fail	alert[0x7]	9460	1			T34	29		T52	18		T33	12
alert_integrity_fail	alert[0x8]	9066	1			T24	25		T34	28		T52	189
alert_integrity_fail	alert[0x9]	1984	1			T34	48		T80	20		T82	6
alert_integrity_fail	alert[0xa]	4986	1			T5	12		T24	5		T18	25
alert_integrity_fail	alert[0xb]	8792	1			T24	10		T34	31		T74	9
alert_integrity_fail	alert[0xc]	10913	1			T52	61		T80	19		T33	1589
alert_integrity_fail	alert[0xd]	2975	1			T5	26		T18	103		T74	47
alert_integrity_fail	alert[0xe]	3267	1			T18	954		T34	64		T74	4
alert_integrity_fail	alert[0xf]	2475	1			T52	345		T32	3		T69	1
alert_integrity_fail	alert[0x10]	4151	1			T5	123		T34	474		T52	99
alert_integrity_fail	alert[0x11]	4688	1			T5	44		T24	2		T34	26
alert_integrity_fail	alert[0x12]	1618	1			T5	34		T16	2		T18	333
alert_integrity_fail	alert[0x13]	12518	1			T5	58		T34	33		T33	11
alert_integrity_fail	alert[0x14]	4493	1			T5	5		T24	4		T18	21
alert_integrity_fail	alert[0x15]	10085	1			T18	14		T34	6954		T52	81
alert_integrity_fail	alert[0x16]	7075	1			T40	8		T303	49		T97	100
alert_integrity_fail	alert[0x17]	10901	1			T34	351		T52	377		T35	251
alert_integrity_fail	alert[0x18]	4607	1			T5	29		T16	2		T74	6
alert_integrity_fail	alert[0x19]	10484	1			T5	18		T35	110		T80	1026
alert_integrity_fail	alert[0x1a]	2845	1			T5	11		T18	263		T52	3
alert_integrity_fail	alert[0x1b]	2397	1			T24	1		T34	27		T52	1
alert_integrity_fail	alert[0x1c]	9125	1			T18	218		T34	26		T74	1
alert_integrity_fail	alert[0x1d]	4036	1			T52	62		T35	129		T33	274
alert_integrity_fail	alert[0x1e]	2569	1			T5	60		T16	4		T32	7
alert_integrity_fail	alert[0x1f]	5902	1			T5	19		T16	1		T17	1
alert_integrity_fail	alert[0x20]	10623	1			T18	149		T34	29		T84	22
alert_integrity_fail	alert[0x21]	10460	1			T18	51		T34	99		T74	45
alert_integrity_fail	alert[0x22]	9691	1			T5	832		T52	1460		T69	2
alert_integrity_fail	alert[0x23]	9861	1			T5	50		T18	18		T34	6505
alert_integrity_fail	alert[0x24]	5999	1			T69	1		T36	385		T125	9
alert_integrity_fail	alert[0x25]	6541	1			T5	27		T74	3		T35	334
alert_integrity_fail	alert[0x26]	3471	1			T18	16		T36	61		T303	116
alert_integrity_fail	alert[0x27]	4879	1			T35	39		T80	245		T36	61
alert_integrity_fail	alert[0x28]	8176	1			T5	62		T74	291		T32	9
alert_integrity_fail	alert[0x29]	5093	1			T34	3		T52	605		T33	16
alert_integrity_fail	alert[0x2a]	5995	1			T18	18		T52	8		T74	58
alert_integrity_fail	alert[0x2b]	6372	1			T18	54		T35	94		T69	1
alert_integrity_fail	alert[0x2c]	12262	1			T18	171		T34	5800		T52	171
alert_integrity_fail	alert[0x2d]	8283	1			T34	308		T80	15		T32	35
alert_integrity_fail	alert[0x2e]	3447	1			T18	19		T35	219		T80	3
alert_integrity_fail	alert[0x2f]	8903	1			T18	305		T34	477		T52	1683
alert_integrity_fail	alert[0x30]	2312	1			T5	12		T16	1		T18	23
alert_integrity_fail	alert[0x31]	4103	1			T5	67		T18	46		T34	999
alert_integrity_fail	alert[0x32]	1975	1			T74	1		T35	32		T32	15
alert_integrity_fail	alert[0x33]	11473	1			T5	34		T24	2		T18	3326
alert_integrity_fail	alert[0x34]	2758	1			T17	1		T52	24		T74	4
alert_integrity_fail	alert[0x35]	2464	1			T5	552		T52	46		T80	57
alert_integrity_fail	alert[0x36]	8673	1			T5	29		T34	171		T52	189
alert_integrity_fail	alert[0x37]	12474	1			T52	4		T36	59		T243	41
alert_integrity_fail	alert[0x38]	12402	1			T18	45		T52	228		T74	22
alert_integrity_fail	alert[0x39]	7397	1			T5	69		T34	40		T35	1805
alert_integrity_fail	alert[0x3a]	5292	1			T16	3		T18	7		T34	13
alert_integrity_fail	alert[0x3b]	3102	1			T5	1		T24	2		T35	83
alert_integrity_fail	alert[0x3c]	10703	1			T17	3		T18	38		T34	33
alert_integrity_fail	alert[0x3d]	7029	1			T5	869		T74	5		T32	6
alert_integrity_fail	alert[0x3e]	3294	1			T34	469		T33	334		T54	4
alert_integrity_fail	alert[0x3f]	3394	1			T5	641		T17	12		T18	51
alert_integrity_fail	alert[0x40]	7638	1			T5	189		T17	1		T18	5
alert_ping_fail	alert[0x0]	9	1			T306	1		T307	1		T308	2
alert_ping_fail	alert[0x1]	11	1			T309	1		T307	1		T310	1
alert_ping_fail	alert[0x2]	10	1			T10	1		T306	1		T311	2
alert_ping_fail	alert[0x3]	9	1			T312	1		T304	1		T313	1
alert_ping_fail	alert[0x4]	13	1			T11	1		T312	1		T305	1
alert_ping_fail	alert[0x5]	17	1			T11	2		T313	1		T199	1
alert_ping_fail	alert[0x6]	13	1			T8	1		T11	1		T312	1
alert_ping_fail	alert[0x7]	9	1			T10	1		T12	1		T95	1
alert_ping_fail	alert[0x8]	15	1			T8	1		T312	1		T314	1
alert_ping_fail	alert[0x9]	7	1			T191	1		T237	1		T309	1
alert_ping_fail	alert[0xa]	7	1			T305	1		T237	1		T311	1
alert_ping_fail	alert[0xb]	12	1			T10	1		T304	3		T309	1
alert_ping_fail	alert[0xc]	6	1			T11	1		T237	1		T315	1
alert_ping_fail	alert[0xd]	4	1			T304	1		T307	1		T316	1
alert_ping_fail	alert[0xe]	7	1			T302	1		T191	1		T304	1
alert_ping_fail	alert[0xf]	17	1			T10	1		T304	2		T237	1
alert_ping_fail	alert[0x10]	9	1			T191	1		T305	1		T309	1
alert_ping_fail	alert[0x11]	3	1			T306	1		T307	1		T317	1
alert_ping_fail	alert[0x12]	9	1			T304	1		T196	1		T318	1
alert_ping_fail	alert[0x13]	10	1			T9	1		T10	1		T216	1
alert_ping_fail	alert[0x14]	9	1			T11	1		T319	1		T320	2
alert_ping_fail	alert[0x15]	18	1			T11	1		T12	1		T302	1
alert_ping_fail	alert[0x16]	14	1			T7	1		T306	1		T124	1
alert_ping_fail	alert[0x17]	12	1			T12	1		T312	1		T305	1
alert_ping_fail	alert[0x18]	8	1			T10	1		T305	1		T306	1
alert_ping_fail	alert[0x19]	9	1			T302	1		T304	1		T196	1
alert_ping_fail	alert[0x1a]	14	1			T10	1		T12	1		T304	2
alert_ping_fail	alert[0x1b]	17	1			T191	2		T305	1		T196	1
alert_ping_fail	alert[0x1c]	13	1			T7	1		T216	1		T237	1
alert_ping_fail	alert[0x1d]	11	1			T11	1		T12	1		T312	1
alert_ping_fail	alert[0x1e]	10	1			T12	1		T304	1		T237	1
alert_ping_fail	alert[0x1f]	15	1			T7	1		T11	1		T312	1
alert_ping_fail	alert[0x20]	11	1			T191	1		T305	1		T314	1
alert_ping_fail	alert[0x21]	10	1			T305	1		T124	2		T315	1
alert_ping_fail	alert[0x22]	13	1			T124	1		T321	1		T322	3
alert_ping_fail	alert[0x23]	11	1			T237	1		T307	1		T308	1
alert_ping_fail	alert[0x24]	13	1			T304	1		T306	1		T323	1
alert_ping_fail	alert[0x25]	11	1			T191	1		T304	1		T309	1
alert_ping_fail	alert[0x26]	15	1			T10	2		T191	2		T306	1
alert_ping_fail	alert[0x27]	6	1			T313	1		T309	1		T308	1
alert_ping_fail	alert[0x28]	10	1			T217	2		T304	1		T237	1
alert_ping_fail	alert[0x29]	9	1			T313	1		T314	1		T321	1
alert_ping_fail	alert[0x2a]	6	1			T11	1		T12	1		T306	1
alert_ping_fail	alert[0x2b]	12	1			T11	1		T12	1		T305	1
alert_ping_fail	alert[0x2c]	21	1			T8	1		T237	1		T306	1
alert_ping_fail	alert[0x2d]	8	1			T312	1		T318	1		T316	1
alert_ping_fail	alert[0x2e]	11	1			T71	1		T313	1		T324	1
alert_ping_fail	alert[0x2f]	13	1			T9	1		T71	1		T124	1
alert_ping_fail	alert[0x30]	14	1			T10	1		T11	2		T312	1
alert_ping_fail	alert[0x31]	12	1			T12	1		T313	1		T306	2
alert_ping_fail	alert[0x32]	9	1			T11	1		T314	1		T321	1
alert_ping_fail	alert[0x33]	14	1			T10	1		T11	1		T312	1
alert_ping_fail	alert[0x34]	6	1			T305	1		T314	1		T323	1
alert_ping_fail	alert[0x35]	15	1			T12	2		T312	1		T304	1
alert_ping_fail	alert[0x36]	10	1			T304	1		T306	1		T321	2
alert_ping_fail	alert[0x37]	7	1			T11	1		T305	1		T306	1
alert_ping_fail	alert[0x38]	12	1			T11	1		T304	1		T321	1
alert_ping_fail	alert[0x39]	9	1			T10	1		T105	1		T309	1
alert_ping_fail	alert[0x3a]	9	1			T191	1		T305	1		T313	1
alert_ping_fail	alert[0x3b]	15	1			T313	1		T105	1		T124	1
alert_ping_fail	alert[0x3c]	5	1			T11	1		T325	1		T326	1
alert_ping_fail	alert[0x3d]	14	1			T10	1		T12	1		T124	1
alert_ping_fail	alert[0x3e]	9	1			T105	1		T315	1		T327	1
alert_ping_fail	alert[0x3f]	4	1			T124	1		T196	1		T328	1
alert_ping_fail	alert[0x40]	5	1			T11	1		T304	1		T307	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	158020	1			T16	5		T24	51		T18	7968
alert_integrity_fail	class_i[0x1]	59687	1			T5	5546		T16	3		T52	10
alert_integrity_fail	class_i[0x2]	112664	1			T17	10		T34	6		T52	6296
alert_integrity_fail	class_i[0x3]	80916	1			T16	5		T17	8		T34	68
alert_ping_fail	class_i[0x0]	154	1			T12	10		T216	2		T191	1
alert_ping_fail	class_i[0x1]	73	1			T8	3		T10	2		T11	1
alert_ping_fail	class_i[0x2]	258	1			T7	3		T10	11		T12	1
alert_ping_fail	class_i[0x3]	211	1			T9	2		T11	18		T302	1