Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.65 99.97 100.00 100.00 99.38 99.52


Total test records in report: 821
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T770 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3360140279 Jul 11 04:47:11 PM PDT 24 Jul 11 04:47:17 PM PDT 24 63820502 ps
T771 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.174758709 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:41 PM PDT 24 8342710 ps
T772 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4221230946 Jul 11 04:47:18 PM PDT 24 Jul 11 04:47:31 PM PDT 24 261787405 ps
T773 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3354627195 Jul 11 04:46:58 PM PDT 24 Jul 11 04:47:04 PM PDT 24 115847611 ps
T774 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2485672707 Jul 11 04:46:57 PM PDT 24 Jul 11 04:53:01 PM PDT 24 23737392707 ps
T775 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2844919158 Jul 11 04:47:35 PM PDT 24 Jul 11 04:47:53 PM PDT 24 85216282 ps
T776 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.14685807 Jul 11 04:47:22 PM PDT 24 Jul 11 04:48:01 PM PDT 24 1762542667 ps
T146 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.649607725 Jul 11 04:47:23 PM PDT 24 Jul 11 05:04:47 PM PDT 24 54757133738 ps
T777 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.566405998 Jul 11 04:47:25 PM PDT 24 Jul 11 04:47:34 PM PDT 24 49144504 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.644926003 Jul 11 04:47:09 PM PDT 24 Jul 11 04:47:18 PM PDT 24 365571015 ps
T779 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3469494480 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:49 PM PDT 24 594322979 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3759206141 Jul 11 04:47:17 PM PDT 24 Jul 11 04:47:21 PM PDT 24 9861546 ps
T781 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1742272138 Jul 11 04:47:29 PM PDT 24 Jul 11 04:47:44 PM PDT 24 91167449 ps
T159 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1207313009 Jul 11 04:47:05 PM PDT 24 Jul 11 05:02:04 PM PDT 24 23923054409 ps
T782 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.4086953807 Jul 11 04:47:18 PM PDT 24 Jul 11 04:47:22 PM PDT 24 11915382 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2421021782 Jul 11 04:47:22 PM PDT 24 Jul 11 04:47:27 PM PDT 24 27076941 ps
T784 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3826608580 Jul 11 04:47:05 PM PDT 24 Jul 11 04:47:18 PM PDT 24 657811076 ps
T160 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3379078320 Jul 11 04:48:35 PM PDT 24 Jul 11 04:50:54 PM PDT 24 17328360194 ps
T785 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3373289833 Jul 11 04:48:05 PM PDT 24 Jul 11 04:48:42 PM PDT 24 1079128882 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1161858677 Jul 11 04:47:01 PM PDT 24 Jul 11 04:49:09 PM PDT 24 13590064416 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.73525701 Jul 11 04:47:09 PM PDT 24 Jul 11 04:47:15 PM PDT 24 92889386 ps
T788 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4291795521 Jul 11 04:47:28 PM PDT 24 Jul 11 04:47:47 PM PDT 24 105315033 ps
T789 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2434035720 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:40 PM PDT 24 9175532 ps
T790 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2294475411 Jul 11 04:47:29 PM PDT 24 Jul 11 04:47:35 PM PDT 24 12293077 ps
T164 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3041944596 Jul 11 04:47:18 PM PDT 24 Jul 11 04:49:32 PM PDT 24 3906631064 ps
T791 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.168763229 Jul 11 04:47:21 PM PDT 24 Jul 11 04:47:45 PM PDT 24 1142387729 ps
T182 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.555434374 Jul 11 04:47:35 PM PDT 24 Jul 11 04:49:05 PM PDT 24 5171388277 ps
T184 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2830565865 Jul 11 04:47:32 PM PDT 24 Jul 11 04:47:40 PM PDT 24 23325701 ps
T792 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4092237762 Jul 11 04:47:18 PM PDT 24 Jul 11 04:50:25 PM PDT 24 6080130567 ps
T793 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1561834600 Jul 11 04:47:32 PM PDT 24 Jul 11 04:47:40 PM PDT 24 31471998 ps
T178 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4202902783 Jul 11 04:47:11 PM PDT 24 Jul 11 04:47:14 PM PDT 24 57378160 ps
T161 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2496043387 Jul 11 04:47:16 PM PDT 24 Jul 11 04:56:23 PM PDT 24 7780948963 ps
T163 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.733182029 Jul 11 04:47:05 PM PDT 24 Jul 11 04:56:36 PM PDT 24 4662899676 ps
T794 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4284923446 Jul 11 04:47:04 PM PDT 24 Jul 11 04:47:08 PM PDT 24 6175284 ps
T181 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2720771660 Jul 11 04:47:22 PM PDT 24 Jul 11 04:47:29 PM PDT 24 100728244 ps
T795 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1850364570 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:40 PM PDT 24 9374006 ps
T796 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2963513795 Jul 11 04:47:14 PM PDT 24 Jul 11 04:47:28 PM PDT 24 625045162 ps
T166 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.193344314 Jul 11 04:47:20 PM PDT 24 Jul 11 05:06:08 PM PDT 24 57528618947 ps
T363 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4197986490 Jul 11 04:47:19 PM PDT 24 Jul 11 04:54:54 PM PDT 24 6142772049 ps
T797 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1209166117 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:46 PM PDT 24 19117415 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3487867016 Jul 11 04:47:24 PM PDT 24 Jul 11 04:47:36 PM PDT 24 79574923 ps
T799 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2282151238 Jul 11 04:47:20 PM PDT 24 Jul 11 04:47:26 PM PDT 24 10161628 ps
T800 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.759187196 Jul 11 04:47:29 PM PDT 24 Jul 11 04:47:36 PM PDT 24 16819409 ps
T801 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2000154238 Jul 11 04:47:35 PM PDT 24 Jul 11 04:47:46 PM PDT 24 144821572 ps
T171 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.521547478 Jul 11 04:47:26 PM PDT 24 Jul 11 05:02:01 PM PDT 24 13314106686 ps
T802 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1589752430 Jul 11 04:47:29 PM PDT 24 Jul 11 04:48:12 PM PDT 24 511887654 ps
T803 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2041594397 Jul 11 04:47:18 PM PDT 24 Jul 11 04:47:24 PM PDT 24 22375658 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.36606830 Jul 11 04:46:59 PM PDT 24 Jul 11 04:47:13 PM PDT 24 195172451 ps
T168 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.946067157 Jul 11 04:47:25 PM PDT 24 Jul 11 04:49:35 PM PDT 24 2046368260 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2014559746 Jul 11 04:47:30 PM PDT 24 Jul 11 04:47:45 PM PDT 24 265184954 ps
T179 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3496918172 Jul 11 04:47:19 PM PDT 24 Jul 11 04:48:07 PM PDT 24 618338743 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2613804087 Jul 11 04:47:23 PM PDT 24 Jul 11 04:47:32 PM PDT 24 62329630 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2997018333 Jul 11 04:47:01 PM PDT 24 Jul 11 04:47:04 PM PDT 24 6860895 ps
T808 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1803437341 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:50 PM PDT 24 140571614 ps
T170 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2765081123 Jul 11 04:47:37 PM PDT 24 Jul 11 04:50:14 PM PDT 24 7890577619 ps
T809 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2503430959 Jul 11 04:47:11 PM PDT 24 Jul 11 04:47:25 PM PDT 24 174012818 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1951752619 Jul 11 04:47:11 PM PDT 24 Jul 11 04:49:18 PM PDT 24 1629142145 ps
T811 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4195664044 Jul 11 04:47:24 PM PDT 24 Jul 11 04:47:33 PM PDT 24 34798354 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.702196162 Jul 11 04:48:58 PM PDT 24 Jul 11 04:49:39 PM PDT 24 1934522755 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3749891897 Jul 11 04:47:22 PM PDT 24 Jul 11 04:47:31 PM PDT 24 135663753 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.186182063 Jul 11 04:47:35 PM PDT 24 Jul 11 04:48:01 PM PDT 24 330774961 ps
T154 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3193940603 Jul 11 04:47:22 PM PDT 24 Jul 11 04:49:03 PM PDT 24 869199309 ps
T815 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.943325932 Jul 11 04:47:32 PM PDT 24 Jul 11 04:47:39 PM PDT 24 14320822 ps
T816 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.436078907 Jul 11 04:47:14 PM PDT 24 Jul 11 04:47:28 PM PDT 24 170975589 ps
T817 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1544290302 Jul 11 04:47:28 PM PDT 24 Jul 11 04:47:51 PM PDT 24 291168875 ps
T818 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2395793622 Jul 11 04:47:28 PM PDT 24 Jul 11 04:47:34 PM PDT 24 9445361 ps
T819 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.644107003 Jul 11 04:47:31 PM PDT 24 Jul 11 04:47:42 PM PDT 24 422512121 ps
T820 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1006704973 Jul 11 04:47:28 PM PDT 24 Jul 11 04:48:05 PM PDT 24 2459661189 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1650511025 Jul 11 04:47:21 PM PDT 24 Jul 11 04:47:48 PM PDT 24 616226458 ps
T167 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1118378398 Jul 11 04:47:22 PM PDT 24 Jul 11 04:53:26 PM PDT 24 12676691180 ps
T169 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2348363435 Jul 11 04:47:30 PM PDT 24 Jul 11 04:53:09 PM PDT 24 22603499793 ps

Test location /workspace/coverage/default/28.alert_handler_random_classes.2251265219
Short name T6
Test name
Test status
Simulation time 1067641249 ps
CPU time 73.63 seconds
Started Jul 11 06:46:52 PM PDT 24
Finished Jul 11 06:48:06 PM PDT 24
Peak memory 250244 kb
Host smart-fe0501a5-b8db-4bac-93af-a429b97a87c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
65219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2251265219
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2839288289
Short name T5
Test name
Test status
Simulation time 148866238920 ps
CPU time 2366.55 seconds
Started Jul 11 06:45:35 PM PDT 24
Finished Jul 11 07:25:03 PM PDT 24
Peak memory 283304 kb
Host smart-8c0f840f-06cb-4b27-97e9-0daed765010f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839288289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2839288289
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1243382231
Short name T74
Test name
Test status
Simulation time 72587795144 ps
CPU time 1347.96 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 07:08:09 PM PDT 24
Peak memory 282352 kb
Host smart-359c35f2-8d14-4f51-bdc4-1b4bd8cbdd87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243382231 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1243382231
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2559895318
Short name T14
Test name
Test status
Simulation time 211905379 ps
CPU time 14.81 seconds
Started Jul 11 06:44:15 PM PDT 24
Finished Jul 11 06:44:31 PM PDT 24
Peak memory 279252 kb
Host smart-9df8aa7b-140f-4fac-9920-700f20a83cb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2559895318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2559895318
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2432957541
Short name T9
Test name
Test status
Simulation time 128628135940 ps
CPU time 2014.93 seconds
Started Jul 11 06:49:41 PM PDT 24
Finished Jul 11 07:23:17 PM PDT 24
Peak memory 285748 kb
Host smart-b1ec3561-38f8-46d0-a6c2-00080e019682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432957541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2432957541
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1216449354
Short name T36
Test name
Test status
Simulation time 534285627388 ps
CPU time 2793.4 seconds
Started Jul 11 06:46:49 PM PDT 24
Finished Jul 11 07:33:24 PM PDT 24
Peak memory 290128 kb
Host smart-74071894-6026-44b3-bbde-2f84621b2cc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216449354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1216449354
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1438567046
Short name T147
Test name
Test status
Simulation time 4978762437 ps
CPU time 605.68 seconds
Started Jul 11 04:47:26 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 265252 kb
Host smart-d910f579-eb73-4d76-bdbe-611c7bac7490
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438567046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1438567046
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.598836785
Short name T98
Test name
Test status
Simulation time 89685470470 ps
CPU time 1514.28 seconds
Started Jul 11 06:46:08 PM PDT 24
Finished Jul 11 07:11:23 PM PDT 24
Peak memory 273864 kb
Host smart-bfff2766-af55-4d40-8a1d-1f343de60cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598836785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.598836785
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.138491761
Short name T142
Test name
Test status
Simulation time 13100197455 ps
CPU time 859.38 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 05:03:11 PM PDT 24
Peak memory 265112 kb
Host smart-6dabfa9b-11d4-4315-a8df-959299955329
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138491761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.138491761
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2787227388
Short name T34
Test name
Test status
Simulation time 46212676797 ps
CPU time 1284.07 seconds
Started Jul 11 06:47:05 PM PDT 24
Finished Jul 11 07:08:30 PM PDT 24
Peak memory 290120 kb
Host smart-a86c7504-1f56-4026-a87d-f6ded97b7f68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787227388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2787227388
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2324255883
Short name T7
Test name
Test status
Simulation time 44949615614 ps
CPU time 2582.88 seconds
Started Jul 11 06:44:40 PM PDT 24
Finished Jul 11 07:27:45 PM PDT 24
Peak memory 282168 kb
Host smart-c535a2a7-ad11-4a02-b144-b8021d2f1482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324255883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2324255883
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4226406086
Short name T134
Test name
Test status
Simulation time 5682115093 ps
CPU time 193.61 seconds
Started Jul 11 04:47:27 PM PDT 24
Finished Jul 11 04:50:45 PM PDT 24
Peak memory 272240 kb
Host smart-7a20dd1f-b9fe-4ca1-bcc6-ed226865b9dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4226406086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4226406086
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3615984300
Short name T11
Test name
Test status
Simulation time 52674078711 ps
CPU time 560.97 seconds
Started Jul 11 06:46:24 PM PDT 24
Finished Jul 11 06:55:47 PM PDT 24
Peak memory 249344 kb
Host smart-1649b8bf-b2e3-40bc-916c-6b061e34941e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615984300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3615984300
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.196854029
Short name T355
Test name
Test status
Simulation time 189133248 ps
CPU time 7.67 seconds
Started Jul 11 04:47:06 PM PDT 24
Finished Jul 11 04:47:15 PM PDT 24
Peak memory 237396 kb
Host smart-47c68bb5-ca2a-4a4b-a8a8-09cc732b3a90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=196854029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.196854029
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2562396237
Short name T210
Test name
Test status
Simulation time 10268734843 ps
CPU time 47.83 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 06:45:58 PM PDT 24
Peak memory 249420 kb
Host smart-bd0c4dab-ac1b-422a-824e-9036e8571255
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2562396237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2562396237
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1725129919
Short name T140
Test name
Test status
Simulation time 17690204088 ps
CPU time 609.03 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:57:32 PM PDT 24
Peak memory 265292 kb
Host smart-2e3ebb14-12da-4797-82ed-7b30b5e13fa9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725129919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1725129919
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3414424200
Short name T19
Test name
Test status
Simulation time 233310694008 ps
CPU time 1687.73 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 07:12:53 PM PDT 24
Peak memory 290016 kb
Host smart-955c529f-76ad-41ec-b4f5-7e2a1c19501d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414424200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3414424200
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.335589964
Short name T689
Test name
Test status
Simulation time 19844313796 ps
CPU time 1478.12 seconds
Started Jul 11 06:50:25 PM PDT 24
Finished Jul 11 07:15:04 PM PDT 24
Peak memory 288836 kb
Host smart-a6629a89-6e8f-4c35-ab0b-49217fc768ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335589964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.335589964
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1793656407
Short name T103
Test name
Test status
Simulation time 9495243015 ps
CPU time 37.03 seconds
Started Jul 11 06:44:21 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 256932 kb
Host smart-181d3988-968b-430b-9fd5-ca28836b332c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
56407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1793656407
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.480958814
Short name T153
Test name
Test status
Simulation time 5441421149 ps
CPU time 355.9 seconds
Started Jul 11 04:47:14 PM PDT 24
Finished Jul 11 04:53:11 PM PDT 24
Peak memory 272668 kb
Host smart-c6f15a7b-793e-472a-be87-785e27f79f7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=480958814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.480958814
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2275151589
Short name T350
Test name
Test status
Simulation time 22671998 ps
CPU time 1.43 seconds
Started Jul 11 04:47:30 PM PDT 24
Finished Jul 11 04:47:37 PM PDT 24
Peak memory 236616 kb
Host smart-a1a36df1-7b25-4e9f-b7e6-d0d2ce8cb5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2275151589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2275151589
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2892632495
Short name T8
Test name
Test status
Simulation time 62662934486 ps
CPU time 3521.63 seconds
Started Jul 11 06:46:57 PM PDT 24
Finished Jul 11 07:45:39 PM PDT 24
Peak memory 290324 kb
Host smart-29199e91-70ca-44e0-9ca3-4be8dfa5bdff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892632495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2892632495
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1222757472
Short name T148
Test name
Test status
Simulation time 24626837774 ps
CPU time 875.53 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 05:02:15 PM PDT 24
Peak memory 271944 kb
Host smart-f21cdc6a-062a-4d51-8150-d0508c565d8e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222757472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1222757472
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1232992494
Short name T304
Test name
Test status
Simulation time 54621673023 ps
CPU time 517.79 seconds
Started Jul 11 06:46:49 PM PDT 24
Finished Jul 11 06:55:27 PM PDT 24
Peak memory 249416 kb
Host smart-b2255785-f080-4446-86f4-84ab8e73b7b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232992494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1232992494
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.531427980
Short name T32
Test name
Test status
Simulation time 36185238333 ps
CPU time 1209.82 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 07:05:20 PM PDT 24
Peak memory 286412 kb
Host smart-d7c0246f-370f-427e-a058-2a0450d0a8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531427980 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.531427980
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1664626772
Short name T279
Test name
Test status
Simulation time 353734755 ps
CPU time 45.79 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:48:25 PM PDT 24
Peak memory 240344 kb
Host smart-efaf77fd-4a96-47c6-b797-42d35c534152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1664626772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1664626772
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1469256506
Short name T155
Test name
Test status
Simulation time 7853057415 ps
CPU time 288 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:53:32 PM PDT 24
Peak memory 263124 kb
Host smart-0d77d307-7d72-429f-b9c9-3d8e81c73b48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1469256506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1469256506
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4281402362
Short name T24
Test name
Test status
Simulation time 11825496273 ps
CPU time 1335.24 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 07:07:25 PM PDT 24
Peak memory 290284 kb
Host smart-c63726a8-abb7-44bf-9370-47c35913aa60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281402362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4281402362
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3855581312
Short name T320
Test name
Test status
Simulation time 62112509959 ps
CPU time 3385.85 seconds
Started Jul 11 06:48:18 PM PDT 24
Finished Jul 11 07:44:45 PM PDT 24
Peak memory 289704 kb
Host smart-b787cf4d-5fc0-4e0f-9495-aa7a8063ce54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855581312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3855581312
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2348363435
Short name T169
Test name
Test status
Simulation time 22603499793 ps
CPU time 333.21 seconds
Started Jul 11 04:47:30 PM PDT 24
Finished Jul 11 04:53:09 PM PDT 24
Peak memory 265416 kb
Host smart-ca05b92c-c166-4545-ad9d-741d504137c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2348363435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2348363435
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2275989157
Short name T322
Test name
Test status
Simulation time 43091718254 ps
CPU time 492.35 seconds
Started Jul 11 06:47:07 PM PDT 24
Finished Jul 11 06:55:20 PM PDT 24
Peak memory 249376 kb
Host smart-fa65a00a-e9d8-4cba-bdce-f0195b75d7a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275989157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2275989157
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2850601382
Short name T40
Test name
Test status
Simulation time 49909663521 ps
CPU time 3266.48 seconds
Started Jul 11 06:44:58 PM PDT 24
Finished Jul 11 07:39:26 PM PDT 24
Peak memory 298608 kb
Host smart-b3167a07-f95f-4ceb-81e5-1ab49706f635
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850601382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2850601382
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.739663772
Short name T337
Test name
Test status
Simulation time 37298282549 ps
CPU time 1280.49 seconds
Started Jul 11 06:51:02 PM PDT 24
Finished Jul 11 07:12:23 PM PDT 24
Peak memory 273920 kb
Host smart-7e42a04d-a292-43e5-8e05-285c9d875702
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739663772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.739663772
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1811113514
Short name T305
Test name
Test status
Simulation time 32110868334 ps
CPU time 341.8 seconds
Started Jul 11 06:45:29 PM PDT 24
Finished Jul 11 06:51:12 PM PDT 24
Peak memory 249352 kb
Host smart-dbca5e6f-6294-4a7e-8b86-ca72e5839dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811113514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1811113514
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.34489297
Short name T144
Test name
Test status
Simulation time 4600394988 ps
CPU time 283.81 seconds
Started Jul 11 04:47:24 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 265324 kb
Host smart-70633a0f-e0b1-486f-8537-9e482574b9b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34489297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors
.34489297
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2898286324
Short name T58
Test name
Test status
Simulation time 54449109125 ps
CPU time 3092.26 seconds
Started Jul 11 06:44:15 PM PDT 24
Finished Jul 11 07:35:49 PM PDT 24
Peak memory 289768 kb
Host smart-0cfd2fe9-6c1f-462a-830b-12350945ac26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898286324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2898286324
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3506123570
Short name T52
Test name
Test status
Simulation time 101393000100 ps
CPU time 2702.24 seconds
Started Jul 11 06:51:23 PM PDT 24
Finished Jul 11 07:36:26 PM PDT 24
Peak memory 306200 kb
Host smart-8a7b75bc-1d40-47b3-98ce-beb389971ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506123570 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3506123570
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.19706098
Short name T351
Test name
Test status
Simulation time 6446369 ps
CPU time 1.46 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237488 kb
Host smart-bbbe5285-dba8-48af-b6ce-54b6744db359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=19706098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.19706098
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2556491278
Short name T263
Test name
Test status
Simulation time 29969367005 ps
CPU time 1861.71 seconds
Started Jul 11 06:44:08 PM PDT 24
Finished Jul 11 07:15:11 PM PDT 24
Peak memory 286232 kb
Host smart-e9ccec3e-9c84-4900-a2ad-168c717086c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556491278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2556491278
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.733182029
Short name T163
Test name
Test status
Simulation time 4662899676 ps
CPU time 569.08 seconds
Started Jul 11 04:47:05 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 265456 kb
Host smart-6bbece22-c8f9-48c8-ad20-31047918057c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733182029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.733182029
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3107051855
Short name T71
Test name
Test status
Simulation time 12378169689 ps
CPU time 1054.26 seconds
Started Jul 11 06:44:59 PM PDT 24
Finished Jul 11 07:02:35 PM PDT 24
Peak memory 274040 kb
Host smart-16318327-6ee5-4089-81a2-8752741958cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107051855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3107051855
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3400651002
Short name T257
Test name
Test status
Simulation time 2243140876 ps
CPU time 44.41 seconds
Started Jul 11 06:46:10 PM PDT 24
Finished Jul 11 06:46:56 PM PDT 24
Peak memory 248836 kb
Host smart-67261ce2-fd31-47fc-9c60-b5dc5a7b358f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34006
51002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3400651002
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1173045439
Short name T124
Test name
Test status
Simulation time 38894614876 ps
CPU time 395.82 seconds
Started Jul 11 06:48:17 PM PDT 24
Finished Jul 11 06:54:54 PM PDT 24
Peak memory 248268 kb
Host smart-5568506e-1a26-42c6-b1b4-8a38350280f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173045439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1173045439
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2692851604
Short name T341
Test name
Test status
Simulation time 93865838993 ps
CPU time 2742.52 seconds
Started Jul 11 06:44:20 PM PDT 24
Finished Jul 11 07:30:04 PM PDT 24
Peak memory 289620 kb
Host smart-5d8f5482-df93-4659-8cc7-90edf439113a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692851604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2692851604
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.951962361
Short name T258
Test name
Test status
Simulation time 50172272540 ps
CPU time 2942.7 seconds
Started Jul 11 06:47:20 PM PDT 24
Finished Jul 11 07:36:24 PM PDT 24
Peak memory 306272 kb
Host smart-01ed4f89-88a2-4a97-85ed-94a893594a98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951962361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.951962361
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1115707649
Short name T129
Test name
Test status
Simulation time 191874442963 ps
CPU time 2863 seconds
Started Jul 11 06:47:56 PM PDT 24
Finished Jul 11 07:35:40 PM PDT 24
Peak memory 290428 kb
Host smart-83f55ca3-203d-434d-8592-f20a80d1a924
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115707649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1115707649
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3801278274
Short name T644
Test name
Test status
Simulation time 44097864264 ps
CPU time 525.95 seconds
Started Jul 11 06:48:57 PM PDT 24
Finished Jul 11 06:57:44 PM PDT 24
Peak memory 249408 kb
Host smart-8bd68e1f-cdac-453d-aba1-1874207ffb51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801278274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3801278274
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1510810870
Short name T299
Test name
Test status
Simulation time 41205543013 ps
CPU time 2650.41 seconds
Started Jul 11 06:49:17 PM PDT 24
Finished Jul 11 07:33:28 PM PDT 24
Peak memory 299540 kb
Host smart-b23e5d18-435f-4f48-a77a-9ede319e7330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510810870 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1510810870
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1699104547
Short name T174
Test name
Test status
Simulation time 81174975 ps
CPU time 5.04 seconds
Started Jul 11 04:47:06 PM PDT 24
Finished Jul 11 04:47:12 PM PDT 24
Peak memory 237856 kb
Host smart-ec8659af-0aab-4bb5-9f49-34d1df22ffab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1699104547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1699104547
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.156179
Short name T136
Test name
Test status
Simulation time 7956390835 ps
CPU time 161.66 seconds
Started Jul 11 04:47:30 PM PDT 24
Finished Jul 11 04:50:16 PM PDT 24
Peak memory 266432 kb
Host smart-76661842-361f-44c3-be55-08e3ce7fce10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=156179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.156179
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2765081123
Short name T170
Test name
Test status
Simulation time 7890577619 ps
CPU time 150.87 seconds
Started Jul 11 04:47:37 PM PDT 24
Finished Jul 11 04:50:14 PM PDT 24
Peak memory 265220 kb
Host smart-c47c32bd-96c2-41ab-b0d3-3aeea321f710
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2765081123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2765081123
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3287260246
Short name T236
Test name
Test status
Simulation time 56597552 ps
CPU time 3.52 seconds
Started Jul 11 06:44:08 PM PDT 24
Finished Jul 11 06:44:13 PM PDT 24
Peak memory 249556 kb
Host smart-245a8281-a79c-4a04-a610-1c0a9d242609
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287260246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3287260246
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2055207440
Short name T230
Test name
Test status
Simulation time 67477707 ps
CPU time 3.45 seconds
Started Jul 11 06:44:15 PM PDT 24
Finished Jul 11 06:44:19 PM PDT 24
Peak memory 249576 kb
Host smart-37e5166f-33b6-44c8-9a49-4dc9a6b2268c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2055207440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2055207440
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3430635156
Short name T21
Test name
Test status
Simulation time 50160931 ps
CPU time 4.36 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 06:44:51 PM PDT 24
Peak memory 249556 kb
Host smart-26a4fd1a-e2cf-4215-b40c-730801ed6d63
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3430635156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3430635156
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1064522254
Short name T222
Test name
Test status
Simulation time 41423614 ps
CPU time 3.99 seconds
Started Jul 11 06:45:10 PM PDT 24
Finished Jul 11 06:45:15 PM PDT 24
Peak memory 249716 kb
Host smart-af895bb6-8cfb-4b12-a572-7a6762207550
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1064522254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1064522254
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.193344314
Short name T166
Test name
Test status
Simulation time 57528618947 ps
CPU time 1124.58 seconds
Started Jul 11 04:47:20 PM PDT 24
Finished Jul 11 05:06:08 PM PDT 24
Peak memory 265160 kb
Host smart-5ceae1dc-d444-4662-a97a-7b2f375f8cdd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193344314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.193344314
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3761834235
Short name T283
Test name
Test status
Simulation time 78026981068 ps
CPU time 373.61 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 06:50:28 PM PDT 24
Peak memory 267356 kb
Host smart-f55ef221-53dd-4db5-8c55-c87e2d3be2e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761834235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3761834235
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3143002841
Short name T268
Test name
Test status
Simulation time 711421879 ps
CPU time 52.71 seconds
Started Jul 11 06:45:32 PM PDT 24
Finished Jul 11 06:46:26 PM PDT 24
Peak memory 256796 kb
Host smart-0e50bcc8-efb9-4095-9ffc-730b178382f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31430
02841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3143002841
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.693290667
Short name T284
Test name
Test status
Simulation time 57843826466 ps
CPU time 3333.12 seconds
Started Jul 11 06:45:55 PM PDT 24
Finished Jul 11 07:41:29 PM PDT 24
Peak memory 289900 kb
Host smart-7d4ae270-016f-4562-9510-5da4f1d009fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693290667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.693290667
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.292188402
Short name T271
Test name
Test status
Simulation time 170938075966 ps
CPU time 4340.01 seconds
Started Jul 11 06:46:12 PM PDT 24
Finished Jul 11 07:58:33 PM PDT 24
Peak memory 323000 kb
Host smart-a8e3f3c8-65c1-4fb2-8e02-dd52f8407c0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292188402 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.292188402
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3768782799
Short name T290
Test name
Test status
Simulation time 16012486915 ps
CPU time 1461.33 seconds
Started Jul 11 06:47:02 PM PDT 24
Finished Jul 11 07:11:24 PM PDT 24
Peak memory 302192 kb
Host smart-db1dfff1-2542-4bac-b43d-6c012d81f0d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768782799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3768782799
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3816216232
Short name T277
Test name
Test status
Simulation time 889399408 ps
CPU time 56.21 seconds
Started Jul 11 06:48:31 PM PDT 24
Finished Jul 11 06:49:28 PM PDT 24
Peak memory 257456 kb
Host smart-b8a724d3-e9a5-44a4-9ac7-cdef9779e2e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816216232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3816216232
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.396558736
Short name T603
Test name
Test status
Simulation time 19662145596 ps
CPU time 213.23 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:48:02 PM PDT 24
Peak memory 249368 kb
Host smart-505e9808-3a78-474d-938f-7b4fa3aa9c5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396558736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.396558736
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3209384371
Short name T162
Test name
Test status
Simulation time 2743059285 ps
CPU time 171.9 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:50:33 PM PDT 24
Peak memory 256284 kb
Host smart-400713ce-5b89-48bc-9e3d-99b848a84ee4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3209384371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3209384371
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3649802917
Short name T30
Test name
Test status
Simulation time 144303036 ps
CPU time 13.11 seconds
Started Jul 11 06:45:07 PM PDT 24
Finished Jul 11 06:45:21 PM PDT 24
Peak memory 249312 kb
Host smart-b4cdaa80-b5eb-4758-af2a-898aa6c44cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
02917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3649802917
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1118378398
Short name T167
Test name
Test status
Simulation time 12676691180 ps
CPU time 359.54 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:53:26 PM PDT 24
Peak memory 265236 kb
Host smart-06456d11-c493-48bf-ace8-c76339dbb1ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1118378398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1118378398
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4197986490
Short name T363
Test name
Test status
Simulation time 6142772049 ps
CPU time 451.29 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:54:54 PM PDT 24
Peak memory 265364 kb
Host smart-6343f7da-3ef4-4cc4-a7be-5d6bbbc419af
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197986490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4197986490
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.60790064
Short name T297
Test name
Test status
Simulation time 103235134912 ps
CPU time 3415.54 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 07:41:06 PM PDT 24
Peak memory 290104 kb
Host smart-743ec23d-e815-4567-9c14-daef0ce7899e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60790064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.60790064
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4208372683
Short name T317
Test name
Test status
Simulation time 3932713657 ps
CPU time 155.93 seconds
Started Jul 11 06:44:06 PM PDT 24
Finished Jul 11 06:46:43 PM PDT 24
Peak memory 249436 kb
Host smart-0c62b981-c61a-45fc-9ee5-311332024da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208372683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4208372683
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2506587504
Short name T376
Test name
Test status
Simulation time 19200335626 ps
CPU time 124.05 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 06:46:17 PM PDT 24
Peak memory 257188 kb
Host smart-f962b22f-4c7e-4163-aa18-3d3656627005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
87504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2506587504
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1200260771
Short name T687
Test name
Test status
Simulation time 60133544910 ps
CPU time 584.52 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 06:54:29 PM PDT 24
Peak memory 249360 kb
Host smart-816a5014-c3f2-47fc-95dd-aad13442ba21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200260771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1200260771
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.687076204
Short name T330
Test name
Test status
Simulation time 39602444270 ps
CPU time 2519.47 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 07:27:10 PM PDT 24
Peak memory 289948 kb
Host smart-2ead504c-e75a-400f-8326-786058c3647e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687076204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.687076204
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1923772404
Short name T335
Test name
Test status
Simulation time 107160415679 ps
CPU time 1657.75 seconds
Started Jul 11 06:45:34 PM PDT 24
Finished Jul 11 07:13:13 PM PDT 24
Peak memory 273324 kb
Host smart-9600aaaf-9d06-4a49-809f-8d37ee27e2ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923772404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1923772404
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1169393417
Short name T54
Test name
Test status
Simulation time 1176551653 ps
CPU time 25.56 seconds
Started Jul 11 06:46:04 PM PDT 24
Finished Jul 11 06:46:30 PM PDT 24
Peak memory 256812 kb
Host smart-aba2aa03-ddd9-4431-810b-468967f3ac88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
93417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1169393417
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2156479349
Short name T281
Test name
Test status
Simulation time 15411323666 ps
CPU time 1281.22 seconds
Started Jul 11 06:46:56 PM PDT 24
Finished Jul 11 07:08:18 PM PDT 24
Peak memory 282208 kb
Host smart-c7c06819-9b25-4c9b-b21f-1fee38c94366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156479349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2156479349
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1308836514
Short name T288
Test name
Test status
Simulation time 3587666112 ps
CPU time 216.67 seconds
Started Jul 11 06:44:19 PM PDT 24
Finished Jul 11 06:47:57 PM PDT 24
Peak memory 257160 kb
Host smart-091c2279-6b86-4d92-9705-5c228f69a239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
36514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1308836514
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3283448519
Short name T272
Test name
Test status
Simulation time 801306634 ps
CPU time 14.89 seconds
Started Jul 11 06:47:32 PM PDT 24
Finished Jul 11 06:47:48 PM PDT 24
Peak memory 249332 kb
Host smart-cfc70e17-f435-49ae-9661-8baeeff722ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
48519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3283448519
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.145661713
Short name T273
Test name
Test status
Simulation time 668098073 ps
CPU time 10.96 seconds
Started Jul 11 06:48:01 PM PDT 24
Finished Jul 11 06:48:12 PM PDT 24
Peak memory 248808 kb
Host smart-6a7e32a0-73be-4e54-abd3-77974785d7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14566
1713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.145661713
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3489589144
Short name T262
Test name
Test status
Simulation time 169728134286 ps
CPU time 2703.51 seconds
Started Jul 11 06:48:49 PM PDT 24
Finished Jul 11 07:33:54 PM PDT 24
Peak memory 290372 kb
Host smart-ce2b0036-5191-4aa0-9694-cb2f59099e89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489589144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3489589144
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2679410543
Short name T102
Test name
Test status
Simulation time 103353932945 ps
CPU time 1769.38 seconds
Started Jul 11 06:49:55 PM PDT 24
Finished Jul 11 07:19:26 PM PDT 24
Peak memory 273608 kb
Host smart-ab6cbb85-eb50-4b5a-b2fc-42ee1983b9d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679410543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2679410543
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2071436971
Short name T282
Test name
Test status
Simulation time 1265059529 ps
CPU time 27.88 seconds
Started Jul 11 06:50:22 PM PDT 24
Finished Jul 11 06:50:50 PM PDT 24
Peak memory 248616 kb
Host smart-348954ce-8933-4090-b0a5-a7c03a08909f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20714
36971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2071436971
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3048679916
Short name T294
Test name
Test status
Simulation time 83478023980 ps
CPU time 1338.41 seconds
Started Jul 11 06:44:33 PM PDT 24
Finished Jul 11 07:06:53 PM PDT 24
Peak memory 273480 kb
Host smart-36b23d45-30b9-4d5c-b37d-bfe653649422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048679916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3048679916
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3243837074
Short name T13
Test name
Test status
Simulation time 4353666377 ps
CPU time 162.66 seconds
Started Jul 11 06:44:10 PM PDT 24
Finished Jul 11 06:46:54 PM PDT 24
Peak memory 268508 kb
Host smart-06d2c62a-b6de-48cb-9033-a19cd1dc6653
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3243837074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3243837074
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2720771660
Short name T181
Test name
Test status
Simulation time 100728244 ps
CPU time 3.08 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:29 PM PDT 24
Peak memory 237400 kb
Host smart-b872ad0b-d99d-4e50-a28c-0250738b2543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2720771660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2720771660
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2515358019
Short name T149
Test name
Test status
Simulation time 126612899146 ps
CPU time 1236.45 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 05:07:38 PM PDT 24
Peak memory 265372 kb
Host smart-1da62963-c3d5-432d-997f-3e50ed00a278
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515358019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2515358019
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1303833408
Short name T143
Test name
Test status
Simulation time 1578568514 ps
CPU time 92.3 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:48:33 PM PDT 24
Peak memory 265220 kb
Host smart-c4653507-d7f3-4e33-9c57-40d43f1d2658
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1303833408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1303833408
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3496918172
Short name T179
Test name
Test status
Simulation time 618338743 ps
CPU time 44.56 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:48:07 PM PDT 24
Peak memory 240412 kb
Host smart-5aca9d89-85ef-4ef2-928d-9b5c5afa7bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3496918172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3496918172
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.865574015
Short name T183
Test name
Test status
Simulation time 52734237 ps
CPU time 4.31 seconds
Started Jul 11 04:47:12 PM PDT 24
Finished Jul 11 04:47:18 PM PDT 24
Peak memory 238000 kb
Host smart-254e494f-a7fe-4481-9de1-98a848133369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=865574015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.865574015
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.555434374
Short name T182
Test name
Test status
Simulation time 5171388277 ps
CPU time 83.83 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 240332 kb
Host smart-6696af46-cb8e-482a-bf29-729841a64647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=555434374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.555434374
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2074268715
Short name T173
Test name
Test status
Simulation time 65254639 ps
CPU time 2.04 seconds
Started Jul 11 04:47:05 PM PDT 24
Finished Jul 11 04:47:09 PM PDT 24
Peak memory 237880 kb
Host smart-be9b7a0b-6fc1-4a92-9808-1bba0310d117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2074268715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2074268715
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2235921970
Short name T189
Test name
Test status
Simulation time 338225113 ps
CPU time 24.31 seconds
Started Jul 11 04:47:34 PM PDT 24
Finished Jul 11 04:48:04 PM PDT 24
Peak memory 248536 kb
Host smart-0ccab5a9-8f4a-449a-bb8e-f3d95dc42545
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2235921970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2235921970
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2830565865
Short name T184
Test name
Test status
Simulation time 23325701 ps
CPU time 2.55 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237792 kb
Host smart-dcd912c3-4453-430e-8168-1fcfb9495eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2830565865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2830565865
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4202902783
Short name T178
Test name
Test status
Simulation time 57378160 ps
CPU time 2.15 seconds
Started Jul 11 04:47:11 PM PDT 24
Finished Jul 11 04:47:14 PM PDT 24
Peak memory 236600 kb
Host smart-ff38c6d5-fe45-4823-b6e4-249d40eb2425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4202902783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4202902783
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3963598766
Short name T172
Test name
Test status
Simulation time 55442139 ps
CPU time 2.03 seconds
Started Jul 11 04:46:57 PM PDT 24
Finished Jul 11 04:47:00 PM PDT 24
Peak memory 237976 kb
Host smart-9a60b9e3-dd0d-418c-b4bb-789d93193642
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3963598766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3963598766
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4171159352
Short name T180
Test name
Test status
Simulation time 567916334 ps
CPU time 36.05 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:49:20 PM PDT 24
Peak memory 235708 kb
Host smart-9141ad1f-3a65-4887-a41b-cf98682e699a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4171159352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4171159352
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3434468553
Short name T188
Test name
Test status
Simulation time 3322873802 ps
CPU time 49.91 seconds
Started Jul 11 04:47:01 PM PDT 24
Finished Jul 11 04:47:53 PM PDT 24
Peak memory 240540 kb
Host smart-66d8fa84-3ec5-46de-bd2a-6738575b70ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3434468553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3434468553
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.609716528
Short name T185
Test name
Test status
Simulation time 1842212835 ps
CPU time 38.5 seconds
Started Jul 11 04:47:20 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 237556 kb
Host smart-787645ca-38dc-4d03-a825-dec02f720980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=609716528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.609716528
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3383016566
Short name T358
Test name
Test status
Simulation time 41891783375 ps
CPU time 272.11 seconds
Started Jul 11 04:47:02 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 240512 kb
Host smart-3b62cf3a-5288-4db8-966f-580aee61bfd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3383016566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3383016566
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2485672707
Short name T774
Test name
Test status
Simulation time 23737392707 ps
CPU time 362.92 seconds
Started Jul 11 04:46:57 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 236660 kb
Host smart-a531a8dd-7f97-484c-88c0-036523846cb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2485672707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2485672707
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3073530563
Short name T730
Test name
Test status
Simulation time 102553959 ps
CPU time 4.93 seconds
Started Jul 11 04:46:55 PM PDT 24
Finished Jul 11 04:47:01 PM PDT 24
Peak memory 248688 kb
Host smart-056395b3-b019-487d-b259-b9536a739e33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3073530563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3073530563
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4032654530
Short name T757
Test name
Test status
Simulation time 216616932 ps
CPU time 5.01 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:47:07 PM PDT 24
Peak memory 239736 kb
Host smart-296448da-3ea2-455b-aef3-3b6a735c3c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032654530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4032654530
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2197945739
Short name T187
Test name
Test status
Simulation time 64438486 ps
CPU time 5.25 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:47:06 PM PDT 24
Peak memory 236568 kb
Host smart-99efb130-6cf6-4a39-9ee2-69aaee44fb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2197945739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2197945739
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2997018333
Short name T807
Test name
Test status
Simulation time 6860895 ps
CPU time 1.49 seconds
Started Jul 11 04:47:01 PM PDT 24
Finished Jul 11 04:47:04 PM PDT 24
Peak memory 236516 kb
Host smart-6df448c0-a817-476d-b948-986b097b4376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2997018333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2997018333
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.873907016
Short name T739
Test name
Test status
Simulation time 556378889 ps
CPU time 21.77 seconds
Started Jul 11 04:46:57 PM PDT 24
Finished Jul 11 04:47:20 PM PDT 24
Peak memory 245752 kb
Host smart-dec8a3dc-5ebe-41fa-b568-8745feef0adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=873907016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.873907016
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3246008802
Short name T158
Test name
Test status
Simulation time 51694211776 ps
CPU time 286.47 seconds
Started Jul 11 04:46:56 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 265396 kb
Host smart-67c14f09-86ae-47a7-aa1c-02c3b04188bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3246008802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3246008802
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2816390252
Short name T763
Test name
Test status
Simulation time 454553230 ps
CPU time 12.97 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:47:15 PM PDT 24
Peak memory 248628 kb
Host smart-99921220-67f5-4f8a-a67b-8f3a4fd60e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2816390252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2816390252
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1161858677
Short name T786
Test name
Test status
Simulation time 13590064416 ps
CPU time 126.55 seconds
Started Jul 11 04:47:01 PM PDT 24
Finished Jul 11 04:49:09 PM PDT 24
Peak memory 237584 kb
Host smart-1ddd9eee-c5c5-4b42-a73c-83d230850fc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1161858677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1161858677
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2688552744
Short name T747
Test name
Test status
Simulation time 1692169138 ps
CPU time 196.92 seconds
Started Jul 11 04:47:04 PM PDT 24
Finished Jul 11 04:50:21 PM PDT 24
Peak memory 237732 kb
Host smart-338c07d9-913b-4838-bca5-73ca3160d70c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2688552744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2688552744
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4055593582
Short name T249
Test name
Test status
Simulation time 139554084 ps
CPU time 6.45 seconds
Started Jul 11 04:47:02 PM PDT 24
Finished Jul 11 04:47:09 PM PDT 24
Peak memory 248584 kb
Host smart-3c56bba2-954b-49cb-aa51-1c1bab498ef3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4055593582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4055593582
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1195988709
Short name T356
Test name
Test status
Simulation time 107022660 ps
CPU time 4.57 seconds
Started Jul 11 04:47:00 PM PDT 24
Finished Jul 11 04:47:06 PM PDT 24
Peak memory 240440 kb
Host smart-51e4758a-51ca-45ae-a758-c29b93e84f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195988709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1195988709
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3354627195
Short name T773
Test name
Test status
Simulation time 115847611 ps
CPU time 5.45 seconds
Started Jul 11 04:46:58 PM PDT 24
Finished Jul 11 04:47:04 PM PDT 24
Peak memory 237512 kb
Host smart-8d5aeac1-008f-4fe7-b7d4-88cf0585b6e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3354627195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3354627195
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2773507854
Short name T352
Test name
Test status
Simulation time 20948452 ps
CPU time 1.4 seconds
Started Jul 11 04:47:03 PM PDT 24
Finished Jul 11 04:47:05 PM PDT 24
Peak memory 235840 kb
Host smart-991f3d40-0f26-4c0a-8dfb-8de8b06d7f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2773507854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2773507854
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2415545526
Short name T737
Test name
Test status
Simulation time 2257301795 ps
CPU time 43.16 seconds
Started Jul 11 04:47:02 PM PDT 24
Finished Jul 11 04:47:46 PM PDT 24
Peak memory 245696 kb
Host smart-32a72556-59dc-4d26-b3f6-e889df16c1d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2415545526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2415545526
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.541284050
Short name T135
Test name
Test status
Simulation time 2586887615 ps
CPU time 175.29 seconds
Started Jul 11 04:46:59 PM PDT 24
Finished Jul 11 04:49:56 PM PDT 24
Peak memory 272140 kb
Host smart-609b5670-d485-478c-a0a1-d3d092894f4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=541284050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.541284050
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.569652091
Short name T145
Test name
Test status
Simulation time 2219455901 ps
CPU time 337.98 seconds
Started Jul 11 04:46:55 PM PDT 24
Finished Jul 11 04:52:34 PM PDT 24
Peak memory 269476 kb
Host smart-84a9196c-f325-4698-947c-79c74c37405a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569652091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.569652091
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.36606830
Short name T804
Test name
Test status
Simulation time 195172451 ps
CPU time 12.78 seconds
Started Jul 11 04:46:59 PM PDT 24
Finished Jul 11 04:47:13 PM PDT 24
Peak memory 248696 kb
Host smart-3c546625-1995-4b5f-904d-157aeab5be3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=36606830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.36606830
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3749891897
Short name T813
Test name
Test status
Simulation time 135663753 ps
CPU time 5.48 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:31 PM PDT 24
Peak memory 240440 kb
Host smart-215e41a7-1962-4843-99bf-f261c8f0cdf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749891897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3749891897
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.566405998
Short name T777
Test name
Test status
Simulation time 49144504 ps
CPU time 4.89 seconds
Started Jul 11 04:47:25 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 240496 kb
Host smart-29f9ecec-0b22-4766-b736-81ef70f5e439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=566405998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.566405998
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2282151238
Short name T799
Test name
Test status
Simulation time 10161628 ps
CPU time 1.58 seconds
Started Jul 11 04:47:20 PM PDT 24
Finished Jul 11 04:47:26 PM PDT 24
Peak memory 237496 kb
Host smart-1e41ab57-4e7f-4c02-8d4b-e06698eaca26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2282151238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2282151238
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2089728460
Short name T745
Test name
Test status
Simulation time 363970071 ps
CPU time 13 seconds
Started Jul 11 04:47:30 PM PDT 24
Finished Jul 11 04:47:48 PM PDT 24
Peak memory 248696 kb
Host smart-af2a9745-b204-4137-b5ce-1fd4c9284363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2089728460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2089728460
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1387751781
Short name T138
Test name
Test status
Simulation time 8284436509 ps
CPU time 156.33 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 267668 kb
Host smart-91a5ca6e-2702-4c20-a0aa-741c1c186717
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1387751781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1387751781
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2742313778
Short name T137
Test name
Test status
Simulation time 2392406343 ps
CPU time 308.8 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:52:30 PM PDT 24
Peak memory 265360 kb
Host smart-5c4ce5ea-df8c-4f48-9656-9d2bc82a1ad9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742313778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2742313778
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2644345042
Short name T723
Test name
Test status
Simulation time 60661706 ps
CPU time 5.84 seconds
Started Jul 11 04:47:26 PM PDT 24
Finished Jul 11 04:47:35 PM PDT 24
Peak memory 248652 kb
Host smart-e7122bc9-b455-4939-b46e-c6a326c7ccb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2644345042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2644345042
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2151133875
Short name T190
Test name
Test status
Simulation time 133471959 ps
CPU time 2.32 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:24 PM PDT 24
Peak memory 238456 kb
Host smart-2d5f116e-21c2-402f-893e-8c626b12fb86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2151133875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2151133875
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3595026986
Short name T741
Test name
Test status
Simulation time 555469859 ps
CPU time 5.9 seconds
Started Jul 11 04:47:20 PM PDT 24
Finished Jul 11 04:47:30 PM PDT 24
Peak memory 238492 kb
Host smart-374599a4-5dba-4154-993c-dbb1d6deba64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595026986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3595026986
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.466386827
Short name T767
Test name
Test status
Simulation time 20540032 ps
CPU time 3.94 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:29 PM PDT 24
Peak memory 237516 kb
Host smart-932b4a7e-dc1f-432d-a2a0-99262f4836fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=466386827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.466386827
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2041594397
Short name T803
Test name
Test status
Simulation time 22375658 ps
CPU time 1.4 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:24 PM PDT 24
Peak memory 236508 kb
Host smart-ea29e934-6f27-4185-b4fe-a6925bdad08f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2041594397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2041594397
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1650511025
Short name T821
Test name
Test status
Simulation time 616226458 ps
CPU time 23.68 seconds
Started Jul 11 04:47:21 PM PDT 24
Finished Jul 11 04:47:48 PM PDT 24
Peak memory 245748 kb
Host smart-432be839-d88d-4e72-98bf-946c442852c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1650511025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1650511025
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.946067157
Short name T168
Test name
Test status
Simulation time 2046368260 ps
CPU time 126.83 seconds
Started Jul 11 04:47:25 PM PDT 24
Finished Jul 11 04:49:35 PM PDT 24
Peak memory 265320 kb
Host smart-df334325-fb57-4a90-9abd-29b13cc4bdb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=946067157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.946067157
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1854343989
Short name T762
Test name
Test status
Simulation time 981984577 ps
CPU time 11.09 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 248592 kb
Host smart-5bcfa0ef-0652-48d3-8edb-fb51565b2b65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1854343989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1854343989
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.791681075
Short name T280
Test name
Test status
Simulation time 21244627 ps
CPU time 2.59 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:29 PM PDT 24
Peak memory 238448 kb
Host smart-5c6ea0c6-15b8-45d0-952d-88610aba1f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=791681075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.791681075
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3487867016
Short name T798
Test name
Test status
Simulation time 79574923 ps
CPU time 8.06 seconds
Started Jul 11 04:47:24 PM PDT 24
Finished Jul 11 04:47:36 PM PDT 24
Peak memory 240844 kb
Host smart-51edee72-0e71-4cf0-8d4b-9efe4f93ed26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487867016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3487867016
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2613804087
Short name T806
Test name
Test status
Simulation time 62329630 ps
CPU time 5.2 seconds
Started Jul 11 04:47:23 PM PDT 24
Finished Jul 11 04:47:32 PM PDT 24
Peak memory 240392 kb
Host smart-2f3ccfb3-b850-49e7-b2c3-9eaea8fb3b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2613804087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2613804087
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2421021782
Short name T783
Test name
Test status
Simulation time 27076941 ps
CPU time 1.37 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:27 PM PDT 24
Peak memory 237452 kb
Host smart-69ad5856-a9ad-42d1-99ac-0798d80f3be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2421021782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2421021782
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.186182063
Short name T814
Test name
Test status
Simulation time 330774961 ps
CPU time 20.21 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:48:01 PM PDT 24
Peak memory 244596 kb
Host smart-0d259fcf-9360-4a7a-a41c-ecd6e3b2dd20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=186182063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.186182063
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.406221413
Short name T255
Test name
Test status
Simulation time 48784608 ps
CPU time 4.7 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:31 PM PDT 24
Peak memory 248456 kb
Host smart-a91469c8-61c6-45e6-8b5d-ec68dba1aab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=406221413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.406221413
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.14685807
Short name T776
Test name
Test status
Simulation time 1762542667 ps
CPU time 35.73 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:48:01 PM PDT 24
Peak memory 237620 kb
Host smart-f92e12f5-7bbf-44d1-aea5-080da2ad4c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=14685807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.14685807
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1095712059
Short name T250
Test name
Test status
Simulation time 442908345 ps
CPU time 8.55 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:35 PM PDT 24
Peak memory 240440 kb
Host smart-4b469700-c141-47b4-90a4-d6732e03fe24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095712059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1095712059
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2885154496
Short name T248
Test name
Test status
Simulation time 94737172 ps
CPU time 5.35 seconds
Started Jul 11 04:47:25 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 240432 kb
Host smart-ca6d4400-3680-471f-8b4a-3cacde354404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2885154496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2885154496
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3004756100
Short name T717
Test name
Test status
Simulation time 24641852 ps
CPU time 1.2 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:38 PM PDT 24
Peak memory 237460 kb
Host smart-7dcb6264-6107-4892-a251-abb642f04944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3004756100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3004756100
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2844919158
Short name T775
Test name
Test status
Simulation time 85216282 ps
CPU time 12.31 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:47:53 PM PDT 24
Peak memory 240492 kb
Host smart-e315b010-dba0-4a24-b377-36ad953b8659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2844919158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2844919158
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1803437341
Short name T808
Test name
Test status
Simulation time 140571614 ps
CPU time 10.87 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:50 PM PDT 24
Peak memory 249780 kb
Host smart-88e0110b-284f-4238-92ea-b00db5b67f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1803437341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1803437341
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1609362407
Short name T254
Test name
Test status
Simulation time 277975611 ps
CPU time 5.24 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:39 PM PDT 24
Peak memory 238400 kb
Host smart-a31748e2-1b07-49b5-af95-1af527014e67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609362407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1609362407
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4195664044
Short name T811
Test name
Test status
Simulation time 34798354 ps
CPU time 5.38 seconds
Started Jul 11 04:47:24 PM PDT 24
Finished Jul 11 04:47:33 PM PDT 24
Peak memory 237508 kb
Host smart-0e22d7e4-9311-41e1-a65a-42dcac1ad92e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4195664044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4195664044
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3811726081
Short name T709
Test name
Test status
Simulation time 6501650 ps
CPU time 1.45 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 235468 kb
Host smart-bf2e2cd3-65d0-4c67-89bb-4968be6ac0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3811726081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3811726081
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.521547478
Short name T171
Test name
Test status
Simulation time 13314106686 ps
CPU time 871.01 seconds
Started Jul 11 04:47:26 PM PDT 24
Finished Jul 11 05:02:01 PM PDT 24
Peak memory 265232 kb
Host smart-1efd444a-355c-4e81-b09d-8eac6ee43543
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521547478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.521547478
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1544290302
Short name T817
Test name
Test status
Simulation time 291168875 ps
CPU time 19.63 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:51 PM PDT 24
Peak memory 248644 kb
Host smart-8f112761-d525-4620-ac3e-d83cc59f20c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1544290302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1544290302
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.138484503
Short name T359
Test name
Test status
Simulation time 232927671 ps
CPU time 8.4 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 253380 kb
Host smart-46dae987-4121-4c5b-b399-e9c05791c4ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138484503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.138484503
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3469494480
Short name T779
Test name
Test status
Simulation time 594322979 ps
CPU time 10.19 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:49 PM PDT 24
Peak memory 237388 kb
Host smart-a7c30315-c2a1-4920-b5db-4ae2889219f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3469494480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3469494480
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.898653106
Short name T721
Test name
Test status
Simulation time 15647145 ps
CPU time 1.43 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237400 kb
Host smart-79cb3266-70a1-45ea-b116-fdd02345cf3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=898653106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.898653106
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1120084806
Short name T193
Test name
Test status
Simulation time 362309813 ps
CPU time 12.76 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:45 PM PDT 24
Peak memory 245632 kb
Host smart-004e171f-2e13-4ed2-b36f-f89058572e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1120084806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1120084806
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3379078320
Short name T160
Test name
Test status
Simulation time 17328360194 ps
CPU time 130.1 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:50:54 PM PDT 24
Peak memory 263188 kb
Host smart-b39cd43a-6076-4d28-8299-4cab78fe9825
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379078320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3379078320
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3089214100
Short name T150
Test name
Test status
Simulation time 7797000516 ps
CPU time 548.42 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 269772 kb
Host smart-1ef17dca-9fff-479f-ada3-0323d58d3046
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089214100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3089214100
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2000154238
Short name T801
Test name
Test status
Simulation time 144821572 ps
CPU time 4.91 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:47:46 PM PDT 24
Peak memory 247828 kb
Host smart-e321693d-7542-4e70-ba17-fef194977f77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000154238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2000154238
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.702196162
Short name T812
Test name
Test status
Simulation time 1934522755 ps
CPU time 34.15 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 240260 kb
Host smart-1374abc0-8775-4492-a27d-bae745f1973a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=702196162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.702196162
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2014559746
Short name T805
Test name
Test status
Simulation time 265184954 ps
CPU time 10.68 seconds
Started Jul 11 04:47:30 PM PDT 24
Finished Jul 11 04:47:45 PM PDT 24
Peak memory 255124 kb
Host smart-9a1cd8c0-8f18-4780-9869-e2dad6b4f66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014559746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2014559746
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3004688642
Short name T192
Test name
Test status
Simulation time 256032691 ps
CPU time 5.48 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:47:47 PM PDT 24
Peak memory 237336 kb
Host smart-27607804-5c9e-46c1-a883-bb9f06e5e852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3004688642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3004688642
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3170181745
Short name T755
Test name
Test status
Simulation time 7247761 ps
CPU time 1.51 seconds
Started Jul 11 04:47:25 PM PDT 24
Finished Jul 11 04:47:30 PM PDT 24
Peak memory 237556 kb
Host smart-4b4de790-a3fa-48a6-85b1-c7ddf1a97271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3170181745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3170181745
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2754550059
Short name T194
Test name
Test status
Simulation time 500809592 ps
CPU time 35.7 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:48:13 PM PDT 24
Peak memory 245652 kb
Host smart-262d162d-1b7a-4626-bf84-35dc1ee7fd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754550059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2754550059
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.649607725
Short name T146
Test name
Test status
Simulation time 54757133738 ps
CPU time 1039.5 seconds
Started Jul 11 04:47:23 PM PDT 24
Finished Jul 11 05:04:47 PM PDT 24
Peak memory 265368 kb
Host smart-2c52c5c8-db38-4fbb-99b9-f9ba23dae573
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649607725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.649607725
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4291795521
Short name T788
Test name
Test status
Simulation time 105315033 ps
CPU time 14.65 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:47 PM PDT 24
Peak memory 248200 kb
Host smart-7f17888e-c9fa-41dc-9d48-c53bbcc92bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4291795521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4291795521
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.982091303
Short name T744
Test name
Test status
Simulation time 251747087 ps
CPU time 5.22 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:42 PM PDT 24
Peak memory 239504 kb
Host smart-0f85461b-e212-4d79-adba-35abcbbce7e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982091303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.982091303
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3738461242
Short name T253
Test name
Test status
Simulation time 75511350 ps
CPU time 5.58 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:42 PM PDT 24
Peak memory 240336 kb
Host smart-5767eec2-c8fc-4bb3-8e53-41133ac15f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3738461242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3738461242
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2658035495
Short name T348
Test name
Test status
Simulation time 8706778 ps
CPU time 1.52 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237424 kb
Host smart-cae4e426-911d-4b60-820a-a0fdfaccc1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2658035495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2658035495
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1589752430
Short name T802
Test name
Test status
Simulation time 511887654 ps
CPU time 38.56 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:48:12 PM PDT 24
Peak memory 245748 kb
Host smart-9e1e1e9a-cfc1-42bb-a8bc-7829f296758b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1589752430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1589752430
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3193940603
Short name T154
Test name
Test status
Simulation time 869199309 ps
CPU time 97.29 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:49:03 PM PDT 24
Peak memory 256332 kb
Host smart-cb3ab4b3-d2f6-4cc3-ac15-348f32d977a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193940603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3193940603
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2581996789
Short name T765
Test name
Test status
Simulation time 59366394 ps
CPU time 5.83 seconds
Started Jul 11 04:47:34 PM PDT 24
Finished Jul 11 04:47:46 PM PDT 24
Peak memory 248604 kb
Host smart-34313cbe-96fa-488c-ace6-b99ed8259573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2581996789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2581996789
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1006704973
Short name T820
Test name
Test status
Simulation time 2459661189 ps
CPU time 33.02 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:48:05 PM PDT 24
Peak memory 237692 kb
Host smart-b87a54c0-823e-41f4-bfc3-0b52c2e7ee29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1006704973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1006704973
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2062667877
Short name T728
Test name
Test status
Simulation time 65974000 ps
CPU time 4.93 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:38 PM PDT 24
Peak memory 240552 kb
Host smart-83be604c-7555-43ee-a363-0e232883cdc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062667877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2062667877
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2461348421
Short name T764
Test name
Test status
Simulation time 36207704 ps
CPU time 2.99 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 239344 kb
Host smart-b3668519-83d8-474d-a279-7cda2176bed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2461348421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2461348421
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3665043998
Short name T725
Test name
Test status
Simulation time 16489628 ps
CPU time 1.32 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:39 PM PDT 24
Peak memory 237460 kb
Host smart-13764919-c289-4574-ad9d-eb84dfafa6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3665043998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3665043998
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1546839856
Short name T195
Test name
Test status
Simulation time 359439289 ps
CPU time 28.62 seconds
Started Jul 11 04:47:26 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 245624 kb
Host smart-5f9bb5df-1399-4d12-bbc8-4e6bd9a1345a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1546839856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1546839856
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1405775754
Short name T768
Test name
Test status
Simulation time 458110994 ps
CPU time 9.42 seconds
Started Jul 11 04:47:36 PM PDT 24
Finished Jul 11 04:47:51 PM PDT 24
Peak memory 252640 kb
Host smart-6d2a045e-acdb-4990-94dc-494ab634d44d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1405775754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1405775754
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3709134371
Short name T251
Test name
Test status
Simulation time 502828181 ps
CPU time 5.98 seconds
Started Jul 11 04:47:30 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 239488 kb
Host smart-22897b77-597b-45b1-b1e8-762a18cf4987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709134371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3709134371
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.644107003
Short name T819
Test name
Test status
Simulation time 422512121 ps
CPU time 5.39 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:42 PM PDT 24
Peak memory 240468 kb
Host smart-3f37b9c1-f820-4b68-a740-71be52287214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=644107003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.644107003
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.701817716
Short name T711
Test name
Test status
Simulation time 12355716 ps
CPU time 1.28 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:35 PM PDT 24
Peak memory 237556 kb
Host smart-4a39b245-4f9a-4169-8d9d-1061b2b4d696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701817716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.701817716
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1431760519
Short name T186
Test name
Test status
Simulation time 1924261500 ps
CPU time 26.83 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:48:05 PM PDT 24
Peak memory 245928 kb
Host smart-78ec1f4b-d06a-4caa-99d2-100166dfdedb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1431760519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1431760519
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1326223997
Short name T133
Test name
Test status
Simulation time 12370832676 ps
CPU time 422.03 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 268688 kb
Host smart-93f8671a-4046-44d4-a29c-13fdad50669c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326223997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1326223997
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2815549480
Short name T714
Test name
Test status
Simulation time 139200799 ps
CPU time 6.57 seconds
Started Jul 11 04:47:27 PM PDT 24
Finished Jul 11 04:47:37 PM PDT 24
Peak memory 248728 kb
Host smart-ebf8f55a-644b-4d6d-99a8-236229dad120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2815549480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2815549480
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3373289833
Short name T785
Test name
Test status
Simulation time 1079128882 ps
CPU time 33.53 seconds
Started Jul 11 04:48:05 PM PDT 24
Finished Jul 11 04:48:42 PM PDT 24
Peak memory 245712 kb
Host smart-f596f97e-7209-4872-a4d7-8a5ddc51246e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3373289833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3373289833
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1459527036
Short name T361
Test name
Test status
Simulation time 14024298063 ps
CPU time 242.21 seconds
Started Jul 11 04:47:10 PM PDT 24
Finished Jul 11 04:51:13 PM PDT 24
Peak memory 241304 kb
Host smart-93d8c848-1168-45ba-9ed7-364f4133870d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1459527036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1459527036
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4092237762
Short name T792
Test name
Test status
Simulation time 6080130567 ps
CPU time 183.17 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:50:25 PM PDT 24
Peak memory 237448 kb
Host smart-88a1cc7d-d38a-44e4-93ea-38d86232e5e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4092237762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4092237762
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2677177436
Short name T716
Test name
Test status
Simulation time 26659627 ps
CPU time 3.97 seconds
Started Jul 11 04:47:02 PM PDT 24
Finished Jul 11 04:47:07 PM PDT 24
Peak memory 240500 kb
Host smart-f0dcddcb-3cf4-43cc-8f07-2d9203669596
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2677177436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2677177436
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.644926003
Short name T778
Test name
Test status
Simulation time 365571015 ps
CPU time 8.27 seconds
Started Jul 11 04:47:09 PM PDT 24
Finished Jul 11 04:47:18 PM PDT 24
Peak memory 238512 kb
Host smart-08dc7832-eb49-4269-933d-efc2826b9fc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644926003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.644926003
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4284923446
Short name T794
Test name
Test status
Simulation time 6175284 ps
CPU time 1.47 seconds
Started Jul 11 04:47:04 PM PDT 24
Finished Jul 11 04:47:08 PM PDT 24
Peak memory 235516 kb
Host smart-9c49c9cd-4a83-4648-8255-6a28de4e72e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4284923446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4284923446
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3826608580
Short name T784
Test name
Test status
Simulation time 657811076 ps
CPU time 11.83 seconds
Started Jul 11 04:47:05 PM PDT 24
Finished Jul 11 04:47:18 PM PDT 24
Peak memory 244796 kb
Host smart-37f002b3-09f4-4a95-89d0-34d6d4bdbb8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3826608580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3826608580
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.97993613
Short name T156
Test name
Test status
Simulation time 42763511303 ps
CPU time 288.61 seconds
Started Jul 11 04:47:08 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 265336 kb
Host smart-8b9b5b14-57eb-4c70-bb69-85306d0e4ca6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97993613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.97993613
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3972166117
Short name T769
Test name
Test status
Simulation time 241862016 ps
CPU time 7.24 seconds
Started Jul 11 04:47:07 PM PDT 24
Finished Jul 11 04:47:16 PM PDT 24
Peak memory 247912 kb
Host smart-01b650c9-417e-4821-9d2f-2d7c25f19ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3972166117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3972166117
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2395793622
Short name T818
Test name
Test status
Simulation time 9445361 ps
CPU time 1.29 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 237548 kb
Host smart-10d0d1d0-ef3b-46d2-9438-e304e64ee4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2395793622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2395793622
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.62560820
Short name T349
Test name
Test status
Simulation time 7606781 ps
CPU time 1.39 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 235588 kb
Host smart-abd4a57e-baae-4d08-9916-73c5253a6c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=62560820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.62560820
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.331618237
Short name T734
Test name
Test status
Simulation time 7786419 ps
CPU time 1.43 seconds
Started Jul 11 04:47:28 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 236600 kb
Host smart-2feeea05-5155-44b8-98a0-f21d084ad9a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331618237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.331618237
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.481871691
Short name T177
Test name
Test status
Simulation time 10521546 ps
CPU time 1.61 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:35 PM PDT 24
Peak memory 237456 kb
Host smart-5b7872ab-f8c2-416f-b70d-64ec9f553edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481871691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.481871691
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1625408558
Short name T729
Test name
Test status
Simulation time 19581535 ps
CPU time 1.48 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:38 PM PDT 24
Peak memory 237364 kb
Host smart-a1a051f9-7cc7-4424-ab0d-72327c2d473d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1625408558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1625408558
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2434035720
Short name T789
Test name
Test status
Simulation time 9175532 ps
CPU time 1.57 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237556 kb
Host smart-29ca5a47-9110-4eac-9eb8-2659c6bfebd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2434035720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2434035720
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2294475411
Short name T790
Test name
Test status
Simulation time 12293077 ps
CPU time 1.37 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:35 PM PDT 24
Peak memory 237496 kb
Host smart-2ecca99f-1f89-448f-bed3-a4467b64604c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2294475411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2294475411
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1850364570
Short name T795
Test name
Test status
Simulation time 9374006 ps
CPU time 1.34 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237556 kb
Host smart-ddc9622c-72a5-4dcf-88dc-7e03c8c58a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1850364570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1850364570
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.635137583
Short name T710
Test name
Test status
Simulation time 6303904 ps
CPU time 1.46 seconds
Started Jul 11 04:47:36 PM PDT 24
Finished Jul 11 04:47:44 PM PDT 24
Peak memory 235524 kb
Host smart-13a46393-a231-477f-bb54-947fc586ebc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=635137583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.635137583
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3601736618
Short name T758
Test name
Test status
Simulation time 2124589060 ps
CPU time 152.75 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 240252 kb
Host smart-d25a6543-2bd0-4ceb-8d5c-4b391c711d47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3601736618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3601736618
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2197918415
Short name T727
Test name
Test status
Simulation time 821054608 ps
CPU time 97.53 seconds
Started Jul 11 04:47:17 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 240500 kb
Host smart-4ada9130-6c02-4924-a14f-8cbee5933fa4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2197918415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2197918415
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3713488726
Short name T733
Test name
Test status
Simulation time 199854501 ps
CPU time 9.14 seconds
Started Jul 11 04:47:06 PM PDT 24
Finished Jul 11 04:47:17 PM PDT 24
Peak memory 248968 kb
Host smart-f8ab7d00-fd62-43e8-94ab-1ffa8d2e7c20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3713488726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3713488726
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.73525701
Short name T787
Test name
Test status
Simulation time 92889386 ps
CPU time 4.87 seconds
Started Jul 11 04:47:09 PM PDT 24
Finished Jul 11 04:47:15 PM PDT 24
Peak memory 240428 kb
Host smart-a5b57bd0-0218-4c36-8800-b08c207cf02a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73525701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.alert_handler_csr_mem_rw_with_rand_reset.73525701
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1344944269
Short name T362
Test name
Test status
Simulation time 250559924 ps
CPU time 9.32 seconds
Started Jul 11 04:47:08 PM PDT 24
Finished Jul 11 04:47:18 PM PDT 24
Peak memory 237436 kb
Host smart-324ab58f-6159-402e-9264-26a2997c4a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1344944269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1344944269
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.4086953807
Short name T782
Test name
Test status
Simulation time 11915382 ps
CPU time 1.42 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:22 PM PDT 24
Peak memory 237556 kb
Host smart-50d96d7b-da69-4d20-82b6-f8149f457fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4086953807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.4086953807
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1952055345
Short name T753
Test name
Test status
Simulation time 1775991176 ps
CPU time 18.42 seconds
Started Jul 11 04:47:04 PM PDT 24
Finished Jul 11 04:47:25 PM PDT 24
Peak memory 245696 kb
Host smart-ad5339a9-fe9a-4318-ba51-efe37cd0c65d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1952055345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1952055345
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4261955352
Short name T139
Test name
Test status
Simulation time 4666744977 ps
CPU time 280.5 seconds
Started Jul 11 04:47:15 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 266344 kb
Host smart-55955eff-bedb-4a19-a1cd-f9c55531d168
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4261955352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4261955352
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1207313009
Short name T159
Test name
Test status
Simulation time 23923054409 ps
CPU time 897.06 seconds
Started Jul 11 04:47:05 PM PDT 24
Finished Jul 11 05:02:04 PM PDT 24
Peak memory 265464 kb
Host smart-3af321ef-8534-400e-8722-4d9d06f0ae55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207313009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1207313009
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2577883281
Short name T707
Test name
Test status
Simulation time 3827650258 ps
CPU time 19.22 seconds
Started Jul 11 04:47:17 PM PDT 24
Finished Jul 11 04:47:39 PM PDT 24
Peak memory 254776 kb
Host smart-f760911d-4e1c-473e-93d6-e1531af4c56d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2577883281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2577883281
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.759187196
Short name T800
Test name
Test status
Simulation time 16819409 ps
CPU time 1.48 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:36 PM PDT 24
Peak memory 236564 kb
Host smart-5c7e3269-bba0-458d-b877-b14a4c619fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=759187196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.759187196
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2147770976
Short name T176
Test name
Test status
Simulation time 8158690 ps
CPU time 1.5 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:47:43 PM PDT 24
Peak memory 236612 kb
Host smart-984bac94-26d3-4ebf-a146-9b3f8ae94397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2147770976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2147770976
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3107254365
Short name T752
Test name
Test status
Simulation time 8995998 ps
CPU time 1.52 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:41 PM PDT 24
Peak memory 236508 kb
Host smart-74b9d831-e8c2-4781-b0e5-4f2aab806242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3107254365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3107254365
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.272097821
Short name T749
Test name
Test status
Simulation time 6603038 ps
CPU time 1.4 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237536 kb
Host smart-9ae5e3a3-465b-436e-984f-eff1f2718bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=272097821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.272097821
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3423958043
Short name T712
Test name
Test status
Simulation time 23871346 ps
CPU time 1.51 seconds
Started Jul 11 04:47:36 PM PDT 24
Finished Jul 11 04:47:44 PM PDT 24
Peak memory 236684 kb
Host smart-da6d783a-f642-4508-8b60-1968cbb9dfa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3423958043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3423958043
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.215802542
Short name T742
Test name
Test status
Simulation time 12380597 ps
CPU time 1.51 seconds
Started Jul 11 04:47:35 PM PDT 24
Finished Jul 11 04:47:43 PM PDT 24
Peak memory 237456 kb
Host smart-8d995647-ee60-4b3f-867b-3b092de61606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=215802542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.215802542
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4160154603
Short name T748
Test name
Test status
Simulation time 6519470 ps
CPU time 1.43 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:41 PM PDT 24
Peak memory 237412 kb
Host smart-d00aa019-e5b6-4899-971f-0b12403a9beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4160154603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4160154603
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.928671914
Short name T743
Test name
Test status
Simulation time 30199957 ps
CPU time 1.39 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 236488 kb
Host smart-35685af1-057f-4f54-987d-8bde302d1b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928671914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.928671914
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2566484427
Short name T736
Test name
Test status
Simulation time 12171451 ps
CPU time 1.69 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 237548 kb
Host smart-a2103758-5025-492b-84cb-26db5301aeeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2566484427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2566484427
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1951752619
Short name T810
Test name
Test status
Simulation time 1629142145 ps
CPU time 126.43 seconds
Started Jul 11 04:47:11 PM PDT 24
Finished Jul 11 04:49:18 PM PDT 24
Peak memory 240680 kb
Host smart-1f530cbd-8a67-4010-90a1-083b119cca20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1951752619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1951752619
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1378247296
Short name T360
Test name
Test status
Simulation time 823344965 ps
CPU time 109.66 seconds
Started Jul 11 04:47:09 PM PDT 24
Finished Jul 11 04:49:00 PM PDT 24
Peak memory 237544 kb
Host smart-4b3a6c6f-6788-48a1-ab1f-d8a444e132d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1378247296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1378247296
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.926097830
Short name T732
Test name
Test status
Simulation time 129211664 ps
CPU time 3.98 seconds
Started Jul 11 04:47:17 PM PDT 24
Finished Jul 11 04:47:24 PM PDT 24
Peak memory 248680 kb
Host smart-d7dcd765-17f8-4c45-86e5-4d39708a995e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=926097830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.926097830
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3360140279
Short name T770
Test name
Test status
Simulation time 63820502 ps
CPU time 5.55 seconds
Started Jul 11 04:47:11 PM PDT 24
Finished Jul 11 04:47:17 PM PDT 24
Peak memory 253948 kb
Host smart-d2dec682-ceb4-4b53-9ca6-3d9f9f530375
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360140279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3360140279
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1605138950
Short name T252
Test name
Test status
Simulation time 237106019 ps
CPU time 5.59 seconds
Started Jul 11 04:47:12 PM PDT 24
Finished Jul 11 04:47:19 PM PDT 24
Peak memory 236592 kb
Host smart-0fc108a1-7560-474b-97f8-43e53ce9ea05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1605138950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1605138950
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3356249562
Short name T708
Test name
Test status
Simulation time 19708234 ps
CPU time 1.37 seconds
Started Jul 11 04:47:16 PM PDT 24
Finished Jul 11 04:47:19 PM PDT 24
Peak memory 235472 kb
Host smart-5d0042f6-d685-4436-8bac-4f81dcf17221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3356249562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3356249562
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2931556931
Short name T726
Test name
Test status
Simulation time 608340537 ps
CPU time 43.14 seconds
Started Jul 11 04:47:13 PM PDT 24
Finished Jul 11 04:47:57 PM PDT 24
Peak memory 248612 kb
Host smart-d2f8f6c6-bff1-48d7-9575-030ff8631724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2931556931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2931556931
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3041944596
Short name T164
Test name
Test status
Simulation time 3906631064 ps
CPU time 129.8 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:49:32 PM PDT 24
Peak memory 265364 kb
Host smart-a94c92ea-8928-42d2-952d-4decf753488f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3041944596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3041944596
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.492888871
Short name T722
Test name
Test status
Simulation time 1822433823 ps
CPU time 18.78 seconds
Started Jul 11 04:47:11 PM PDT 24
Finished Jul 11 04:47:31 PM PDT 24
Peak memory 248760 kb
Host smart-6d88eafc-6f08-46ba-8f70-ed8952148e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=492888871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.492888871
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1748731445
Short name T759
Test name
Test status
Simulation time 59112899 ps
CPU time 3.79 seconds
Started Jul 11 04:47:11 PM PDT 24
Finished Jul 11 04:47:15 PM PDT 24
Peak memory 237428 kb
Host smart-665ca984-2478-42f6-9be2-22deb3097c31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1748731445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1748731445
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2704787288
Short name T756
Test name
Test status
Simulation time 6901172 ps
CPU time 1.55 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 04:47:53 PM PDT 24
Peak memory 237464 kb
Host smart-ccb2b32f-d893-46ce-a8f5-6a4e344b92c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2704787288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2704787288
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2531296358
Short name T175
Test name
Test status
Simulation time 12580692 ps
CPU time 1.77 seconds
Started Jul 11 04:47:37 PM PDT 24
Finished Jul 11 04:47:45 PM PDT 24
Peak memory 236612 kb
Host smart-fc55686e-7142-4a87-8f64-86eaab3afda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2531296358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2531296358
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1275689802
Short name T760
Test name
Test status
Simulation time 10664073 ps
CPU time 1.55 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:38 PM PDT 24
Peak memory 237460 kb
Host smart-acc8299c-312e-4048-8187-dd98388022d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1275689802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1275689802
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1209166117
Short name T797
Test name
Test status
Simulation time 19117415 ps
CPU time 1.44 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:46 PM PDT 24
Peak memory 237528 kb
Host smart-f4902362-855d-4304-ba0a-eed59b30e8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1209166117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1209166117
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2165288883
Short name T724
Test name
Test status
Simulation time 46044883 ps
CPU time 1.44 seconds
Started Jul 11 04:47:34 PM PDT 24
Finished Jul 11 04:47:42 PM PDT 24
Peak memory 237316 kb
Host smart-a94c84a7-4a41-4108-8cf0-2a31f8932fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2165288883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2165288883
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1561834600
Short name T793
Test name
Test status
Simulation time 31471998 ps
CPU time 1.44 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:40 PM PDT 24
Peak memory 236620 kb
Host smart-c110f2e7-f717-4374-a701-c5271d2caa76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561834600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1561834600
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.943325932
Short name T815
Test name
Test status
Simulation time 14320822 ps
CPU time 1.34 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:39 PM PDT 24
Peak memory 236496 kb
Host smart-d0a65233-1fc3-4f86-b348-1fcb8b210631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=943325932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.943325932
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2943213550
Short name T720
Test name
Test status
Simulation time 10813782 ps
CPU time 1.37 seconds
Started Jul 11 04:47:31 PM PDT 24
Finished Jul 11 04:47:38 PM PDT 24
Peak memory 237388 kb
Host smart-dbfa5021-e601-403b-ba0c-e1f73487a420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2943213550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2943213550
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.174758709
Short name T771
Test name
Test status
Simulation time 8342710 ps
CPU time 1.53 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:41 PM PDT 24
Peak memory 236508 kb
Host smart-4713de56-cf56-40f2-a9f6-283afe1ffb29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=174758709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.174758709
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.790070604
Short name T735
Test name
Test status
Simulation time 18548117 ps
CPU time 1.85 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:41 PM PDT 24
Peak memory 236616 kb
Host smart-934495bf-cac0-4537-b3d6-f8cece64450e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=790070604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.790070604
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3874326094
Short name T731
Test name
Test status
Simulation time 159136115 ps
CPU time 5.02 seconds
Started Jul 11 04:47:13 PM PDT 24
Finished Jul 11 04:47:20 PM PDT 24
Peak memory 242176 kb
Host smart-d2276af8-818e-4a84-9480-17078874318e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874326094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3874326094
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2966600407
Short name T754
Test name
Test status
Simulation time 60365710 ps
CPU time 5.28 seconds
Started Jul 11 04:47:09 PM PDT 24
Finished Jul 11 04:47:16 PM PDT 24
Peak memory 236556 kb
Host smart-fc6b1971-6974-4523-aa59-990599840e99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2966600407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2966600407
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3947781775
Short name T354
Test name
Test status
Simulation time 8878584 ps
CPU time 1.39 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:47:25 PM PDT 24
Peak memory 237424 kb
Host smart-67679fec-4cba-44ff-8018-80c4e37890dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3947781775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3947781775
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2503430959
Short name T809
Test name
Test status
Simulation time 174012818 ps
CPU time 12.39 seconds
Started Jul 11 04:47:11 PM PDT 24
Finished Jul 11 04:47:25 PM PDT 24
Peak memory 244696 kb
Host smart-4cb3d95e-43aa-4e10-bbd1-40f6d1b9068b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2503430959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2503430959
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.972861937
Short name T141
Test name
Test status
Simulation time 3436267952 ps
CPU time 105.38 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:49:08 PM PDT 24
Peak memory 266816 kb
Host smart-bfa49e45-2cc3-4956-aeef-0bc1dfc0981c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=972861937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.972861937
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.706708118
Short name T157
Test name
Test status
Simulation time 11838935850 ps
CPU time 407.3 seconds
Started Jul 11 04:47:12 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 265280 kb
Host smart-0cbb2ce5-6e01-4664-8dc1-c3801f69e22d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706708118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.706708118
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.199003218
Short name T718
Test name
Test status
Simulation time 903497712 ps
CPU time 15.13 seconds
Started Jul 11 04:47:10 PM PDT 24
Finished Jul 11 04:47:26 PM PDT 24
Peak memory 252628 kb
Host smart-96d874c8-718f-4b6a-9363-3ac2445e55a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199003218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.199003218
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.936508908
Short name T738
Test name
Test status
Simulation time 133703150 ps
CPU time 5.47 seconds
Started Jul 11 04:47:21 PM PDT 24
Finished Jul 11 04:47:30 PM PDT 24
Peak memory 242528 kb
Host smart-57430135-8470-4943-b019-e6d26a550f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936508908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.936508908
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2533435234
Short name T761
Test name
Test status
Simulation time 101109966 ps
CPU time 3.21 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:47:27 PM PDT 24
Peak memory 236448 kb
Host smart-e0a240e2-869a-46bc-b5ac-3c46c3ba2207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2533435234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2533435234
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2070187118
Short name T353
Test name
Test status
Simulation time 6730356 ps
CPU time 1.44 seconds
Started Jul 11 04:47:17 PM PDT 24
Finished Jul 11 04:47:20 PM PDT 24
Peak memory 236600 kb
Host smart-f1ca77d0-430e-47a8-a7e4-b6a76bc2d4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2070187118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2070187118
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2963513795
Short name T796
Test name
Test status
Simulation time 625045162 ps
CPU time 12.45 seconds
Started Jul 11 04:47:14 PM PDT 24
Finished Jul 11 04:47:28 PM PDT 24
Peak memory 245756 kb
Host smart-e481da3e-410c-44d4-b26f-54c75b9bec0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963513795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2963513795
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3455730171
Short name T152
Test name
Test status
Simulation time 1826467088 ps
CPU time 107.1 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:49:10 PM PDT 24
Peak memory 265292 kb
Host smart-bcbd8c64-c6ce-4358-a7bc-9d0b3a8f8b43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3455730171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3455730171
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2270074593
Short name T715
Test name
Test status
Simulation time 32348245 ps
CPU time 4.38 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:27 PM PDT 24
Peak memory 249780 kb
Host smart-1aec5b37-48f2-41ba-85ab-3459d2307239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2270074593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2270074593
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.876489033
Short name T357
Test name
Test status
Simulation time 427230176 ps
CPU time 5.56 seconds
Started Jul 11 04:47:17 PM PDT 24
Finished Jul 11 04:47:25 PM PDT 24
Peak memory 256484 kb
Host smart-ad789d89-72d5-403a-9836-3190d1992113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876489033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.876489033
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4221230946
Short name T772
Test name
Test status
Simulation time 261787405 ps
CPU time 9.36 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:31 PM PDT 24
Peak memory 240492 kb
Host smart-1f57d90a-40c5-46b3-beb1-1522058c27eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4221230946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4221230946
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3759206141
Short name T780
Test name
Test status
Simulation time 9861546 ps
CPU time 1.58 seconds
Started Jul 11 04:47:17 PM PDT 24
Finished Jul 11 04:47:21 PM PDT 24
Peak memory 236636 kb
Host smart-324bf046-ce50-4061-b125-6cf8bcf7154d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3759206141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3759206141
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1742272138
Short name T781
Test name
Test status
Simulation time 91167449 ps
CPU time 10.58 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 04:47:44 PM PDT 24
Peak memory 244708 kb
Host smart-ff98ad8f-a65d-47e7-b974-95648ae397e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1742272138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1742272138
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2496043387
Short name T161
Test name
Test status
Simulation time 7780948963 ps
CPU time 545.36 seconds
Started Jul 11 04:47:16 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 270024 kb
Host smart-cdc58432-35a3-4b25-9fcd-9f2a49f0f176
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496043387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2496043387
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1358588819
Short name T706
Test name
Test status
Simulation time 436611697 ps
CPU time 9.23 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:31 PM PDT 24
Peak memory 254172 kb
Host smart-ec8ab537-0cc2-43a4-87af-a02d006c3df9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1358588819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1358588819
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3347490416
Short name T766
Test name
Test status
Simulation time 189130529 ps
CPU time 14.35 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:36 PM PDT 24
Peak memory 243864 kb
Host smart-fb712751-9ff2-462c-b15e-1b6769cfbda4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347490416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3347490416
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.295133813
Short name T751
Test name
Test status
Simulation time 183925736 ps
CPU time 4.54 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:26 PM PDT 24
Peak memory 240472 kb
Host smart-5da07dd6-0272-4989-81de-2dd9a7254512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=295133813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.295133813
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3693994312
Short name T719
Test name
Test status
Simulation time 22934235 ps
CPU time 1.76 seconds
Started Jul 11 04:47:18 PM PDT 24
Finished Jul 11 04:47:24 PM PDT 24
Peak memory 235600 kb
Host smart-ea6c9ae2-d606-43c1-884c-33379b4ab9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3693994312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3693994312
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.436078907
Short name T816
Test name
Test status
Simulation time 170975589 ps
CPU time 12.27 seconds
Started Jul 11 04:47:14 PM PDT 24
Finished Jul 11 04:47:28 PM PDT 24
Peak memory 244740 kb
Host smart-72c03bab-2a6c-429e-9a36-ca1c10236ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=436078907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.436078907
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2127690726
Short name T165
Test name
Test status
Simulation time 48796327639 ps
CPU time 920.32 seconds
Started Jul 11 04:47:29 PM PDT 24
Finished Jul 11 05:02:54 PM PDT 24
Peak memory 265276 kb
Host smart-9f8772b6-e35f-47da-b650-3a878c3d9cbb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127690726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2127690726
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1648634052
Short name T713
Test name
Test status
Simulation time 346671254 ps
CPU time 11.91 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:47:34 PM PDT 24
Peak memory 248652 kb
Host smart-6d886a29-ad4e-4ef6-81d9-30366a8c946b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1648634052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1648634052
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3127762144
Short name T205
Test name
Test status
Simulation time 59142613 ps
CPU time 4.61 seconds
Started Jul 11 04:47:24 PM PDT 24
Finished Jul 11 04:47:32 PM PDT 24
Peak memory 237556 kb
Host smart-c0e6d42c-c201-43b1-87b8-f2c0d1fc8d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127762144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3127762144
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1732453202
Short name T740
Test name
Test status
Simulation time 246830387 ps
CPU time 4.81 seconds
Started Jul 11 04:47:22 PM PDT 24
Finished Jul 11 04:47:31 PM PDT 24
Peak memory 236460 kb
Host smart-0a52b7d8-7007-454b-bc40-ac2e9b9c1fa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1732453202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1732453202
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3424508785
Short name T746
Test name
Test status
Simulation time 16731776 ps
CPU time 1.33 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:47:23 PM PDT 24
Peak memory 236504 kb
Host smart-45ed67aa-803d-4034-ad42-94fbce419d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3424508785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3424508785
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4104431261
Short name T750
Test name
Test status
Simulation time 679393273 ps
CPU time 22.8 seconds
Started Jul 11 04:47:20 PM PDT 24
Finished Jul 11 04:47:46 PM PDT 24
Peak memory 245752 kb
Host smart-f0fb31eb-07f2-4185-ab4d-c2d6f2781c48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4104431261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4104431261
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1149584297
Short name T151
Test name
Test status
Simulation time 6788363231 ps
CPU time 410.64 seconds
Started Jul 11 04:47:19 PM PDT 24
Finished Jul 11 04:54:13 PM PDT 24
Peak memory 268304 kb
Host smart-8df1a98d-8665-4a90-9ad5-0bc27b8cb301
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149584297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1149584297
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.168763229
Short name T791
Test name
Test status
Simulation time 1142387729 ps
CPU time 19.66 seconds
Started Jul 11 04:47:21 PM PDT 24
Finished Jul 11 04:47:45 PM PDT 24
Peak memory 248656 kb
Host smart-aca6e130-1723-4473-a491-25e3413ee668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=168763229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.168763229
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.4208761566
Short name T212
Test name
Test status
Simulation time 137639548593 ps
CPU time 1700.73 seconds
Started Jul 11 06:44:02 PM PDT 24
Finished Jul 11 07:12:24 PM PDT 24
Peak memory 273996 kb
Host smart-56c73f2f-04fc-4927-98f4-1cdfd1393077
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208761566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4208761566
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1195557918
Short name T702
Test name
Test status
Simulation time 448795376 ps
CPU time 8.37 seconds
Started Jul 11 06:44:10 PM PDT 24
Finished Jul 11 06:44:20 PM PDT 24
Peak memory 249232 kb
Host smart-0853080c-0f70-4b29-9417-231e2e9a9883
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1195557918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1195557918
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1269679727
Short name T378
Test name
Test status
Simulation time 3097558378 ps
CPU time 66.06 seconds
Started Jul 11 06:44:05 PM PDT 24
Finished Jul 11 06:45:12 PM PDT 24
Peak memory 256780 kb
Host smart-8d7f88f2-bbfe-4bfb-a420-24f1ddfd099d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12696
79727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1269679727
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2585231764
Short name T552
Test name
Test status
Simulation time 2078421109 ps
CPU time 72.44 seconds
Started Jul 11 06:44:05 PM PDT 24
Finished Jul 11 06:45:19 PM PDT 24
Peak memory 257072 kb
Host smart-52646050-62b8-4f50-8963-0cf0187f8f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
31764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2585231764
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.849964131
Short name T468
Test name
Test status
Simulation time 1953101661 ps
CPU time 32.32 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 06:44:42 PM PDT 24
Peak memory 249252 kb
Host smart-b16cba01-146f-4ef4-8fbf-766420b721aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84996
4131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.849964131
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.359767229
Short name T481
Test name
Test status
Simulation time 1630156135 ps
CPU time 49.54 seconds
Started Jul 11 06:44:07 PM PDT 24
Finished Jul 11 06:44:57 PM PDT 24
Peak memory 249088 kb
Host smart-e7f9d0d7-1b99-4c70-acb0-e033929ccefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35976
7229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.359767229
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4065244981
Short name T600
Test name
Test status
Simulation time 1967523535 ps
CPU time 64.27 seconds
Started Jul 11 06:44:05 PM PDT 24
Finished Jul 11 06:45:11 PM PDT 24
Peak memory 249332 kb
Host smart-2dc0ee3f-7e68-40f3-b71f-002e9c2eed9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40652
44981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4065244981
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1556656157
Short name T538
Test name
Test status
Simulation time 181386515 ps
CPU time 9.42 seconds
Started Jul 11 06:44:07 PM PDT 24
Finished Jul 11 06:44:17 PM PDT 24
Peak memory 249316 kb
Host smart-9df37413-11e4-4f66-9ebd-b75518516d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
56157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1556656157
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3835700658
Short name T699
Test name
Test status
Simulation time 134719107910 ps
CPU time 2368.7 seconds
Started Jul 11 06:44:10 PM PDT 24
Finished Jul 11 07:23:40 PM PDT 24
Peak memory 285280 kb
Host smart-33b9a351-e2ed-4548-807c-1135e9620c5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835700658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3835700658
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1917626753
Short name T383
Test name
Test status
Simulation time 261817552 ps
CPU time 14.57 seconds
Started Jul 11 06:44:16 PM PDT 24
Finished Jul 11 06:44:32 PM PDT 24
Peak memory 249328 kb
Host smart-336ebaf9-b336-48dd-8365-9a26406b26df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1917626753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1917626753
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2676842593
Short name T409
Test name
Test status
Simulation time 1421761359 ps
CPU time 19.49 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 06:44:30 PM PDT 24
Peak memory 255872 kb
Host smart-bfeb845d-4860-4a70-a5f5-053097709990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26768
42593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2676842593
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3845794316
Short name T319
Test name
Test status
Simulation time 36243694400 ps
CPU time 2344.29 seconds
Started Jul 11 06:44:10 PM PDT 24
Finished Jul 11 07:23:16 PM PDT 24
Peak memory 289804 kb
Host smart-88bcf4fd-0ff4-4fbf-8e3b-bc9276ad923f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845794316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3845794316
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4095121305
Short name T395
Test name
Test status
Simulation time 13311256279 ps
CPU time 1317.57 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 07:06:11 PM PDT 24
Peak memory 289368 kb
Host smart-297cbda5-6a96-444e-b2fa-1b57b5c84577
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095121305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4095121305
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.244234542
Short name T579
Test name
Test status
Simulation time 5243428822 ps
CPU time 88.05 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 06:45:38 PM PDT 24
Peak memory 249428 kb
Host smart-88907bf1-2198-4fa0-8d5f-8a9daa6c13c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244234542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.244234542
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3938076253
Short name T555
Test name
Test status
Simulation time 219591553 ps
CPU time 8.5 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 06:44:22 PM PDT 24
Peak memory 254056 kb
Host smart-b34dd9a4-546b-4ec6-b877-c6ab1c9a6a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
76253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3938076253
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3738680091
Short name T72
Test name
Test status
Simulation time 349577842 ps
CPU time 10.85 seconds
Started Jul 11 06:44:08 PM PDT 24
Finished Jul 11 06:44:20 PM PDT 24
Peak memory 248764 kb
Host smart-f95399d5-0dda-4509-8e1f-be5c3400bc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
80091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3738680091
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2391622845
Short name T15
Test name
Test status
Simulation time 2938489671 ps
CPU time 25.69 seconds
Started Jul 11 06:44:21 PM PDT 24
Finished Jul 11 06:44:48 PM PDT 24
Peak memory 271800 kb
Host smart-22a56105-b92a-425c-80cd-7f5a1bf4686d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2391622845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2391622845
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3578103778
Short name T372
Test name
Test status
Simulation time 45520364 ps
CPU time 7.17 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 06:44:18 PM PDT 24
Peak memory 254104 kb
Host smart-d4b295e3-1501-4b66-b42c-896b251b6b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35781
03778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3578103778
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.73045669
Short name T404
Test name
Test status
Simulation time 4854716240 ps
CPU time 34.93 seconds
Started Jul 11 06:44:09 PM PDT 24
Finished Jul 11 06:44:45 PM PDT 24
Peak memory 257508 kb
Host smart-58ae0649-3d6a-48aa-a293-a18c7eff4ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73045
669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.73045669
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2979540086
Short name T547
Test name
Test status
Simulation time 32679510833 ps
CPU time 2458.73 seconds
Started Jul 11 06:44:44 PM PDT 24
Finished Jul 11 07:25:45 PM PDT 24
Peak memory 289560 kb
Host smart-3814f575-cdba-4914-83ef-eb5e0e41e968
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979540086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2979540086
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2470164965
Short name T453
Test name
Test status
Simulation time 183459408 ps
CPU time 9.52 seconds
Started Jul 11 06:44:43 PM PDT 24
Finished Jul 11 06:44:55 PM PDT 24
Peak memory 249284 kb
Host smart-55958f64-500c-4a72-8751-f449a8d6c377
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2470164965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2470164965
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.257344649
Short name T411
Test name
Test status
Simulation time 1872841860 ps
CPU time 159.61 seconds
Started Jul 11 06:44:43 PM PDT 24
Finished Jul 11 06:47:25 PM PDT 24
Peak memory 257684 kb
Host smart-c422f816-66a1-4717-bb51-a523e1be921c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25734
4649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.257344649
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2194378083
Short name T525
Test name
Test status
Simulation time 1901328990 ps
CPU time 31.49 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 06:45:16 PM PDT 24
Peak memory 256140 kb
Host smart-c5c90ea3-c3c8-4e45-91d8-2a5b22df5f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943
78083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2194378083
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3176266884
Short name T636
Test name
Test status
Simulation time 21800845035 ps
CPU time 967.83 seconds
Started Jul 11 06:44:40 PM PDT 24
Finished Jul 11 07:00:50 PM PDT 24
Peak memory 273972 kb
Host smart-47fae91b-106b-47dd-bdc5-e14352abee02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176266884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3176266884
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.517152147
Short name T92
Test name
Test status
Simulation time 32659040305 ps
CPU time 742.11 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:57:06 PM PDT 24
Peak memory 273836 kb
Host smart-560e87f7-4940-4be8-82b5-1b33ea615a98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517152147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.517152147
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.608298537
Short name T300
Test name
Test status
Simulation time 773878341 ps
CPU time 47.58 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 06:45:31 PM PDT 24
Peak memory 256980 kb
Host smart-f5dd95fe-524a-4be1-bbdc-06a6f00a3d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60829
8537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.608298537
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2498687948
Short name T459
Test name
Test status
Simulation time 1712078342 ps
CPU time 48.06 seconds
Started Jul 11 06:44:46 PM PDT 24
Finished Jul 11 06:45:36 PM PDT 24
Peak memory 257484 kb
Host smart-2ddec9d5-6f69-4db2-8524-e14cf8380d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24986
87948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2498687948
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2708308346
Short name T208
Test name
Test status
Simulation time 866255322 ps
CPU time 16.47 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:44:59 PM PDT 24
Peak memory 248688 kb
Host smart-f70d77f8-b1fe-4691-a705-4fa45fe8ebec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
08346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2708308346
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1338937595
Short name T89
Test name
Test status
Simulation time 499796700 ps
CPU time 15.82 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:44:59 PM PDT 24
Peak memory 255460 kb
Host smart-dab357ce-19f5-45b5-89d6-242cc9bb6c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13389
37595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1338937595
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.493704889
Short name T127
Test name
Test status
Simulation time 667589648 ps
CPU time 76.57 seconds
Started Jul 11 06:44:40 PM PDT 24
Finished Jul 11 06:45:58 PM PDT 24
Peak memory 257524 kb
Host smart-90b2c6d5-6c44-44ed-a622-ac7308168f6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493704889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.493704889
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.560764694
Short name T265
Test name
Test status
Simulation time 78231881512 ps
CPU time 3855.26 seconds
Started Jul 11 06:44:43 PM PDT 24
Finished Jul 11 07:49:01 PM PDT 24
Peak memory 339664 kb
Host smart-74e6e3e7-247d-4c07-9519-d3b4a9e304a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560764694 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.560764694
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.667984651
Short name T221
Test name
Test status
Simulation time 80178143 ps
CPU time 3.99 seconds
Started Jul 11 06:44:53 PM PDT 24
Finished Jul 11 06:44:58 PM PDT 24
Peak memory 249556 kb
Host smart-2c635d8d-b5c7-4943-b7ee-afae24beb1e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=667984651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.667984651
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1367923530
Short name T415
Test name
Test status
Simulation time 90577191025 ps
CPU time 2837.67 seconds
Started Jul 11 06:44:49 PM PDT 24
Finished Jul 11 07:32:07 PM PDT 24
Peak memory 286292 kb
Host smart-72cdc48e-ae97-447b-ad3d-522b89e1c196
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367923530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1367923530
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1587395587
Short name T704
Test name
Test status
Simulation time 10014610886 ps
CPU time 23.84 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 06:45:11 PM PDT 24
Peak memory 249356 kb
Host smart-4f4f0bb6-3dc8-47ad-b4ed-eceaf12ecf86
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1587395587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1587395587
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3351167962
Short name T692
Test name
Test status
Simulation time 1482538183 ps
CPU time 113.23 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 06:46:40 PM PDT 24
Peak memory 257344 kb
Host smart-c7567a3f-7b3b-40d1-8e5b-b0e938be53ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33511
67962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3351167962
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2716791129
Short name T29
Test name
Test status
Simulation time 168147006 ps
CPU time 12.54 seconds
Started Jul 11 06:44:51 PM PDT 24
Finished Jul 11 06:45:04 PM PDT 24
Peak memory 256588 kb
Host smart-c386a340-3efd-449d-bac1-563a50acd25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
91129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2716791129
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2937794730
Short name T339
Test name
Test status
Simulation time 115587129061 ps
CPU time 1661.3 seconds
Started Jul 11 06:44:43 PM PDT 24
Finished Jul 11 07:12:27 PM PDT 24
Peak memory 273824 kb
Host smart-dba2a6a2-07d7-4aa3-a42e-77ee7f45fa98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937794730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2937794730
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3172750993
Short name T465
Test name
Test status
Simulation time 60541279503 ps
CPU time 1589.14 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 07:11:16 PM PDT 24
Peak memory 289884 kb
Host smart-8ab4124c-63c0-4ae3-ae2a-96cbb8e3478d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172750993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3172750993
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1037776870
Short name T311
Test name
Test status
Simulation time 9674642009 ps
CPU time 404.96 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 06:51:32 PM PDT 24
Peak memory 256708 kb
Host smart-ead9e7c0-8011-4d99-9777-15700567c2d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037776870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1037776870
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.409636098
Short name T246
Test name
Test status
Simulation time 1526375236 ps
CPU time 42.13 seconds
Started Jul 11 06:44:44 PM PDT 24
Finished Jul 11 06:45:29 PM PDT 24
Peak memory 249292 kb
Host smart-b83ddffe-27f4-4dc3-94b5-8cbc7af692a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40963
6098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.409636098
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.148584467
Short name T622
Test name
Test status
Simulation time 422602447 ps
CPU time 47.37 seconds
Started Jul 11 06:44:43 PM PDT 24
Finished Jul 11 06:45:33 PM PDT 24
Peak memory 249012 kb
Host smart-073a0a4c-1007-4465-b2ba-34a2e4f8d76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
4467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.148584467
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1271724167
Short name T536
Test name
Test status
Simulation time 462781012 ps
CPU time 13.36 seconds
Started Jul 11 06:44:46 PM PDT 24
Finished Jul 11 06:45:01 PM PDT 24
Peak memory 256872 kb
Host smart-efb24365-e656-4bdd-a57e-ee3f3b235209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12717
24167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1271724167
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.183319901
Short name T201
Test name
Test status
Simulation time 444169052 ps
CPU time 16.94 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 249304 kb
Host smart-888e1264-a4b4-481f-b5d8-afbca54e6f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18331
9901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.183319901
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.606003911
Short name T587
Test name
Test status
Simulation time 27404307011 ps
CPU time 533.93 seconds
Started Jul 11 06:44:43 PM PDT 24
Finished Jul 11 06:53:39 PM PDT 24
Peak memory 257596 kb
Host smart-cd7bc081-b997-4609-9666-bab643935a39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606003911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.606003911
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2660501350
Short name T229
Test name
Test status
Simulation time 134728123 ps
CPU time 2.97 seconds
Started Jul 11 06:44:54 PM PDT 24
Finished Jul 11 06:44:58 PM PDT 24
Peak memory 249576 kb
Host smart-cfc50f7c-5513-46be-af5b-36499ed170fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2660501350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2660501350
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.774012749
Short name T120
Test name
Test status
Simulation time 8300842439 ps
CPU time 1176.65 seconds
Started Jul 11 06:44:49 PM PDT 24
Finished Jul 11 07:04:26 PM PDT 24
Peak memory 290244 kb
Host smart-34553b2e-1ad6-40db-8ba8-992de1d61c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774012749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.774012749
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2386550487
Short name T428
Test name
Test status
Simulation time 1075038317 ps
CPU time 14.23 seconds
Started Jul 11 06:44:48 PM PDT 24
Finished Jul 11 06:45:03 PM PDT 24
Peak memory 249220 kb
Host smart-d953aa53-51f7-4979-8cdd-fdbd93067344
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2386550487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2386550487
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.249869008
Short name T473
Test name
Test status
Simulation time 632287073 ps
CPU time 28.85 seconds
Started Jul 11 06:44:49 PM PDT 24
Finished Jul 11 06:45:18 PM PDT 24
Peak memory 257456 kb
Host smart-09ff5eab-6fb4-4b0e-bcf0-ffd7f3a4ae5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24986
9008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.249869008
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.271798309
Short name T550
Test name
Test status
Simulation time 1114646218 ps
CPU time 45.43 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 06:45:32 PM PDT 24
Peak memory 256496 kb
Host smart-95da87fd-e574-4992-86a1-197eb3d77797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
8309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.271798309
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2170706273
Short name T346
Test name
Test status
Simulation time 118293499876 ps
CPU time 1808.41 seconds
Started Jul 11 06:44:51 PM PDT 24
Finished Jul 11 07:15:00 PM PDT 24
Peak memory 273340 kb
Host smart-d9678ce3-7199-42d8-95de-fc6231455a19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170706273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2170706273
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2950122458
Short name T515
Test name
Test status
Simulation time 69840354513 ps
CPU time 2019.62 seconds
Started Jul 11 06:44:52 PM PDT 24
Finished Jul 11 07:18:33 PM PDT 24
Peak memory 273668 kb
Host smart-603ad92d-2566-4ee8-a6a5-bd841a3ecbb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950122458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2950122458
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1514117500
Short name T237
Test name
Test status
Simulation time 12530192764 ps
CPU time 279.45 seconds
Started Jul 11 06:44:52 PM PDT 24
Finished Jul 11 06:49:32 PM PDT 24
Peak memory 255268 kb
Host smart-75a1c373-4ba8-46d1-bdba-074f3af19e08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514117500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1514117500
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.965503244
Short name T660
Test name
Test status
Simulation time 1613322560 ps
CPU time 25.06 seconds
Started Jul 11 06:44:44 PM PDT 24
Finished Jul 11 06:45:11 PM PDT 24
Peak memory 257356 kb
Host smart-678843ac-7a6f-4059-b283-ff30da8097cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96550
3244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.965503244
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3083039431
Short name T53
Test name
Test status
Simulation time 391422851 ps
CPU time 30.62 seconds
Started Jul 11 06:44:53 PM PDT 24
Finished Jul 11 06:45:24 PM PDT 24
Peak memory 257472 kb
Host smart-5ff69743-d8f3-4577-9a39-32ddf2782b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30830
39431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3083039431
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1269508135
Short name T371
Test name
Test status
Simulation time 867088611 ps
CPU time 22.09 seconds
Started Jul 11 06:44:51 PM PDT 24
Finished Jul 11 06:45:14 PM PDT 24
Peak memory 256520 kb
Host smart-fdba6836-4379-4138-a1ca-12da2bd5b26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12695
08135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1269508135
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1424592512
Short name T548
Test name
Test status
Simulation time 177244802 ps
CPU time 12.63 seconds
Started Jul 11 06:44:46 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 249280 kb
Host smart-0b6b1b58-3402-489a-bac5-84b0300c61d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
92512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1424592512
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2369568947
Short name T446
Test name
Test status
Simulation time 296823552 ps
CPU time 19.89 seconds
Started Jul 11 06:44:49 PM PDT 24
Finished Jul 11 06:45:10 PM PDT 24
Peak memory 256968 kb
Host smart-8dc47384-1950-48fa-ad35-d2a6a9db0abe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369568947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2369568947
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1937248093
Short name T264
Test name
Test status
Simulation time 150243892719 ps
CPU time 4879.59 seconds
Started Jul 11 06:44:54 PM PDT 24
Finished Jul 11 08:06:15 PM PDT 24
Peak memory 339056 kb
Host smart-b7375454-bc1d-41b1-9d0e-e7acb8d5297a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937248093 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1937248093
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3430096898
Short name T223
Test name
Test status
Simulation time 51843209 ps
CPU time 2.49 seconds
Started Jul 11 06:44:58 PM PDT 24
Finished Jul 11 06:45:01 PM PDT 24
Peak memory 249528 kb
Host smart-e2086be0-3b96-4f5f-8b96-eda6791c48cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3430096898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3430096898
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.221592127
Short name T666
Test name
Test status
Simulation time 83213259558 ps
CPU time 1369.66 seconds
Started Jul 11 06:45:01 PM PDT 24
Finished Jul 11 07:07:51 PM PDT 24
Peak memory 273528 kb
Host smart-9e1290ca-ea8b-4c1d-a9f6-a47cd17a75bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221592127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.221592127
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.691666169
Short name T657
Test name
Test status
Simulation time 700575706 ps
CPU time 32.5 seconds
Started Jul 11 06:44:59 PM PDT 24
Finished Jul 11 06:45:33 PM PDT 24
Peak memory 249304 kb
Host smart-4cdc9b3c-e9c0-4125-b093-ab506a04aaf2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=691666169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.691666169
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1018701286
Short name T67
Test name
Test status
Simulation time 25383435341 ps
CPU time 171.65 seconds
Started Jul 11 06:44:54 PM PDT 24
Finished Jul 11 06:47:46 PM PDT 24
Peak memory 256780 kb
Host smart-a1d98ecb-e3bf-4b5f-9381-a0f225f2daad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
01286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1018701286
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3493669137
Short name T81
Test name
Test status
Simulation time 202156180 ps
CPU time 6.95 seconds
Started Jul 11 06:44:55 PM PDT 24
Finished Jul 11 06:45:03 PM PDT 24
Peak memory 254912 kb
Host smart-edcf2e8b-79fd-478f-8f45-2dfe3ee93c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34936
69137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3493669137
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.25426902
Short name T122
Test name
Test status
Simulation time 75736114050 ps
CPU time 2389.86 seconds
Started Jul 11 06:44:59 PM PDT 24
Finished Jul 11 07:24:50 PM PDT 24
Peak memory 273960 kb
Host smart-988b0966-6c66-485a-b0e2-50629a9a560f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25426902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.25426902
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2177658071
Short name T318
Test name
Test status
Simulation time 12998650152 ps
CPU time 554.93 seconds
Started Jul 11 06:45:00 PM PDT 24
Finished Jul 11 06:54:16 PM PDT 24
Peak memory 249416 kb
Host smart-3fe2bf77-3dad-4cda-97e2-dc98b9bb41b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177658071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2177658071
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3155555812
Short name T612
Test name
Test status
Simulation time 2840166993 ps
CPU time 49.76 seconds
Started Jul 11 06:44:53 PM PDT 24
Finished Jul 11 06:45:44 PM PDT 24
Peak memory 256884 kb
Host smart-99a10a1e-0a02-487c-82d5-4b56987ce211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31555
55812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3155555812
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.207029049
Short name T441
Test name
Test status
Simulation time 3374408821 ps
CPU time 47.08 seconds
Started Jul 11 06:44:56 PM PDT 24
Finished Jul 11 06:45:44 PM PDT 24
Peak memory 249464 kb
Host smart-ee3b7973-a463-4e34-9b53-f67bb8d8aa43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
9049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.207029049
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3108664582
Short name T259
Test name
Test status
Simulation time 1106932548 ps
CPU time 72.7 seconds
Started Jul 11 06:44:57 PM PDT 24
Finished Jul 11 06:46:11 PM PDT 24
Peak memory 257072 kb
Host smart-55a36e9a-9471-4dea-afed-ebc488177829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31086
64582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3108664582
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3875207425
Short name T596
Test name
Test status
Simulation time 1432313583 ps
CPU time 46.69 seconds
Started Jul 11 06:44:56 PM PDT 24
Finished Jul 11 06:45:44 PM PDT 24
Peak memory 256556 kb
Host smart-90aa32b2-5311-469e-a527-57c90c7fa99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38752
07425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3875207425
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1153504533
Short name T529
Test name
Test status
Simulation time 39454032155 ps
CPU time 1297.38 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 07:06:47 PM PDT 24
Peak memory 273812 kb
Host smart-2246c9d3-440c-442c-9ce7-334e3a31e663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153504533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1153504533
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2126756947
Short name T425
Test name
Test status
Simulation time 4291663461 ps
CPU time 239.57 seconds
Started Jul 11 06:45:06 PM PDT 24
Finished Jul 11 06:49:06 PM PDT 24
Peak memory 257592 kb
Host smart-39be445a-8c64-4ed8-8716-c307646cc9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21267
56947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2126756947
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1982196263
Short name T648
Test name
Test status
Simulation time 25747068819 ps
CPU time 1238.48 seconds
Started Jul 11 06:45:08 PM PDT 24
Finished Jul 11 07:05:48 PM PDT 24
Peak memory 289444 kb
Host smart-92fc90ee-73bf-4383-9204-d6d3d2e439fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982196263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1982196263
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3485317290
Short name T682
Test name
Test status
Simulation time 9533041034 ps
CPU time 101.17 seconds
Started Jul 11 06:45:10 PM PDT 24
Finished Jul 11 06:46:53 PM PDT 24
Peak memory 249396 kb
Host smart-6f8a0b4f-6515-4dff-946a-5d7fe8f08dff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485317290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3485317290
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2739811073
Short name T43
Test name
Test status
Simulation time 686608392 ps
CPU time 13.78 seconds
Started Jul 11 06:45:06 PM PDT 24
Finished Jul 11 06:45:21 PM PDT 24
Peak memory 249304 kb
Host smart-36075144-b7fa-4fd7-8c89-dc79c2477264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27398
11073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2739811073
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3129329959
Short name T476
Test name
Test status
Simulation time 4143568351 ps
CPU time 52.69 seconds
Started Jul 11 06:45:06 PM PDT 24
Finished Jul 11 06:46:00 PM PDT 24
Peak memory 249388 kb
Host smart-2a876187-2f41-4f11-839a-260bffb01c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31293
29959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3129329959
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3366664847
Short name T512
Test name
Test status
Simulation time 418047908 ps
CPU time 8.51 seconds
Started Jul 11 06:45:08 PM PDT 24
Finished Jul 11 06:45:18 PM PDT 24
Peak memory 253056 kb
Host smart-5613aabf-148f-4b77-b0e9-ab4dbfb1a095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666
64847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3366664847
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2363264503
Short name T382
Test name
Test status
Simulation time 564295656 ps
CPU time 36.93 seconds
Started Jul 11 06:45:07 PM PDT 24
Finished Jul 11 06:45:45 PM PDT 24
Peak memory 257432 kb
Host smart-5dabc11f-1901-4a54-b74f-d57fc3802e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
64503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2363264503
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.277995742
Short name T227
Test name
Test status
Simulation time 15081982 ps
CPU time 2.51 seconds
Started Jul 11 06:45:17 PM PDT 24
Finished Jul 11 06:45:20 PM PDT 24
Peak memory 249616 kb
Host smart-d71f48a0-2c94-4386-804f-67b854108511
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=277995742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.277995742
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2936282856
Short name T449
Test name
Test status
Simulation time 25093667558 ps
CPU time 1944.08 seconds
Started Jul 11 06:45:16 PM PDT 24
Finished Jul 11 07:17:41 PM PDT 24
Peak memory 290076 kb
Host smart-878b6483-3bdb-4251-84cc-f42821742fd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936282856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2936282856
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2398818714
Short name T513
Test name
Test status
Simulation time 410328862 ps
CPU time 20.2 seconds
Started Jul 11 06:45:11 PM PDT 24
Finished Jul 11 06:45:33 PM PDT 24
Peak memory 249388 kb
Host smart-4da732fe-9aba-4d85-8874-40fab5eff5a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2398818714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2398818714
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1132114982
Short name T430
Test name
Test status
Simulation time 4032803511 ps
CPU time 62.76 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 06:46:13 PM PDT 24
Peak memory 257160 kb
Host smart-9a5de413-ee47-406b-901a-ab08f3ba20f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11321
14982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1132114982
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.45777620
Short name T432
Test name
Test status
Simulation time 411610421 ps
CPU time 14.41 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 06:45:25 PM PDT 24
Peak memory 248756 kb
Host smart-f13d458a-a225-4bd3-9ebd-ed68a8d83f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45777
620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.45777620
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2334259704
Short name T239
Test name
Test status
Simulation time 17107917935 ps
CPU time 1767.84 seconds
Started Jul 11 06:45:16 PM PDT 24
Finished Jul 11 07:14:45 PM PDT 24
Peak memory 290056 kb
Host smart-e7cfac51-1b56-4d82-a595-b125d5a22f7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334259704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2334259704
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1279047408
Short name T204
Test name
Test status
Simulation time 61504414323 ps
CPU time 1952.28 seconds
Started Jul 11 06:45:11 PM PDT 24
Finished Jul 11 07:17:45 PM PDT 24
Peak memory 273908 kb
Host smart-08ea3bdb-e0e2-4de6-8c6e-b22614cd715d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279047408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1279047408
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1236207461
Short name T312
Test name
Test status
Simulation time 31673274405 ps
CPU time 320.8 seconds
Started Jul 11 06:45:12 PM PDT 24
Finished Jul 11 06:50:34 PM PDT 24
Peak memory 256324 kb
Host smart-3e18f78d-d8b3-4aea-aeb4-a86b7789c4ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236207461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1236207461
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.847008706
Short name T564
Test name
Test status
Simulation time 11441737636 ps
CPU time 67.83 seconds
Started Jul 11 06:45:09 PM PDT 24
Finished Jul 11 06:46:18 PM PDT 24
Peak memory 257528 kb
Host smart-7d9dcf17-b5d4-42c2-8f98-1faa5a9d1aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84700
8706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.847008706
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.447938260
Short name T500
Test name
Test status
Simulation time 154037251 ps
CPU time 10.13 seconds
Started Jul 11 06:45:10 PM PDT 24
Finished Jul 11 06:45:21 PM PDT 24
Peak memory 252540 kb
Host smart-0b98efc3-908b-40f7-b4dd-8e360271141e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44793
8260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.447938260
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3103143470
Short name T100
Test name
Test status
Simulation time 781158177 ps
CPU time 45.98 seconds
Started Jul 11 06:45:12 PM PDT 24
Finished Jul 11 06:45:59 PM PDT 24
Peak memory 248572 kb
Host smart-05e0cfd2-124f-45e0-b470-7a2b4966ea7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031
43470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3103143470
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1547661441
Short name T99
Test name
Test status
Simulation time 642448699 ps
CPU time 40.44 seconds
Started Jul 11 06:45:10 PM PDT 24
Finished Jul 11 06:45:52 PM PDT 24
Peak memory 256552 kb
Host smart-03ce86c1-215d-4fc6-b61c-907a4639a1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
61441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1547661441
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2767624210
Short name T423
Test name
Test status
Simulation time 21347688418 ps
CPU time 1232.69 seconds
Started Jul 11 06:45:20 PM PDT 24
Finished Jul 11 07:05:53 PM PDT 24
Peak memory 273956 kb
Host smart-0c345b55-98ea-4491-aee9-b97a6003c99e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767624210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2767624210
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.898913641
Short name T22
Test name
Test status
Simulation time 45947307 ps
CPU time 3.86 seconds
Started Jul 11 06:45:27 PM PDT 24
Finished Jul 11 06:45:32 PM PDT 24
Peak memory 249496 kb
Host smart-a0d8aea5-5a66-4066-996e-5f500fb94d80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=898913641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.898913641
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3531060800
Short name T469
Test name
Test status
Simulation time 23611574425 ps
CPU time 1474.3 seconds
Started Jul 11 06:45:21 PM PDT 24
Finished Jul 11 07:09:56 PM PDT 24
Peak memory 290128 kb
Host smart-43c9eea6-50dd-42df-8c53-083cb9ef53d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531060800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3531060800
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2972708273
Short name T401
Test name
Test status
Simulation time 470913975 ps
CPU time 22.29 seconds
Started Jul 11 06:45:20 PM PDT 24
Finished Jul 11 06:45:43 PM PDT 24
Peak memory 249300 kb
Host smart-abf347a0-4054-4704-b844-f65341004fe1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2972708273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2972708273
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3016420430
Short name T491
Test name
Test status
Simulation time 4096598748 ps
CPU time 125.72 seconds
Started Jul 11 06:45:22 PM PDT 24
Finished Jul 11 06:47:28 PM PDT 24
Peak memory 256840 kb
Host smart-cfb402b0-ab3a-4c8c-a0f3-86f8ca6cc53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30164
20430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3016420430
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3512243003
Short name T393
Test name
Test status
Simulation time 202092571 ps
CPU time 18.02 seconds
Started Jul 11 06:45:22 PM PDT 24
Finished Jul 11 06:45:41 PM PDT 24
Peak memory 257032 kb
Host smart-edef8c07-bc5b-4142-a04d-dd7462b75d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122
43003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3512243003
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3068911433
Short name T651
Test name
Test status
Simulation time 91589962430 ps
CPU time 1376.12 seconds
Started Jul 11 06:45:20 PM PDT 24
Finished Jul 11 07:08:17 PM PDT 24
Peak memory 265808 kb
Host smart-ccd91235-d143-42e7-8f7a-4466b1e47cb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068911433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3068911433
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3128616260
Short name T695
Test name
Test status
Simulation time 10729153403 ps
CPU time 960.58 seconds
Started Jul 11 06:45:19 PM PDT 24
Finished Jul 11 07:01:20 PM PDT 24
Peak memory 273828 kb
Host smart-a554ebdd-7edb-42ec-947e-a9c6720c577e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128616260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3128616260
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1950045799
Short name T306
Test name
Test status
Simulation time 37878825274 ps
CPU time 401.4 seconds
Started Jul 11 06:45:23 PM PDT 24
Finished Jul 11 06:52:05 PM PDT 24
Peak memory 249400 kb
Host smart-ec28a7e7-9e79-4a3f-a9e3-79615bb97aa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950045799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1950045799
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3344399080
Short name T664
Test name
Test status
Simulation time 2302553153 ps
CPU time 57.19 seconds
Started Jul 11 06:45:16 PM PDT 24
Finished Jul 11 06:46:14 PM PDT 24
Peak memory 257296 kb
Host smart-c0551eb0-adee-45b2-88df-da531ed4830f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33443
99080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3344399080
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4160289358
Short name T25
Test name
Test status
Simulation time 222793237 ps
CPU time 8.12 seconds
Started Jul 11 06:45:23 PM PDT 24
Finished Jul 11 06:45:32 PM PDT 24
Peak memory 248704 kb
Host smart-b3f47557-a870-45d3-a1f7-92f6f8bce798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
89358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4160289358
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.386401259
Short name T631
Test name
Test status
Simulation time 776992891 ps
CPU time 27.73 seconds
Started Jul 11 06:45:21 PM PDT 24
Finished Jul 11 06:45:50 PM PDT 24
Peak memory 249860 kb
Host smart-1d873af2-9ad6-4893-8c6e-5cd86edcd1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640
1259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.386401259
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4070094279
Short name T470
Test name
Test status
Simulation time 464571678 ps
CPU time 36.93 seconds
Started Jul 11 06:45:36 PM PDT 24
Finished Jul 11 06:46:14 PM PDT 24
Peak memory 257480 kb
Host smart-455b80b9-8aee-4b89-bbe7-6cb1803b6911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40700
94279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4070094279
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2929942329
Short name T117
Test name
Test status
Simulation time 67161319565 ps
CPU time 2504.94 seconds
Started Jul 11 06:45:27 PM PDT 24
Finished Jul 11 07:27:13 PM PDT 24
Peak memory 288580 kb
Host smart-7d8f460c-30ce-4ca6-b081-48a432071046
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929942329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2929942329
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2038879776
Short name T610
Test name
Test status
Simulation time 196948913884 ps
CPU time 4931.86 seconds
Started Jul 11 06:45:27 PM PDT 24
Finished Jul 11 08:07:41 PM PDT 24
Peak memory 322572 kb
Host smart-0d490156-0adf-48ed-bc52-f97a595e1672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038879776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2038879776
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2552896539
Short name T234
Test name
Test status
Simulation time 92539602 ps
CPU time 3.93 seconds
Started Jul 11 06:45:35 PM PDT 24
Finished Jul 11 06:45:39 PM PDT 24
Peak memory 249584 kb
Host smart-75dd52f2-2799-4f08-9220-654af6a66175
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2552896539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2552896539
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1335180344
Short name T646
Test name
Test status
Simulation time 144361991655 ps
CPU time 2690.81 seconds
Started Jul 11 06:45:31 PM PDT 24
Finished Jul 11 07:30:23 PM PDT 24
Peak memory 290072 kb
Host smart-1f785768-afce-4010-8e4b-a8a958b9dcf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335180344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1335180344
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2253205503
Short name T672
Test name
Test status
Simulation time 258982395 ps
CPU time 8.94 seconds
Started Jul 11 06:45:35 PM PDT 24
Finished Jul 11 06:45:45 PM PDT 24
Peak memory 249180 kb
Host smart-e59ff9e9-ad77-4d89-8fbc-651154946d42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2253205503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2253205503
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.813106000
Short name T245
Test name
Test status
Simulation time 211306526 ps
CPU time 12.92 seconds
Started Jul 11 06:45:31 PM PDT 24
Finished Jul 11 06:45:45 PM PDT 24
Peak memory 256112 kb
Host smart-c276673f-156b-4bec-a946-d019590e47b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81310
6000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.813106000
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2765174995
Short name T443
Test name
Test status
Simulation time 4044883206 ps
CPU time 22.07 seconds
Started Jul 11 06:45:26 PM PDT 24
Finished Jul 11 06:45:48 PM PDT 24
Peak memory 255772 kb
Host smart-e0f67bb9-f7a0-4c15-b33f-ffb49594a8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
74995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2765174995
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2742948782
Short name T95
Test name
Test status
Simulation time 44660312259 ps
CPU time 1250.92 seconds
Started Jul 11 06:45:32 PM PDT 24
Finished Jul 11 07:06:24 PM PDT 24
Peak memory 284736 kb
Host smart-a756dad4-5f12-47b2-a994-150421158c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742948782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2742948782
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2346939618
Short name T595
Test name
Test status
Simulation time 10036040366 ps
CPU time 999.09 seconds
Started Jul 11 06:45:30 PM PDT 24
Finished Jul 11 07:02:10 PM PDT 24
Peak memory 272456 kb
Host smart-ea2e578b-fcb8-4ad0-8285-6c37710e64c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346939618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2346939618
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1134116662
Short name T665
Test name
Test status
Simulation time 505393568 ps
CPU time 33.44 seconds
Started Jul 11 06:45:28 PM PDT 24
Finished Jul 11 06:46:02 PM PDT 24
Peak memory 249332 kb
Host smart-44eed3df-327c-40d5-8134-094799aabbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11341
16662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1134116662
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2680061503
Short name T486
Test name
Test status
Simulation time 558991496 ps
CPU time 19.9 seconds
Started Jul 11 06:45:27 PM PDT 24
Finished Jul 11 06:45:48 PM PDT 24
Peak memory 257244 kb
Host smart-765fa66c-9655-4fbd-9778-83764fe4882f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26800
61503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2680061503
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2218951687
Short name T551
Test name
Test status
Simulation time 103472214 ps
CPU time 12.43 seconds
Started Jul 11 06:45:25 PM PDT 24
Finished Jul 11 06:45:38 PM PDT 24
Peak memory 257424 kb
Host smart-8effa8f3-c870-45dc-a5d1-067ee726337a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
51687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2218951687
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2971756957
Short name T235
Test name
Test status
Simulation time 147323646 ps
CPU time 2.53 seconds
Started Jul 11 06:45:35 PM PDT 24
Finished Jul 11 06:45:38 PM PDT 24
Peak memory 249600 kb
Host smart-090673ba-9204-44d4-98bc-dce23c9c5b98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2971756957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2971756957
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.15562751
Short name T590
Test name
Test status
Simulation time 23689695314 ps
CPU time 1314.05 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 07:07:35 PM PDT 24
Peak memory 273632 kb
Host smart-c8867081-84a1-4a1f-a8f8-0da9c5a2ee23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15562751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.15562751
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1671135424
Short name T652
Test name
Test status
Simulation time 1116229732 ps
CPU time 14.77 seconds
Started Jul 11 06:45:35 PM PDT 24
Finished Jul 11 06:45:50 PM PDT 24
Peak memory 249452 kb
Host smart-c846d313-90c7-431d-8202-f20a94ec618d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1671135424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1671135424
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3463558615
Short name T489
Test name
Test status
Simulation time 558954091 ps
CPU time 35.5 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 06:46:17 PM PDT 24
Peak memory 256632 kb
Host smart-e19625c8-95de-4e06-8488-fa4522f6b0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34635
58615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3463558615
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.526313288
Short name T450
Test name
Test status
Simulation time 2011800232 ps
CPU time 35.98 seconds
Started Jul 11 06:45:36 PM PDT 24
Finished Jul 11 06:46:13 PM PDT 24
Peak memory 256680 kb
Host smart-7b39b30e-a64b-4ea0-af56-dcfaf970e515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52631
3288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.526313288
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1257942163
Short name T542
Test name
Test status
Simulation time 33607644787 ps
CPU time 2125.6 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 07:21:07 PM PDT 24
Peak memory 274064 kb
Host smart-7f972328-ac57-4ab0-acfd-d0787d91ae01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257942163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1257942163
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1967737164
Short name T667
Test name
Test status
Simulation time 25972396250 ps
CPU time 507.53 seconds
Started Jul 11 06:45:37 PM PDT 24
Finished Jul 11 06:54:06 PM PDT 24
Peak memory 249412 kb
Host smart-b3974592-091d-429b-9323-84bf76a4b493
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967737164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1967737164
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1708805552
Short name T628
Test name
Test status
Simulation time 2281665774 ps
CPU time 11.15 seconds
Started Jul 11 06:45:35 PM PDT 24
Finished Jul 11 06:45:48 PM PDT 24
Peak memory 249380 kb
Host smart-046aa56f-e86f-40cd-b1fa-de24e02d2da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088
05552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1708805552
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2520933303
Short name T426
Test name
Test status
Simulation time 2595188770 ps
CPU time 43.01 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 06:46:25 PM PDT 24
Peak memory 256872 kb
Host smart-4d488462-8de3-4e03-9a11-8e837a7ef71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209
33303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2520933303
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2290282593
Short name T23
Test name
Test status
Simulation time 1390758065 ps
CPU time 22.98 seconds
Started Jul 11 06:45:41 PM PDT 24
Finished Jul 11 06:46:05 PM PDT 24
Peak memory 249848 kb
Host smart-f3517270-478a-473f-b489-f6271ac20f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22902
82593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2290282593
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2673531493
Short name T643
Test name
Test status
Simulation time 55625889121 ps
CPU time 3488.14 seconds
Started Jul 11 06:45:36 PM PDT 24
Finished Jul 11 07:43:45 PM PDT 24
Peak memory 290436 kb
Host smart-f71ed17a-1a59-4cca-8c8d-7c4621859453
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673531493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2673531493
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1702123232
Short name T228
Test name
Test status
Simulation time 164106996 ps
CPU time 4.25 seconds
Started Jul 11 06:45:46 PM PDT 24
Finished Jul 11 06:45:50 PM PDT 24
Peak memory 249576 kb
Host smart-0371c1a5-9c2d-42e2-a84e-4eebf9fa377a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1702123232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1702123232
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4276598891
Short name T125
Test name
Test status
Simulation time 22340342392 ps
CPU time 1307.05 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 07:07:28 PM PDT 24
Peak memory 286908 kb
Host smart-47f64aca-bfb3-4d6d-b371-f5100ea58b0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276598891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4276598891
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4070200713
Short name T511
Test name
Test status
Simulation time 122392259 ps
CPU time 7.3 seconds
Started Jul 11 06:45:43 PM PDT 24
Finished Jul 11 06:45:51 PM PDT 24
Peak memory 249236 kb
Host smart-a4529c8d-8890-454d-8f65-891e6ce8b3a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4070200713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4070200713
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3835899663
Short name T480
Test name
Test status
Simulation time 5410689156 ps
CPU time 313.87 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 06:50:54 PM PDT 24
Peak memory 257812 kb
Host smart-ed19f213-874a-4b03-a896-35a9d42b8c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358
99663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3835899663
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3954876686
Short name T287
Test name
Test status
Simulation time 544987484 ps
CPU time 31.81 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 06:46:13 PM PDT 24
Peak memory 249212 kb
Host smart-8c72993e-f9ea-4cd1-8ffb-917dd911f201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548
76686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3954876686
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3589154305
Short name T599
Test name
Test status
Simulation time 42233077886 ps
CPU time 1915.1 seconds
Started Jul 11 06:45:42 PM PDT 24
Finished Jul 11 07:17:38 PM PDT 24
Peak memory 290260 kb
Host smart-a974a54c-de99-4e70-ac8c-407adbb69c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589154305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3589154305
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1539652811
Short name T681
Test name
Test status
Simulation time 7527141955 ps
CPU time 644.12 seconds
Started Jul 11 06:45:45 PM PDT 24
Finished Jul 11 06:56:30 PM PDT 24
Peak memory 265804 kb
Host smart-c8c4cd38-eb60-46d4-8495-2134ba09f564
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539652811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1539652811
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2475303244
Short name T307
Test name
Test status
Simulation time 12589788509 ps
CPU time 547.87 seconds
Started Jul 11 06:45:39 PM PDT 24
Finished Jul 11 06:54:47 PM PDT 24
Peak memory 248272 kb
Host smart-771c8c73-c56d-45e2-83c0-85d13894936a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475303244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2475303244
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1322892334
Short name T379
Test name
Test status
Simulation time 2656526374 ps
CPU time 41.87 seconds
Started Jul 11 06:45:41 PM PDT 24
Finished Jul 11 06:46:24 PM PDT 24
Peak memory 257536 kb
Host smart-07a65fe1-dc9e-4f42-aee5-4fdb22721e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
92334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1322892334
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2480167326
Short name T545
Test name
Test status
Simulation time 549112912 ps
CPU time 38.96 seconds
Started Jul 11 06:45:39 PM PDT 24
Finished Jul 11 06:46:19 PM PDT 24
Peak memory 256988 kb
Host smart-0f65cea9-21d5-41f7-8454-47a264166375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
67326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2480167326
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4172884767
Short name T561
Test name
Test status
Simulation time 1345051778 ps
CPU time 49.19 seconds
Started Jul 11 06:45:40 PM PDT 24
Finished Jul 11 06:46:30 PM PDT 24
Peak memory 256792 kb
Host smart-55f0c1d0-26aa-4e8a-8405-aeb36d5e9c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41728
84767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4172884767
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3116246471
Short name T494
Test name
Test status
Simulation time 73754447 ps
CPU time 5.76 seconds
Started Jul 11 06:45:37 PM PDT 24
Finished Jul 11 06:45:43 PM PDT 24
Peak memory 255132 kb
Host smart-c7f97ba1-dbb5-448a-8e93-9a5ba87c5a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31162
46471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3116246471
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2285709906
Short name T65
Test name
Test status
Simulation time 1747068735 ps
CPU time 97.33 seconds
Started Jul 11 06:45:43 PM PDT 24
Finished Jul 11 06:47:22 PM PDT 24
Peak memory 257400 kb
Host smart-265c1b85-3407-45e8-983c-20946c3ce4ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285709906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2285709906
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.372052762
Short name T220
Test name
Test status
Simulation time 32484106 ps
CPU time 2.73 seconds
Started Jul 11 06:44:20 PM PDT 24
Finished Jul 11 06:44:24 PM PDT 24
Peak memory 249580 kb
Host smart-571968bd-55ae-4531-9218-aab9fd9d7f21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=372052762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.372052762
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2223354155
Short name T56
Test name
Test status
Simulation time 10802172437 ps
CPU time 849.65 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 06:58:23 PM PDT 24
Peak memory 273984 kb
Host smart-0a9b232f-bf61-47f3-b38f-a41ec3f1d3b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223354155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2223354155
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2721811719
Short name T655
Test name
Test status
Simulation time 1399561031 ps
CPU time 17.67 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 06:44:31 PM PDT 24
Peak memory 249292 kb
Host smart-2099c1f0-9b64-491e-bec1-dda9cb250dde
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2721811719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2721811719
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1076202700
Short name T209
Test name
Test status
Simulation time 13545406155 ps
CPU time 205.7 seconds
Started Jul 11 06:44:14 PM PDT 24
Finished Jul 11 06:47:41 PM PDT 24
Peak memory 257176 kb
Host smart-02433e41-52e4-4005-91c2-c9b7fc50b6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
02700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1076202700
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2565009208
Short name T410
Test name
Test status
Simulation time 593524088 ps
CPU time 10.67 seconds
Started Jul 11 06:44:13 PM PDT 24
Finished Jul 11 06:44:24 PM PDT 24
Peak memory 249336 kb
Host smart-24a3b003-d286-4977-a3cd-517726386e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
09208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2565009208
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1062456310
Short name T626
Test name
Test status
Simulation time 23784227986 ps
CPU time 880.98 seconds
Started Jul 11 06:44:16 PM PDT 24
Finished Jul 11 06:58:58 PM PDT 24
Peak memory 282308 kb
Host smart-68e111e3-5441-4c7b-9cce-f96c59b8cbe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062456310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1062456310
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4152671272
Short name T620
Test name
Test status
Simulation time 45105914927 ps
CPU time 2773.29 seconds
Started Jul 11 06:44:16 PM PDT 24
Finished Jul 11 07:30:31 PM PDT 24
Peak memory 282208 kb
Host smart-c0cc3834-ac15-450f-8210-d812c9d30e11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152671272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4152671272
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.79465211
Short name T191
Test name
Test status
Simulation time 8708865479 ps
CPU time 290.92 seconds
Started Jul 11 06:44:14 PM PDT 24
Finished Jul 11 06:49:06 PM PDT 24
Peak memory 249364 kb
Host smart-358a422e-9778-4eb8-bc66-c62922eb20d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79465211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.79465211
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2094343664
Short name T650
Test name
Test status
Simulation time 911078870 ps
CPU time 21.9 seconds
Started Jul 11 06:44:21 PM PDT 24
Finished Jul 11 06:44:45 PM PDT 24
Peak memory 249220 kb
Host smart-1100b968-04b7-4fe2-9cf8-2b87f2382090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
43664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2094343664
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.962888489
Short name T85
Test name
Test status
Simulation time 134060451 ps
CPU time 15.87 seconds
Started Jul 11 06:44:12 PM PDT 24
Finished Jul 11 06:44:28 PM PDT 24
Peak memory 256988 kb
Host smart-9873a438-caee-48cd-ac7b-c3fc5ee9293f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96288
8489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.962888489
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4123588297
Short name T84
Test name
Test status
Simulation time 269481582 ps
CPU time 16.39 seconds
Started Jul 11 06:44:15 PM PDT 24
Finished Jul 11 06:44:33 PM PDT 24
Peak memory 248836 kb
Host smart-d4ed7aa7-a3ba-4397-8266-d9986658a0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41235
88297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4123588297
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.261681443
Short name T492
Test name
Test status
Simulation time 1512788442 ps
CPU time 48.4 seconds
Started Jul 11 06:44:14 PM PDT 24
Finished Jul 11 06:45:03 PM PDT 24
Peak memory 249740 kb
Host smart-efad5a0b-5357-476d-b747-b9aa60a4dbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26168
1443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.261681443
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.77546186
Short name T16
Test name
Test status
Simulation time 56824133868 ps
CPU time 1327.14 seconds
Started Jul 11 06:45:49 PM PDT 24
Finished Jul 11 07:07:57 PM PDT 24
Peak memory 289308 kb
Host smart-04f9981d-7b5c-42a9-ad93-e0be7059134e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77546186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.77546186
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3867660761
Short name T523
Test name
Test status
Simulation time 738378068 ps
CPU time 18.63 seconds
Started Jul 11 06:45:48 PM PDT 24
Finished Jul 11 06:46:08 PM PDT 24
Peak memory 256984 kb
Host smart-b0b36176-ee98-4ad9-b74d-97cc8a0d452e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
60761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3867660761
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3987164246
Short name T377
Test name
Test status
Simulation time 1821427916 ps
CPU time 30.59 seconds
Started Jul 11 06:45:48 PM PDT 24
Finished Jul 11 06:46:20 PM PDT 24
Peak memory 248848 kb
Host smart-7ed48346-452e-46d0-93cc-c41fd847e815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39871
64246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3987164246
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.610810778
Short name T488
Test name
Test status
Simulation time 142805196877 ps
CPU time 2054.69 seconds
Started Jul 11 06:45:47 PM PDT 24
Finished Jul 11 07:20:02 PM PDT 24
Peak memory 282204 kb
Host smart-e23872ee-a286-44f0-93ba-7c287c1dbeef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610810778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.610810778
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1849061974
Short name T302
Test name
Test status
Simulation time 1756256798 ps
CPU time 81.29 seconds
Started Jul 11 06:45:48 PM PDT 24
Finished Jul 11 06:47:10 PM PDT 24
Peak memory 249268 kb
Host smart-742a522b-298c-4a74-b5f8-b2e8289dcae6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849061974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1849061974
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.30388661
Short name T405
Test name
Test status
Simulation time 237858010 ps
CPU time 33.48 seconds
Started Jul 11 06:45:48 PM PDT 24
Finished Jul 11 06:46:23 PM PDT 24
Peak memory 249220 kb
Host smart-c171fe0c-f660-4bd8-8c40-2dd5edf6cee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30388
661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.30388661
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3422127758
Short name T447
Test name
Test status
Simulation time 526632177 ps
CPU time 14.87 seconds
Started Jul 11 06:45:49 PM PDT 24
Finished Jul 11 06:46:05 PM PDT 24
Peak memory 248740 kb
Host smart-8f7eb484-0fea-4b61-8321-4c6d803ff7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221
27758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3422127758
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4083916825
Short name T582
Test name
Test status
Simulation time 1011538944 ps
CPU time 33.19 seconds
Started Jul 11 06:45:47 PM PDT 24
Finished Jul 11 06:46:21 PM PDT 24
Peak memory 248788 kb
Host smart-ac10d1f1-9ca2-49d6-b030-73f0ad38635c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40839
16825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4083916825
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1383350180
Short name T592
Test name
Test status
Simulation time 302579739 ps
CPU time 6.99 seconds
Started Jul 11 06:45:44 PM PDT 24
Finished Jul 11 06:45:52 PM PDT 24
Peak memory 255684 kb
Host smart-b8643a46-53be-481a-910d-d6a7f68c5102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13833
50180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1383350180
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3318755821
Short name T243
Test name
Test status
Simulation time 109776548965 ps
CPU time 3397.81 seconds
Started Jul 11 06:45:53 PM PDT 24
Finished Jul 11 07:42:32 PM PDT 24
Peak memory 298588 kb
Host smart-ac7af568-364c-47a3-bfb0-c33823d298f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318755821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3318755821
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.732773637
Short name T418
Test name
Test status
Simulation time 82833063055 ps
CPU time 1216.06 seconds
Started Jul 11 06:45:56 PM PDT 24
Finished Jul 11 07:06:13 PM PDT 24
Peak memory 290092 kb
Host smart-19857b3a-5538-4fff-a703-65fc14f89419
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732773637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.732773637
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3466356820
Short name T527
Test name
Test status
Simulation time 3068381113 ps
CPU time 48.29 seconds
Started Jul 11 06:45:57 PM PDT 24
Finished Jul 11 06:46:46 PM PDT 24
Peak memory 257108 kb
Host smart-93345918-53be-46d2-aa1c-ae3e96208026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34663
56820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3466356820
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2228400996
Short name T132
Test name
Test status
Simulation time 760885919 ps
CPU time 46.98 seconds
Started Jul 11 06:45:54 PM PDT 24
Finished Jul 11 06:46:41 PM PDT 24
Peak memory 256864 kb
Host smart-783e56a0-b288-4f14-97d2-2e6b4a8cc104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284
00996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2228400996
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3722462370
Short name T585
Test name
Test status
Simulation time 51185318904 ps
CPU time 1291.49 seconds
Started Jul 11 06:45:57 PM PDT 24
Finished Jul 11 07:07:30 PM PDT 24
Peak memory 290316 kb
Host smart-febb791e-726e-4b8e-84e8-ee401f9bd31e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722462370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3722462370
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.578514269
Short name T671
Test name
Test status
Simulation time 143612974108 ps
CPU time 2227.7 seconds
Started Jul 11 06:45:56 PM PDT 24
Finished Jul 11 07:23:05 PM PDT 24
Peak memory 289488 kb
Host smart-3d0538fd-f6ee-420f-b105-5be3bbc5d3cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578514269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.578514269
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.449059684
Short name T308
Test name
Test status
Simulation time 56454987959 ps
CPU time 558.14 seconds
Started Jul 11 06:45:55 PM PDT 24
Finished Jul 11 06:55:14 PM PDT 24
Peak memory 257556 kb
Host smart-6ee2da34-981e-404c-90ac-37dec6bf97e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449059684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.449059684
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.363038290
Short name T593
Test name
Test status
Simulation time 11436875157 ps
CPU time 51.59 seconds
Started Jul 11 06:45:57 PM PDT 24
Finished Jul 11 06:46:49 PM PDT 24
Peak memory 257204 kb
Host smart-c628c801-2e00-4547-b47d-093bf736dc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
8290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.363038290
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3800761235
Short name T75
Test name
Test status
Simulation time 1501367670 ps
CPU time 34.47 seconds
Started Jul 11 06:45:56 PM PDT 24
Finished Jul 11 06:46:31 PM PDT 24
Peak memory 249404 kb
Host smart-7f9af013-f56c-41bb-8c6c-110f87ed9df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007
61235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3800761235
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1725918466
Short name T427
Test name
Test status
Simulation time 1919289048 ps
CPU time 61.95 seconds
Started Jul 11 06:45:52 PM PDT 24
Finished Jul 11 06:46:54 PM PDT 24
Peak memory 256960 kb
Host smart-612e52d9-565c-40f4-91c3-fb9e5ba41e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17259
18466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1725918466
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.957608270
Short name T70
Test name
Test status
Simulation time 1435450587 ps
CPU time 43.13 seconds
Started Jul 11 06:45:53 PM PDT 24
Finished Jul 11 06:46:36 PM PDT 24
Peak memory 249328 kb
Host smart-6bf6abbe-5766-4e4c-8d7d-f30b433aba3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95760
8270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.957608270
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1738040362
Short name T285
Test name
Test status
Simulation time 45437647185 ps
CPU time 1624.13 seconds
Started Jul 11 06:45:55 PM PDT 24
Finished Jul 11 07:13:00 PM PDT 24
Peak memory 290372 kb
Host smart-5a305d8e-969f-4157-9c07-05d1fe995838
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738040362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1738040362
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2514983768
Short name T451
Test name
Test status
Simulation time 3746094059 ps
CPU time 247.07 seconds
Started Jul 11 06:46:01 PM PDT 24
Finished Jul 11 06:50:09 PM PDT 24
Peak memory 252760 kb
Host smart-2686e451-76bc-4e78-8bd7-0904d3cfbc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149
83768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2514983768
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.293423230
Short name T701
Test name
Test status
Simulation time 374288470 ps
CPU time 22.08 seconds
Started Jul 11 06:46:01 PM PDT 24
Finished Jul 11 06:46:24 PM PDT 24
Peak memory 256052 kb
Host smart-f656e7cf-816b-4795-a62d-9502c85b6f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
3230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.293423230
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2775809177
Short name T332
Test name
Test status
Simulation time 154286662286 ps
CPU time 2006.31 seconds
Started Jul 11 06:46:08 PM PDT 24
Finished Jul 11 07:19:35 PM PDT 24
Peak memory 273908 kb
Host smart-c2c496f0-e623-4b2e-a761-0391734395d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775809177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2775809177
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2837834232
Short name T412
Test name
Test status
Simulation time 178785921777 ps
CPU time 2826.97 seconds
Started Jul 11 06:46:07 PM PDT 24
Finished Jul 11 07:33:15 PM PDT 24
Peak memory 282088 kb
Host smart-009ee642-775f-4099-b995-e22543ceca5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837834232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2837834232
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.887454809
Short name T323
Test name
Test status
Simulation time 2827927881 ps
CPU time 109.3 seconds
Started Jul 11 06:46:07 PM PDT 24
Finished Jul 11 06:47:57 PM PDT 24
Peak memory 249208 kb
Host smart-1be9edbf-8d65-4beb-ab3d-2eb7c81880c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887454809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.887454809
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2110534215
Short name T396
Test name
Test status
Simulation time 1751020278 ps
CPU time 69.49 seconds
Started Jul 11 06:45:57 PM PDT 24
Finished Jul 11 06:47:08 PM PDT 24
Peak memory 256920 kb
Host smart-23d2c3b9-fbbc-4d24-967f-aa8869ab2da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
34215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2110534215
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.818184554
Short name T680
Test name
Test status
Simulation time 1079078796 ps
CPU time 33.66 seconds
Started Jul 11 06:46:02 PM PDT 24
Finished Jul 11 06:46:36 PM PDT 24
Peak memory 249288 kb
Host smart-dc719c17-daab-48fb-96d1-e8a18aa99458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81818
4554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.818184554
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3205271062
Short name T200
Test name
Test status
Simulation time 514609436 ps
CPU time 37.3 seconds
Started Jul 11 06:45:57 PM PDT 24
Finished Jul 11 06:46:36 PM PDT 24
Peak memory 257368 kb
Host smart-cf0eb0b0-ce52-4a24-93ae-60b5e5f9d268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32052
71062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3205271062
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2163531206
Short name T696
Test name
Test status
Simulation time 183242897117 ps
CPU time 3003.57 seconds
Started Jul 11 06:46:06 PM PDT 24
Finished Jul 11 07:36:11 PM PDT 24
Peak memory 290276 kb
Host smart-bf9f2e90-74d2-4e83-a74c-cecabc26111f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163531206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2163531206
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.412218504
Short name T292
Test name
Test status
Simulation time 49388613802 ps
CPU time 1680.08 seconds
Started Jul 11 06:46:07 PM PDT 24
Finished Jul 11 07:14:08 PM PDT 24
Peak memory 298656 kb
Host smart-76a7669b-536d-4723-8467-a65aad6c9f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412218504 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.412218504
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3315945761
Short name T573
Test name
Test status
Simulation time 157446618300 ps
CPU time 2198.46 seconds
Started Jul 11 06:46:12 PM PDT 24
Finished Jul 11 07:22:52 PM PDT 24
Peak memory 273744 kb
Host smart-5c137081-876f-4a98-a573-0752b4bd8618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315945761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3315945761
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2663019186
Short name T474
Test name
Test status
Simulation time 7696023630 ps
CPU time 212.28 seconds
Started Jul 11 06:46:10 PM PDT 24
Finished Jul 11 06:49:43 PM PDT 24
Peak memory 257620 kb
Host smart-5532c8b7-ade2-4661-9933-6769eec950a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
19186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2663019186
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.926876583
Short name T503
Test name
Test status
Simulation time 1102368618 ps
CPU time 67.12 seconds
Started Jul 11 06:46:10 PM PDT 24
Finished Jul 11 06:47:19 PM PDT 24
Peak memory 256556 kb
Host smart-1e307439-f752-4276-942b-cc7d8fe8da04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92687
6583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.926876583
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4192895337
Short name T216
Test name
Test status
Simulation time 55780685496 ps
CPU time 1264.69 seconds
Started Jul 11 06:46:12 PM PDT 24
Finished Jul 11 07:07:18 PM PDT 24
Peak memory 283364 kb
Host smart-35f70aba-0ad7-4e78-9fcd-5a37a2598ab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192895337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4192895337
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.45949502
Short name T110
Test name
Test status
Simulation time 18797674031 ps
CPU time 1088.99 seconds
Started Jul 11 06:46:12 PM PDT 24
Finished Jul 11 07:04:22 PM PDT 24
Peak memory 289624 kb
Host smart-3971f86f-ed3a-4646-b2fe-a88600b8b9c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45949502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.45949502
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1991698037
Short name T659
Test name
Test status
Simulation time 9332477526 ps
CPU time 193.69 seconds
Started Jul 11 06:46:10 PM PDT 24
Finished Jul 11 06:49:25 PM PDT 24
Peak memory 249196 kb
Host smart-fcb4e766-e2d2-4b27-ab42-496ad9e7609b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991698037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1991698037
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.593065265
Short name T41
Test name
Test status
Simulation time 842111695 ps
CPU time 28.36 seconds
Started Jul 11 06:46:05 PM PDT 24
Finished Jul 11 06:46:34 PM PDT 24
Peak memory 249336 kb
Host smart-d82708ed-ee4d-4132-829c-78b2e3d18ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59306
5265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.593065265
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4110924090
Short name T521
Test name
Test status
Simulation time 606820743 ps
CPU time 44.22 seconds
Started Jul 11 06:46:10 PM PDT 24
Finished Jul 11 06:46:55 PM PDT 24
Peak memory 248704 kb
Host smart-674910f2-549c-45ab-8b56-0bb0e01459b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
24090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4110924090
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1164088818
Short name T387
Test name
Test status
Simulation time 1815864515 ps
CPU time 26.74 seconds
Started Jul 11 06:46:06 PM PDT 24
Finished Jul 11 06:46:34 PM PDT 24
Peak memory 256516 kb
Host smart-0d875ce5-e695-48c5-ac2c-f729f52abcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11640
88818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1164088818
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1588154197
Short name T583
Test name
Test status
Simulation time 69981566376 ps
CPU time 1007.91 seconds
Started Jul 11 06:46:12 PM PDT 24
Finished Jul 11 07:03:01 PM PDT 24
Peak memory 265764 kb
Host smart-7eb9f754-7193-4c91-aef6-af1651b57d88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588154197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1588154197
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3711401254
Short name T649
Test name
Test status
Simulation time 12648261451 ps
CPU time 1159.46 seconds
Started Jul 11 06:46:17 PM PDT 24
Finished Jul 11 07:05:37 PM PDT 24
Peak memory 284172 kb
Host smart-6783260b-00c6-42a9-8247-1f1b3e157020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711401254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3711401254
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1481974528
Short name T567
Test name
Test status
Simulation time 3547877055 ps
CPU time 225.4 seconds
Started Jul 11 06:46:16 PM PDT 24
Finished Jul 11 06:50:02 PM PDT 24
Peak memory 257212 kb
Host smart-5902d0d8-df1a-4d4a-b39d-d0b2d3ac8fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
74528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1481974528
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1527715009
Short name T540
Test name
Test status
Simulation time 1392484633 ps
CPU time 43.19 seconds
Started Jul 11 06:46:15 PM PDT 24
Finished Jul 11 06:46:59 PM PDT 24
Peak memory 249884 kb
Host smart-3e5cc9aa-97fa-4675-8d78-4ac6f24fff67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
15009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1527715009
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3152164951
Short name T338
Test name
Test status
Simulation time 31229027208 ps
CPU time 2255.6 seconds
Started Jul 11 06:46:16 PM PDT 24
Finished Jul 11 07:23:52 PM PDT 24
Peak memory 282212 kb
Host smart-6b5ce20e-5dc6-4d5a-83cc-8fcd0ee1a22f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152164951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3152164951
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.6898542
Short name T679
Test name
Test status
Simulation time 70390627717 ps
CPU time 2634.17 seconds
Started Jul 11 06:46:21 PM PDT 24
Finished Jul 11 07:30:16 PM PDT 24
Peak memory 290136 kb
Host smart-8c3c846a-0d4b-401e-9193-733939855073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6898542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.6898542
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.50732298
Short name T328
Test name
Test status
Simulation time 50155830690 ps
CPU time 434.08 seconds
Started Jul 11 06:46:16 PM PDT 24
Finished Jul 11 06:53:31 PM PDT 24
Peak memory 249360 kb
Host smart-0e6b6886-9435-4b08-91cc-3be660190674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50732298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.50732298
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.497249285
Short name T677
Test name
Test status
Simulation time 3542291324 ps
CPU time 53.7 seconds
Started Jul 11 06:46:11 PM PDT 24
Finished Jul 11 06:47:06 PM PDT 24
Peak memory 256912 kb
Host smart-2230d29e-fbee-4324-86be-3df53978c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49724
9285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.497249285
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2534145494
Short name T27
Test name
Test status
Simulation time 165495718 ps
CPU time 25.38 seconds
Started Jul 11 06:46:16 PM PDT 24
Finished Jul 11 06:46:42 PM PDT 24
Peak memory 249088 kb
Host smart-abe37426-7b3a-4f8a-a094-d004c6755f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25341
45494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2534145494
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.315702045
Short name T617
Test name
Test status
Simulation time 3286465951 ps
CPU time 30.58 seconds
Started Jul 11 06:46:15 PM PDT 24
Finished Jul 11 06:46:46 PM PDT 24
Peak memory 248984 kb
Host smart-0cd60ac4-c369-4574-bd88-79d5c3c81701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570
2045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.315702045
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1790751004
Short name T528
Test name
Test status
Simulation time 687360649 ps
CPU time 26.11 seconds
Started Jul 11 06:46:11 PM PDT 24
Finished Jul 11 06:46:38 PM PDT 24
Peak memory 249300 kb
Host smart-3a856cfc-74e6-4ef2-b7bf-5393ccf17821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17907
51004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1790751004
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.870465893
Short name T88
Test name
Test status
Simulation time 16833770034 ps
CPU time 1512.05 seconds
Started Jul 11 06:46:20 PM PDT 24
Finished Jul 11 07:11:33 PM PDT 24
Peak memory 289588 kb
Host smart-7e2a3c23-2358-4bed-957f-8a44e568ed9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870465893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.870465893
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3269631783
Short name T653
Test name
Test status
Simulation time 359007680497 ps
CPU time 9620.36 seconds
Started Jul 11 06:46:20 PM PDT 24
Finished Jul 11 09:26:42 PM PDT 24
Peak memory 387808 kb
Host smart-813d6ff0-7730-4d00-883b-7b6d8b4a91df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269631783 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3269631783
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3747746740
Short name T55
Test name
Test status
Simulation time 43108427762 ps
CPU time 2304.82 seconds
Started Jul 11 06:46:21 PM PDT 24
Finished Jul 11 07:24:47 PM PDT 24
Peak memory 289776 kb
Host smart-1e45a5b0-5ee7-48e7-acab-767eda7dad1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747746740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3747746740
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3984424319
Short name T42
Test name
Test status
Simulation time 1365752489 ps
CPU time 134.35 seconds
Started Jul 11 06:46:21 PM PDT 24
Finished Jul 11 06:48:36 PM PDT 24
Peak memory 257512 kb
Host smart-965205e5-3587-4abc-ae06-bcb5a1aea26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39844
24319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3984424319
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1124629742
Short name T78
Test name
Test status
Simulation time 5751260647 ps
CPU time 52.09 seconds
Started Jul 11 06:46:20 PM PDT 24
Finished Jul 11 06:47:12 PM PDT 24
Peak memory 256716 kb
Host smart-d45c80ef-f0db-478c-bec8-6ccb5781910b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246
29742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1124629742
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.4278772364
Short name T331
Test name
Test status
Simulation time 12492907323 ps
CPU time 1286.83 seconds
Started Jul 11 06:46:24 PM PDT 24
Finished Jul 11 07:07:51 PM PDT 24
Peak memory 289472 kb
Host smart-8f914848-5d8c-4649-b8a5-942cc0410630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278772364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.4278772364
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3963397608
Short name T472
Test name
Test status
Simulation time 32106568704 ps
CPU time 2004.37 seconds
Started Jul 11 06:46:26 PM PDT 24
Finished Jul 11 07:19:52 PM PDT 24
Peak memory 289372 kb
Host smart-adae6fd6-ef1c-479b-83d2-7544f440c966
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963397608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3963397608
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.264743973
Short name T31
Test name
Test status
Simulation time 216907108 ps
CPU time 24.93 seconds
Started Jul 11 06:46:20 PM PDT 24
Finished Jul 11 06:46:46 PM PDT 24
Peak memory 249428 kb
Host smart-ab4377df-f6df-485b-bf23-6b5107d28468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26474
3973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.264743973
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1995409995
Short name T118
Test name
Test status
Simulation time 247971703 ps
CPU time 19.25 seconds
Started Jul 11 06:46:22 PM PDT 24
Finished Jul 11 06:46:42 PM PDT 24
Peak memory 248804 kb
Host smart-8be686aa-8a1b-45e6-a160-884e2ab0d2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19954
09995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1995409995
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.452471340
Short name T244
Test name
Test status
Simulation time 306686254 ps
CPU time 24.07 seconds
Started Jul 11 06:46:22 PM PDT 24
Finished Jul 11 06:46:47 PM PDT 24
Peak memory 256992 kb
Host smart-b1f0d742-40cc-43d0-b017-1217675d79a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45247
1340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.452471340
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1720729199
Short name T91
Test name
Test status
Simulation time 2280532903 ps
CPU time 68.13 seconds
Started Jul 11 06:46:20 PM PDT 24
Finished Jul 11 06:47:28 PM PDT 24
Peak memory 257272 kb
Host smart-0f483df8-1959-4b53-a9a2-da137f6a98f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17207
29199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1720729199
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2216524507
Short name T276
Test name
Test status
Simulation time 70775596308 ps
CPU time 1563.8 seconds
Started Jul 11 06:46:26 PM PDT 24
Finished Jul 11 07:12:31 PM PDT 24
Peak memory 290264 kb
Host smart-c600279b-698b-49fb-a8fc-95fa3de3d0e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216524507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2216524507
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.49626573
Short name T108
Test name
Test status
Simulation time 59286072022 ps
CPU time 1720.06 seconds
Started Jul 11 06:46:35 PM PDT 24
Finished Jul 11 07:15:16 PM PDT 24
Peak memory 289828 kb
Host smart-75670ba7-547d-47c3-8b7a-ebf3c725cde7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49626573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.49626573
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1859576601
Short name T3
Test name
Test status
Simulation time 1364097051 ps
CPU time 40.2 seconds
Started Jul 11 06:46:28 PM PDT 24
Finished Jul 11 06:47:09 PM PDT 24
Peak memory 256524 kb
Host smart-94ad1d32-04da-4e7e-a739-8b641e7e0ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18595
76601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1859576601
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2116408354
Short name T478
Test name
Test status
Simulation time 384157391 ps
CPU time 32.68 seconds
Started Jul 11 06:46:25 PM PDT 24
Finished Jul 11 06:46:59 PM PDT 24
Peak memory 249900 kb
Host smart-a15b260e-2446-49de-8f23-1aef4a9f37d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21164
08354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2116408354
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2240118732
Short name T514
Test name
Test status
Simulation time 151069861128 ps
CPU time 2368.36 seconds
Started Jul 11 06:46:35 PM PDT 24
Finished Jul 11 07:26:04 PM PDT 24
Peak memory 290360 kb
Host smart-9785e904-b517-474a-a11d-f5da5bd9b766
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240118732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2240118732
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1523470744
Short name T571
Test name
Test status
Simulation time 53655368215 ps
CPU time 1157.63 seconds
Started Jul 11 06:46:37 PM PDT 24
Finished Jul 11 07:05:55 PM PDT 24
Peak memory 282096 kb
Host smart-492c7c13-17e0-4160-aa67-0d151d891b8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523470744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1523470744
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.314681870
Short name T609
Test name
Test status
Simulation time 17455322795 ps
CPU time 202.54 seconds
Started Jul 11 06:46:36 PM PDT 24
Finished Jul 11 06:49:59 PM PDT 24
Peak memory 249572 kb
Host smart-fd314364-9132-4eb4-a528-baf88e30716e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314681870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.314681870
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2319926226
Short name T59
Test name
Test status
Simulation time 600505324 ps
CPU time 28.89 seconds
Started Jul 11 06:46:25 PM PDT 24
Finished Jul 11 06:46:55 PM PDT 24
Peak memory 249332 kb
Host smart-ad39b3c1-cd13-4dd0-9630-19fed07e4573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23199
26226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2319926226
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.452616509
Short name T604
Test name
Test status
Simulation time 583820481 ps
CPU time 41.41 seconds
Started Jul 11 06:46:25 PM PDT 24
Finished Jul 11 06:47:08 PM PDT 24
Peak memory 256672 kb
Host smart-2ef51168-9739-4a3d-8f10-ae492f355698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45261
6509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.452616509
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1616375864
Short name T48
Test name
Test status
Simulation time 1180211740 ps
CPU time 20.69 seconds
Started Jul 11 06:46:30 PM PDT 24
Finished Jul 11 06:46:51 PM PDT 24
Peak memory 248544 kb
Host smart-1b313f15-c6b9-455e-bec8-6aa6efa82c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
75864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1616375864
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4110163787
Short name T28
Test name
Test status
Simulation time 261959639 ps
CPU time 28.7 seconds
Started Jul 11 06:46:25 PM PDT 24
Finished Jul 11 06:46:55 PM PDT 24
Peak memory 256544 kb
Host smart-3c7201e9-be88-49a9-9bb2-2465971c5624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41101
63787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4110163787
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.556927752
Short name T440
Test name
Test status
Simulation time 309495862704 ps
CPU time 2273.03 seconds
Started Jul 11 06:46:39 PM PDT 24
Finished Jul 11 07:24:33 PM PDT 24
Peak memory 288308 kb
Host smart-454c274f-adea-4ef3-82be-949e3f98e51e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556927752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.556927752
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3939630624
Short name T17
Test name
Test status
Simulation time 50015004644 ps
CPU time 1221.98 seconds
Started Jul 11 06:46:50 PM PDT 24
Finished Jul 11 07:07:13 PM PDT 24
Peak memory 274092 kb
Host smart-929068a7-9dc9-4146-b333-40968dbbd3bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939630624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3939630624
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3420059116
Short name T601
Test name
Test status
Simulation time 4436410949 ps
CPU time 256.91 seconds
Started Jul 11 06:46:45 PM PDT 24
Finished Jul 11 06:51:02 PM PDT 24
Peak memory 257172 kb
Host smart-dbd0075f-35a5-462e-b9f9-ada5aaaf237b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
59116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3420059116
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1741764787
Short name T73
Test name
Test status
Simulation time 5276320870 ps
CPU time 37.67 seconds
Started Jul 11 06:46:39 PM PDT 24
Finished Jul 11 06:47:17 PM PDT 24
Peak memory 248772 kb
Host smart-fe5647e7-b811-4397-8671-37a1176d2048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
64787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1741764787
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1003591402
Short name T340
Test name
Test status
Simulation time 64379569737 ps
CPU time 974.18 seconds
Started Jul 11 06:46:49 PM PDT 24
Finished Jul 11 07:03:04 PM PDT 24
Peak memory 283344 kb
Host smart-c9e53bac-8808-4e35-924b-31480461f11e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003591402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1003591402
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2209829772
Short name T684
Test name
Test status
Simulation time 97132106742 ps
CPU time 1624.39 seconds
Started Jul 11 06:46:49 PM PDT 24
Finished Jul 11 07:13:55 PM PDT 24
Peak memory 273988 kb
Host smart-199adcd2-950e-46d8-ab75-9bba8ce16336
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209829772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2209829772
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1154274738
Short name T131
Test name
Test status
Simulation time 104250877 ps
CPU time 13.57 seconds
Started Jul 11 06:47:05 PM PDT 24
Finished Jul 11 06:47:20 PM PDT 24
Peak memory 249208 kb
Host smart-432e2e6e-299b-449e-a150-2cc29a2c2cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542
74738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1154274738
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3993776571
Short name T662
Test name
Test status
Simulation time 248667601 ps
CPU time 8.41 seconds
Started Jul 11 06:46:40 PM PDT 24
Finished Jul 11 06:46:49 PM PDT 24
Peak memory 252324 kb
Host smart-ba27056f-517c-480c-9183-59c06d930b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39937
76571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3993776571
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3635591408
Short name T594
Test name
Test status
Simulation time 51245588 ps
CPU time 5.15 seconds
Started Jul 11 06:46:43 PM PDT 24
Finished Jul 11 06:46:49 PM PDT 24
Peak memory 240620 kb
Host smart-e63fec84-5e09-4e3c-a0ab-847431fc7f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
91408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3635591408
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.4252862762
Short name T605
Test name
Test status
Simulation time 935609139 ps
CPU time 31.04 seconds
Started Jul 11 06:46:40 PM PDT 24
Finished Jul 11 06:47:11 PM PDT 24
Peak memory 249320 kb
Host smart-d098dbfa-cc2a-4e46-a961-9b3da845b8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42528
62762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.4252862762
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2250041480
Short name T467
Test name
Test status
Simulation time 3291555787 ps
CPU time 125.77 seconds
Started Jul 11 06:46:54 PM PDT 24
Finished Jul 11 06:49:00 PM PDT 24
Peak memory 257616 kb
Host smart-a89b090b-2e39-47b6-9eaa-5d6a17bd93e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
41480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2250041480
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1704845903
Short name T198
Test name
Test status
Simulation time 538028411 ps
CPU time 32.26 seconds
Started Jul 11 06:46:52 PM PDT 24
Finished Jul 11 06:47:25 PM PDT 24
Peak memory 256692 kb
Host smart-11116a7f-b9bb-4205-91ac-1ce666b1c0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
45903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1704845903
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2352286445
Short name T516
Test name
Test status
Simulation time 111299154950 ps
CPU time 1325.31 seconds
Started Jul 11 06:46:57 PM PDT 24
Finished Jul 11 07:09:03 PM PDT 24
Peak memory 289804 kb
Host smart-d63670a1-9025-4af7-b004-26f7d9189674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352286445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2352286445
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1248601230
Short name T625
Test name
Test status
Simulation time 8841906912 ps
CPU time 388.23 seconds
Started Jul 11 06:46:57 PM PDT 24
Finished Jul 11 06:53:25 PM PDT 24
Peak memory 249240 kb
Host smart-e59c660f-bf3d-423c-8e5c-d427766c43fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248601230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1248601230
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3845106372
Short name T621
Test name
Test status
Simulation time 6269231818 ps
CPU time 61.77 seconds
Started Jul 11 06:46:56 PM PDT 24
Finished Jul 11 06:47:58 PM PDT 24
Peak memory 256656 kb
Host smart-85b0ccec-e0d2-4fde-9fdd-975363b8b3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
06372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3845106372
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4254902517
Short name T613
Test name
Test status
Simulation time 621552566 ps
CPU time 36.96 seconds
Started Jul 11 06:46:54 PM PDT 24
Finished Jul 11 06:47:32 PM PDT 24
Peak memory 249336 kb
Host smart-603feeb2-1f5f-432e-bd4b-f85a5b010739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549
02517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4254902517
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3009291427
Short name T490
Test name
Test status
Simulation time 5193976401 ps
CPU time 18.79 seconds
Started Jul 11 06:46:53 PM PDT 24
Finished Jul 11 06:47:12 PM PDT 24
Peak memory 255448 kb
Host smart-3c3d03f9-d824-439f-97da-22f8946fedeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30092
91427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3009291427
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2149128271
Short name T62
Test name
Test status
Simulation time 168790598697 ps
CPU time 4779.75 seconds
Started Jul 11 06:47:03 PM PDT 24
Finished Jul 11 08:06:44 PM PDT 24
Peak memory 339068 kb
Host smart-ec64d2ce-bdb3-4ade-b059-09bda5f84900
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149128271 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2149128271
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.198323303
Short name T477
Test name
Test status
Simulation time 7175432911 ps
CPU time 189.5 seconds
Started Jul 11 06:47:01 PM PDT 24
Finished Jul 11 06:50:12 PM PDT 24
Peak memory 257620 kb
Host smart-2c50edd4-cd03-4675-bc8a-ef33659cdc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19832
3303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.198323303
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1584857613
Short name T505
Test name
Test status
Simulation time 344597548 ps
CPU time 31.92 seconds
Started Jul 11 06:47:01 PM PDT 24
Finished Jul 11 06:47:34 PM PDT 24
Peak memory 248848 kb
Host smart-c14807c8-5868-4803-b8db-a11f60906631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15848
57613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1584857613
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3450661623
Short name T199
Test name
Test status
Simulation time 53484206146 ps
CPU time 1770.61 seconds
Started Jul 11 06:47:07 PM PDT 24
Finished Jul 11 07:16:39 PM PDT 24
Peak memory 273940 kb
Host smart-f547bdad-ff8b-4dc6-95ea-b4affb804e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450661623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3450661623
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2987304749
Short name T524
Test name
Test status
Simulation time 43997912080 ps
CPU time 1995.6 seconds
Started Jul 11 06:47:12 PM PDT 24
Finished Jul 11 07:20:28 PM PDT 24
Peak memory 289492 kb
Host smart-b1787477-dc33-4974-b92f-67396cf289d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987304749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2987304749
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2389789356
Short name T543
Test name
Test status
Simulation time 2479547783 ps
CPU time 41.54 seconds
Started Jul 11 06:47:02 PM PDT 24
Finished Jul 11 06:47:45 PM PDT 24
Peak memory 256764 kb
Host smart-dba9c262-f049-4ba7-b6cb-5e7e433ff924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23897
89356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2389789356
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3890117636
Short name T51
Test name
Test status
Simulation time 969033319 ps
CPU time 16.78 seconds
Started Jul 11 06:47:01 PM PDT 24
Finished Jul 11 06:47:19 PM PDT 24
Peak memory 254536 kb
Host smart-29185bcb-d17f-459a-a148-30bad85ac06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901
17636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3890117636
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.82044701
Short name T206
Test name
Test status
Simulation time 701381247 ps
CPU time 15.74 seconds
Started Jul 11 06:47:04 PM PDT 24
Finished Jul 11 06:47:21 PM PDT 24
Peak memory 255192 kb
Host smart-c92339f8-d93f-49d4-84c6-7f56e8969bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82044
701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.82044701
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.925613564
Short name T391
Test name
Test status
Simulation time 203087767 ps
CPU time 29.85 seconds
Started Jul 11 06:47:02 PM PDT 24
Finished Jul 11 06:47:33 PM PDT 24
Peak memory 257476 kb
Host smart-25afaba1-f9ac-41f9-8f15-1290807b0bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92561
3564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.925613564
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.762081475
Short name T261
Test name
Test status
Simulation time 5289216705 ps
CPU time 130.21 seconds
Started Jul 11 06:47:10 PM PDT 24
Finished Jul 11 06:49:21 PM PDT 24
Peak memory 257652 kb
Host smart-3ada5784-3037-4d3b-8a0a-36ff4dab025e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762081475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.762081475
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.361031353
Short name T226
Test name
Test status
Simulation time 57782658 ps
CPU time 3.38 seconds
Started Jul 11 06:44:19 PM PDT 24
Finished Jul 11 06:44:24 PM PDT 24
Peak memory 249576 kb
Host smart-eac7b164-424c-486c-a9ca-4d9b265b68ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=361031353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.361031353
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.481056070
Short name T303
Test name
Test status
Simulation time 5410730551 ps
CPU time 655.31 seconds
Started Jul 11 06:44:21 PM PDT 24
Finished Jul 11 06:55:18 PM PDT 24
Peak memory 273480 kb
Host smart-1db6aac2-c36f-44f8-96b5-f7c57921a95d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481056070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.481056070
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3153855220
Short name T454
Test name
Test status
Simulation time 895942994 ps
CPU time 6.61 seconds
Started Jul 11 06:44:19 PM PDT 24
Finished Jul 11 06:44:27 PM PDT 24
Peak memory 249312 kb
Host smart-05ea1cab-afde-411d-ab92-5bb42df3f54b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3153855220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3153855220
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2252804379
Short name T568
Test name
Test status
Simulation time 2658348453 ps
CPU time 75.48 seconds
Started Jul 11 06:44:19 PM PDT 24
Finished Jul 11 06:45:36 PM PDT 24
Peak memory 257168 kb
Host smart-7b65766e-cde1-4d32-b658-a6f56800fb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22528
04379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2252804379
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2826987473
Short name T344
Test name
Test status
Simulation time 27187950085 ps
CPU time 927.1 seconds
Started Jul 11 06:44:21 PM PDT 24
Finished Jul 11 06:59:50 PM PDT 24
Peak memory 273884 kb
Host smart-cfa70407-afb8-46ef-867c-33f102d103f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826987473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2826987473
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.335234573
Short name T289
Test name
Test status
Simulation time 8844087709 ps
CPU time 1138.22 seconds
Started Jul 11 06:44:20 PM PDT 24
Finished Jul 11 07:03:20 PM PDT 24
Peak memory 273956 kb
Host smart-6c09eb1e-8595-4d6e-909b-87f1ed5ebae7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335234573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.335234573
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2314198236
Short name T196
Test name
Test status
Simulation time 47245880245 ps
CPU time 459.84 seconds
Started Jul 11 06:44:18 PM PDT 24
Finished Jul 11 06:52:00 PM PDT 24
Peak memory 256140 kb
Host smart-9b54b34d-1356-47a4-97cf-d4c51cd7615d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314198236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2314198236
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1598064736
Short name T619
Test name
Test status
Simulation time 529272888 ps
CPU time 23.54 seconds
Started Jul 11 06:44:16 PM PDT 24
Finished Jul 11 06:44:41 PM PDT 24
Peak memory 249260 kb
Host smart-b399fe32-bcb3-4833-8250-568f3517a1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
64736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1598064736
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.538926353
Short name T537
Test name
Test status
Simulation time 121344842 ps
CPU time 8.78 seconds
Started Jul 11 06:44:21 PM PDT 24
Finished Jul 11 06:44:31 PM PDT 24
Peak memory 248708 kb
Host smart-6d37020e-5da8-4c18-ba03-43fba3a576e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53892
6353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.538926353
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1851307519
Short name T37
Test name
Test status
Simulation time 1125861420 ps
CPU time 52.1 seconds
Started Jul 11 06:44:20 PM PDT 24
Finished Jul 11 06:45:14 PM PDT 24
Peak memory 278116 kb
Host smart-1c9070dd-8a9f-415b-98c6-bea2e13b6f1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1851307519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1851307519
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1314339169
Short name T522
Test name
Test status
Simulation time 286008571 ps
CPU time 20.31 seconds
Started Jul 11 06:44:20 PM PDT 24
Finished Jul 11 06:44:42 PM PDT 24
Peak memory 257088 kb
Host smart-ed1b58ff-dbe4-4b91-9eda-b45fd80b9cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13143
39169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1314339169
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3611694683
Short name T703
Test name
Test status
Simulation time 64123302711 ps
CPU time 2223.37 seconds
Started Jul 11 06:44:22 PM PDT 24
Finished Jul 11 07:21:27 PM PDT 24
Peak memory 305556 kb
Host smart-ba80688b-662e-437c-a0d8-ab48a54f7fe1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611694683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3611694683
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1380758829
Short name T575
Test name
Test status
Simulation time 64426405867 ps
CPU time 1381.14 seconds
Started Jul 11 06:47:13 PM PDT 24
Finished Jul 11 07:10:16 PM PDT 24
Peak memory 290176 kb
Host smart-f2c350f7-76c3-4509-ab69-4cd48363c20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380758829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1380758829
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3042913709
Short name T496
Test name
Test status
Simulation time 2847795695 ps
CPU time 83.19 seconds
Started Jul 11 06:47:14 PM PDT 24
Finished Jul 11 06:48:38 PM PDT 24
Peak memory 250496 kb
Host smart-391db778-d132-4f76-ac05-0cbd00b40f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30429
13709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3042913709
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1981416237
Short name T517
Test name
Test status
Simulation time 1232760750 ps
CPU time 60.53 seconds
Started Jul 11 06:47:10 PM PDT 24
Finished Jul 11 06:48:11 PM PDT 24
Peak memory 257004 kb
Host smart-230e63d6-51a0-4137-997b-3230378be75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19814
16237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1981416237
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1113388980
Short name T112
Test name
Test status
Simulation time 53333104219 ps
CPU time 1157.65 seconds
Started Jul 11 06:47:21 PM PDT 24
Finished Jul 11 07:06:40 PM PDT 24
Peak memory 273348 kb
Host smart-33953998-2086-4b15-948e-81d89db6db43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113388980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1113388980
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2335081322
Short name T242
Test name
Test status
Simulation time 29111354998 ps
CPU time 1506.92 seconds
Started Jul 11 06:47:19 PM PDT 24
Finished Jul 11 07:12:27 PM PDT 24
Peak memory 273756 kb
Host smart-59bbb274-4725-4af8-b11b-8a088a7271b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335081322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2335081322
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3113740826
Short name T326
Test name
Test status
Simulation time 20800794244 ps
CPU time 450.35 seconds
Started Jul 11 06:47:18 PM PDT 24
Finished Jul 11 06:54:49 PM PDT 24
Peak memory 248276 kb
Host smart-8b73f130-9bd1-415f-bc6a-cc54d6ead6ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113740826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3113740826
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4026794096
Short name T433
Test name
Test status
Simulation time 1061962017 ps
CPU time 31.22 seconds
Started Jul 11 06:47:11 PM PDT 24
Finished Jul 11 06:47:43 PM PDT 24
Peak memory 249336 kb
Host smart-200796f0-012d-4e1f-9de9-ffe0b4dd1fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40267
94096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4026794096
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1394428515
Short name T439
Test name
Test status
Simulation time 1250383444 ps
CPU time 44.36 seconds
Started Jul 11 06:47:09 PM PDT 24
Finished Jul 11 06:47:54 PM PDT 24
Peak memory 256996 kb
Host smart-2d986417-dd09-45a5-923a-50d362e36492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13944
28515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1394428515
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3232261105
Short name T402
Test name
Test status
Simulation time 2942297617 ps
CPU time 51.09 seconds
Started Jul 11 06:47:14 PM PDT 24
Finished Jul 11 06:48:06 PM PDT 24
Peak memory 257140 kb
Host smart-1aa38345-10ba-4bc4-aaeb-2b781d8f0bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32322
61105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3232261105
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.155717615
Short name T369
Test name
Test status
Simulation time 3185309741 ps
CPU time 51.8 seconds
Started Jul 11 06:47:09 PM PDT 24
Finished Jul 11 06:48:02 PM PDT 24
Peak memory 257540 kb
Host smart-827be223-e2f4-4aae-8afb-65bb33fad5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15571
7615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.155717615
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.420408072
Short name T111
Test name
Test status
Simulation time 101339659585 ps
CPU time 1824.3 seconds
Started Jul 11 06:47:27 PM PDT 24
Finished Jul 11 07:17:52 PM PDT 24
Peak memory 290344 kb
Host smart-1e092b1d-f839-4068-a232-a551e363d98e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420408072 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.420408072
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2799499753
Short name T400
Test name
Test status
Simulation time 42013103721 ps
CPU time 2574.77 seconds
Started Jul 11 06:47:25 PM PDT 24
Finished Jul 11 07:30:21 PM PDT 24
Peak memory 286100 kb
Host smart-6d70d011-efd5-466b-b731-db053134757f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799499753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2799499753
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3645767762
Short name T197
Test name
Test status
Simulation time 10735159549 ps
CPU time 208.27 seconds
Started Jul 11 06:47:24 PM PDT 24
Finished Jul 11 06:50:52 PM PDT 24
Peak memory 257084 kb
Host smart-c53ab76b-75e0-4cbc-93f9-cfd6022c0c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36457
67762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3645767762
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.343384432
Short name T475
Test name
Test status
Simulation time 546603951 ps
CPU time 15.75 seconds
Started Jul 11 06:47:24 PM PDT 24
Finished Jul 11 06:47:41 PM PDT 24
Peak memory 249252 kb
Host smart-085795c7-ea98-40e4-a522-086fc55ff62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34338
4432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.343384432
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1052437198
Short name T329
Test name
Test status
Simulation time 53876547529 ps
CPU time 1650.16 seconds
Started Jul 11 06:47:21 PM PDT 24
Finished Jul 11 07:14:52 PM PDT 24
Peak memory 273056 kb
Host smart-9a40e289-4f17-4eaf-af66-1c192e843e52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052437198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1052437198
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3146352466
Short name T296
Test name
Test status
Simulation time 231741577489 ps
CPU time 3448.35 seconds
Started Jul 11 06:47:22 PM PDT 24
Finished Jul 11 07:44:51 PM PDT 24
Peak memory 289576 kb
Host smart-15a89dd1-6273-4ec2-a4c0-a02f34df6166
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146352466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3146352466
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4137617171
Short name T313
Test name
Test status
Simulation time 11758103291 ps
CPU time 343.31 seconds
Started Jul 11 06:47:27 PM PDT 24
Finished Jul 11 06:53:11 PM PDT 24
Peak memory 256572 kb
Host smart-71578338-e524-4299-be7b-4fa67cacf848
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137617171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4137617171
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.349163501
Short name T463
Test name
Test status
Simulation time 25264455 ps
CPU time 3.43 seconds
Started Jul 11 06:47:21 PM PDT 24
Finished Jul 11 06:47:25 PM PDT 24
Peak memory 249244 kb
Host smart-3a176310-5b1e-4fb6-a0d0-71710d6fb793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
3501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.349163501
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1572023741
Short name T50
Test name
Test status
Simulation time 192881543 ps
CPU time 24.42 seconds
Started Jul 11 06:47:25 PM PDT 24
Finished Jul 11 06:47:50 PM PDT 24
Peak memory 249136 kb
Host smart-d024ee8b-1599-4bd4-a782-4f3610d69337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15720
23741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1572023741
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1782355051
Short name T485
Test name
Test status
Simulation time 1773770044 ps
CPU time 40.99 seconds
Started Jul 11 06:47:23 PM PDT 24
Finished Jul 11 06:48:04 PM PDT 24
Peak memory 257088 kb
Host smart-cbe3aac6-c078-4d0d-8341-dbb34fb709c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17823
55051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1782355051
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3457216634
Short name T420
Test name
Test status
Simulation time 1185453400 ps
CPU time 18.93 seconds
Started Jul 11 06:47:24 PM PDT 24
Finished Jul 11 06:47:44 PM PDT 24
Peak memory 255660 kb
Host smart-b54c0edc-5807-4c46-86ec-e4c09fa23fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34572
16634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3457216634
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.558274886
Short name T76
Test name
Test status
Simulation time 447101632 ps
CPU time 23.18 seconds
Started Jul 11 06:47:30 PM PDT 24
Finished Jul 11 06:47:54 PM PDT 24
Peak memory 256600 kb
Host smart-e063edb0-9eec-46c2-8298-380c59d0a76b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558274886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.558274886
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3871558642
Short name T121
Test name
Test status
Simulation time 15255740483 ps
CPU time 1136.16 seconds
Started Jul 11 06:47:28 PM PDT 24
Finished Jul 11 07:06:25 PM PDT 24
Peak memory 273380 kb
Host smart-5bd08e85-d19f-4e0e-9bcd-b19801f59471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871558642 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3871558642
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.846652549
Short name T501
Test name
Test status
Simulation time 4139879918 ps
CPU time 33.33 seconds
Started Jul 11 06:47:31 PM PDT 24
Finished Jul 11 06:48:05 PM PDT 24
Peak memory 248912 kb
Host smart-c711a0ed-3c5f-4b15-9a9f-b1ab9db3ebe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84665
2549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.846652549
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2169383258
Short name T698
Test name
Test status
Simulation time 1384596029 ps
CPU time 35.92 seconds
Started Jul 11 06:47:33 PM PDT 24
Finished Jul 11 06:48:09 PM PDT 24
Peak memory 256816 kb
Host smart-cd5c159b-f8d7-4763-928b-d96c57fea5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
83258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2169383258
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1951380231
Short name T44
Test name
Test status
Simulation time 31745906745 ps
CPU time 1878.18 seconds
Started Jul 11 06:47:36 PM PDT 24
Finished Jul 11 07:18:55 PM PDT 24
Peak memory 273240 kb
Host smart-aa639db0-ed14-48dd-b85b-81216869840c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951380231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1951380231
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1091763042
Short name T211
Test name
Test status
Simulation time 18407041446 ps
CPU time 588.67 seconds
Started Jul 11 06:47:37 PM PDT 24
Finished Jul 11 06:57:26 PM PDT 24
Peak memory 265816 kb
Host smart-caaa850f-f5df-49a1-946a-62d6af42be86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091763042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1091763042
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1496471612
Short name T658
Test name
Test status
Simulation time 66470632834 ps
CPU time 606.54 seconds
Started Jul 11 06:47:37 PM PDT 24
Finished Jul 11 06:57:44 PM PDT 24
Peak memory 255136 kb
Host smart-fdbfb6f6-0bcc-436f-9518-cf07f679efb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496471612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1496471612
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1700680374
Short name T484
Test name
Test status
Simulation time 1083302276 ps
CPU time 61.57 seconds
Started Jul 11 06:47:28 PM PDT 24
Finished Jul 11 06:48:31 PM PDT 24
Peak memory 256628 kb
Host smart-1f97cde5-311d-4c4d-94c3-1ac573c39ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17006
80374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1700680374
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2327584769
Short name T380
Test name
Test status
Simulation time 114445257 ps
CPU time 11.28 seconds
Started Jul 11 06:47:32 PM PDT 24
Finished Jul 11 06:47:44 PM PDT 24
Peak memory 248636 kb
Host smart-30e68445-9b04-48e4-bb30-e478d1048f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23275
84769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2327584769
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1020436620
Short name T502
Test name
Test status
Simulation time 21494758055 ps
CPU time 79.92 seconds
Started Jul 11 06:47:30 PM PDT 24
Finished Jul 11 06:48:51 PM PDT 24
Peak memory 257516 kb
Host smart-27f06e79-f94f-48f9-aa46-7c073dcaae71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
36620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1020436620
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3053298771
Short name T539
Test name
Test status
Simulation time 6716552618 ps
CPU time 287.42 seconds
Started Jul 11 06:47:42 PM PDT 24
Finished Jul 11 06:52:30 PM PDT 24
Peak memory 257612 kb
Host smart-ac445ec0-1912-46ef-b9bb-13d68eb7ba37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053298771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3053298771
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3695805307
Short name T97
Test name
Test status
Simulation time 39746227822 ps
CPU time 4690.7 seconds
Started Jul 11 06:47:43 PM PDT 24
Finished Jul 11 08:05:55 PM PDT 24
Peak memory 322388 kb
Host smart-2b0aac15-816d-4499-8918-54f0cc6f0fa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695805307 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3695805307
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1207694302
Short name T394
Test name
Test status
Simulation time 13753180453 ps
CPU time 741.75 seconds
Started Jul 11 06:47:47 PM PDT 24
Finished Jul 11 07:00:09 PM PDT 24
Peak memory 265820 kb
Host smart-adc52906-597d-4a10-8dfc-8851b0de5d89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207694302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1207694302
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.676524741
Short name T686
Test name
Test status
Simulation time 1114071267 ps
CPU time 71.72 seconds
Started Jul 11 06:47:46 PM PDT 24
Finished Jul 11 06:48:59 PM PDT 24
Peak memory 249296 kb
Host smart-5b0b483f-355e-453c-a04a-bfe2abdd23ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67652
4741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.676524741
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3185648916
Short name T406
Test name
Test status
Simulation time 311447881 ps
CPU time 30.6 seconds
Started Jul 11 06:47:46 PM PDT 24
Finished Jul 11 06:48:17 PM PDT 24
Peak memory 249852 kb
Host smart-f95ef7e9-5d5b-4359-98d1-1f2d3d5168c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31856
48916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3185648916
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1255424422
Short name T576
Test name
Test status
Simulation time 16951341415 ps
CPU time 1536.6 seconds
Started Jul 11 06:47:51 PM PDT 24
Finished Jul 11 07:13:29 PM PDT 24
Peak memory 282208 kb
Host smart-87b81bba-53fa-410e-987b-31cd75eef109
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255424422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1255424422
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1431526684
Short name T642
Test name
Test status
Simulation time 28849743132 ps
CPU time 1372.03 seconds
Started Jul 11 06:47:55 PM PDT 24
Finished Jul 11 07:10:48 PM PDT 24
Peak memory 289416 kb
Host smart-ca00ba78-23c1-42ba-98a1-a7915a02f3bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431526684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1431526684
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2342394119
Short name T581
Test name
Test status
Simulation time 9507926611 ps
CPU time 234.51 seconds
Started Jul 11 06:47:51 PM PDT 24
Finished Jul 11 06:51:45 PM PDT 24
Peak memory 249400 kb
Host smart-523f2c7a-2737-44fb-b2b7-eeffc3db8931
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342394119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2342394119
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2872501541
Short name T633
Test name
Test status
Simulation time 3218918627 ps
CPU time 48.05 seconds
Started Jul 11 06:47:42 PM PDT 24
Finished Jul 11 06:48:30 PM PDT 24
Peak memory 256904 kb
Host smart-cfdf2644-ca4e-4f60-ab12-d9d4fedbdd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
01541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2872501541
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.230674693
Short name T623
Test name
Test status
Simulation time 900502879 ps
CPU time 30.39 seconds
Started Jul 11 06:47:44 PM PDT 24
Finished Jul 11 06:48:16 PM PDT 24
Peak memory 248388 kb
Host smart-4516a693-37ff-46e9-8185-00faab273ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23067
4693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.230674693
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.836020533
Short name T69
Test name
Test status
Simulation time 3118605132 ps
CPU time 50.72 seconds
Started Jul 11 06:47:46 PM PDT 24
Finished Jul 11 06:48:37 PM PDT 24
Peak memory 256652 kb
Host smart-5e105275-ce76-4351-aff0-6b0a6e832adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83602
0533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.836020533
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2506279056
Short name T635
Test name
Test status
Simulation time 1077957544 ps
CPU time 38.59 seconds
Started Jul 11 06:47:42 PM PDT 24
Finished Jul 11 06:48:22 PM PDT 24
Peak memory 256512 kb
Host smart-512c3ab1-52f4-47e3-b14a-a453b4a628d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
79056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2506279056
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1465251636
Short name T4
Test name
Test status
Simulation time 22242357140 ps
CPU time 1527.45 seconds
Started Jul 11 06:47:59 PM PDT 24
Finished Jul 11 07:13:28 PM PDT 24
Peak memory 290264 kb
Host smart-1e46c147-577a-4c30-8c1c-76c6b50da14a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465251636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1465251636
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3940966049
Short name T373
Test name
Test status
Simulation time 2849403509 ps
CPU time 149.29 seconds
Started Jul 11 06:48:00 PM PDT 24
Finished Jul 11 06:50:30 PM PDT 24
Peak memory 256980 kb
Host smart-78e2fe7a-30ee-4c57-9ce0-9b2c6517c2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
66049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3940966049
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1948207997
Short name T591
Test name
Test status
Simulation time 3541867878 ps
CPU time 65.88 seconds
Started Jul 11 06:47:59 PM PDT 24
Finished Jul 11 06:49:06 PM PDT 24
Peak memory 249384 kb
Host smart-a1502cf7-b580-4502-a39c-901d223c6801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19482
07997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1948207997
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.4188768652
Short name T342
Test name
Test status
Simulation time 35632241922 ps
CPU time 685.45 seconds
Started Jul 11 06:48:01 PM PDT 24
Finished Jul 11 06:59:27 PM PDT 24
Peak memory 273752 kb
Host smart-58909ef0-7f34-477d-9255-e23e0d07d94d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188768652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4188768652
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3948737047
Short name T123
Test name
Test status
Simulation time 177102536162 ps
CPU time 3069.48 seconds
Started Jul 11 06:47:59 PM PDT 24
Finished Jul 11 07:39:10 PM PDT 24
Peak memory 288676 kb
Host smart-8027bd3d-b74c-4242-80f3-2413ff3ba8af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948737047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3948737047
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1098029283
Short name T327
Test name
Test status
Simulation time 63963646357 ps
CPU time 401.71 seconds
Started Jul 11 06:47:58 PM PDT 24
Finished Jul 11 06:54:41 PM PDT 24
Peak memory 257608 kb
Host smart-5f11cd3a-67a0-40e1-bdd7-0933e1d8bd50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098029283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1098029283
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1666213471
Short name T57
Test name
Test status
Simulation time 1831898505 ps
CPU time 34.83 seconds
Started Jul 11 06:47:56 PM PDT 24
Finished Jul 11 06:48:32 PM PDT 24
Peak memory 257168 kb
Host smart-1f0dc6c7-e98a-4a87-b709-09e638dab945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
13471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1666213471
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3230628697
Short name T86
Test name
Test status
Simulation time 470753793 ps
CPU time 16.3 seconds
Started Jul 11 06:47:58 PM PDT 24
Finished Jul 11 06:48:15 PM PDT 24
Peak memory 256800 kb
Host smart-11e879ed-0776-42eb-8137-aee48df02a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306
28697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3230628697
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1093660363
Short name T384
Test name
Test status
Simulation time 361129604 ps
CPU time 7.11 seconds
Started Jul 11 06:47:54 PM PDT 24
Finished Jul 11 06:48:02 PM PDT 24
Peak memory 252328 kb
Host smart-e2c5f165-2877-4df4-af6d-b5be10e0e341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10936
60363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1093660363
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2973681098
Short name T436
Test name
Test status
Simulation time 9805040936 ps
CPU time 171.86 seconds
Started Jul 11 06:48:03 PM PDT 24
Finished Jul 11 06:50:56 PM PDT 24
Peak memory 257516 kb
Host smart-d733c07f-40b4-4743-bd60-df17c4ecd081
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973681098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2973681098
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1605512184
Short name T18
Test name
Test status
Simulation time 134155053213 ps
CPU time 2702.21 seconds
Started Jul 11 06:48:21 PM PDT 24
Finished Jul 11 07:33:24 PM PDT 24
Peak memory 290168 kb
Host smart-85d48b25-0c2c-45ae-af6d-a59a68a2c049
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605512184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1605512184
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2114970527
Short name T419
Test name
Test status
Simulation time 2530360635 ps
CPU time 59.85 seconds
Started Jul 11 06:48:19 PM PDT 24
Finished Jul 11 06:49:20 PM PDT 24
Peak memory 257512 kb
Host smart-4157e13c-d986-4a4b-9004-8b0ca943fcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21149
70527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2114970527
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1494472888
Short name T518
Test name
Test status
Simulation time 1136552584 ps
CPU time 71.2 seconds
Started Jul 11 06:48:17 PM PDT 24
Finished Jul 11 06:49:29 PM PDT 24
Peak memory 249108 kb
Host smart-cced6f82-99c5-44a4-b549-ccfe90932ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
72888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1494472888
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1857124070
Short name T424
Test name
Test status
Simulation time 77178107244 ps
CPU time 2095.71 seconds
Started Jul 11 06:48:24 PM PDT 24
Finished Jul 11 07:23:21 PM PDT 24
Peak memory 289392 kb
Host smart-1e11e028-fa6f-43b3-b257-3aea815cc4fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857124070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1857124070
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3254961056
Short name T556
Test name
Test status
Simulation time 882347300 ps
CPU time 52.67 seconds
Started Jul 11 06:48:09 PM PDT 24
Finished Jul 11 06:49:02 PM PDT 24
Peak memory 256632 kb
Host smart-3c0580f5-a62f-4172-bbaf-7e2a70d01d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32549
61056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3254961056
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1259837240
Short name T530
Test name
Test status
Simulation time 747968177 ps
CPU time 13.55 seconds
Started Jul 11 06:48:08 PM PDT 24
Finished Jul 11 06:48:22 PM PDT 24
Peak memory 255464 kb
Host smart-1da45e1b-1b4e-4d94-a550-0a12408e522f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12598
37240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1259837240
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1464418981
Short name T256
Test name
Test status
Simulation time 293989468 ps
CPU time 20.54 seconds
Started Jul 11 06:48:18 PM PDT 24
Finished Jul 11 06:48:39 PM PDT 24
Peak memory 257004 kb
Host smart-325ec3d4-9e44-447b-9819-e7fde48a1d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14644
18981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1464418981
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2774906177
Short name T656
Test name
Test status
Simulation time 36926361 ps
CPU time 6.5 seconds
Started Jul 11 06:48:11 PM PDT 24
Finished Jul 11 06:48:18 PM PDT 24
Peak memory 249276 kb
Host smart-2c6c7789-4e6a-4be5-af92-acea4a953c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27749
06177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2774906177
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2367747097
Short name T266
Test name
Test status
Simulation time 42285834492 ps
CPU time 2881.36 seconds
Started Jul 11 06:48:24 PM PDT 24
Finished Jul 11 07:36:27 PM PDT 24
Peak memory 300652 kb
Host smart-b5743d93-8de4-47f0-9a7b-ca063b49569d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367747097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2367747097
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3897122033
Short name T33
Test name
Test status
Simulation time 69555371776 ps
CPU time 1749.23 seconds
Started Jul 11 06:48:24 PM PDT 24
Finished Jul 11 07:17:35 PM PDT 24
Peak memory 305668 kb
Host smart-22ee6c8a-85f5-4dc5-bc0a-d386d13e7984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897122033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3897122033
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3091107139
Short name T535
Test name
Test status
Simulation time 141957780697 ps
CPU time 2030.25 seconds
Started Jul 11 06:48:31 PM PDT 24
Finished Jul 11 07:22:22 PM PDT 24
Peak memory 288268 kb
Host smart-22fea1c3-9f9e-458c-b6c6-087af4e4a83a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091107139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3091107139
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3510667534
Short name T455
Test name
Test status
Simulation time 3072824932 ps
CPU time 195.71 seconds
Started Jul 11 06:48:31 PM PDT 24
Finished Jul 11 06:51:48 PM PDT 24
Peak memory 257144 kb
Host smart-f9a70036-838e-4677-9465-9ebfd6da396a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35106
67534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3510667534
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.529845671
Short name T46
Test name
Test status
Simulation time 338911716 ps
CPU time 27.69 seconds
Started Jul 11 06:48:27 PM PDT 24
Finished Jul 11 06:48:55 PM PDT 24
Peak memory 256700 kb
Host smart-a00e4ea3-7657-4e8f-9df6-c71b77e69639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52984
5671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.529845671
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.870128668
Short name T690
Test name
Test status
Simulation time 246282142782 ps
CPU time 1525.72 seconds
Started Jul 11 06:48:34 PM PDT 24
Finished Jul 11 07:14:00 PM PDT 24
Peak memory 285376 kb
Host smart-646dc521-83ee-4d71-8a4a-50bb1fdb7ff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870128668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.870128668
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.11854607
Short name T218
Test name
Test status
Simulation time 24130253352 ps
CPU time 1454.56 seconds
Started Jul 11 06:48:34 PM PDT 24
Finished Jul 11 07:12:49 PM PDT 24
Peak memory 273912 kb
Host smart-b9229bea-edd0-4ca7-966b-9ba2a694a99e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11854607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.11854607
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1204015438
Short name T638
Test name
Test status
Simulation time 26113072806 ps
CPU time 276.92 seconds
Started Jul 11 06:48:31 PM PDT 24
Finished Jul 11 06:53:09 PM PDT 24
Peak memory 249436 kb
Host smart-c08ed05b-a94d-4e9d-85de-536d96cbcbec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204015438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1204015438
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1536996376
Short name T688
Test name
Test status
Simulation time 94167463 ps
CPU time 7.64 seconds
Started Jul 11 06:48:21 PM PDT 24
Finished Jul 11 06:48:30 PM PDT 24
Peak memory 249324 kb
Host smart-2163560d-3453-46c9-9189-41630131ea43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15369
96376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1536996376
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1990894131
Short name T115
Test name
Test status
Simulation time 540829414 ps
CPU time 29.79 seconds
Started Jul 11 06:48:27 PM PDT 24
Finished Jul 11 06:48:57 PM PDT 24
Peak memory 249332 kb
Host smart-9454ad5f-bff2-4ae7-9f47-faaa75fb0482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19908
94131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1990894131
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2980615806
Short name T270
Test name
Test status
Simulation time 2760661964 ps
CPU time 23.02 seconds
Started Jul 11 06:48:33 PM PDT 24
Finished Jul 11 06:48:56 PM PDT 24
Peak memory 249408 kb
Host smart-444d3a15-b81d-42b9-82de-2e039d3314bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
15806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2980615806
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.764107070
Short name T560
Test name
Test status
Simulation time 587948016 ps
CPU time 42.06 seconds
Started Jul 11 06:48:22 PM PDT 24
Finished Jul 11 06:49:05 PM PDT 24
Peak memory 257396 kb
Host smart-17f98106-1048-436e-bbf4-c576e6c2ce09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76410
7070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.764107070
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3685134614
Short name T629
Test name
Test status
Simulation time 96341658333 ps
CPU time 2082.04 seconds
Started Jul 11 06:48:36 PM PDT 24
Finished Jul 11 07:23:19 PM PDT 24
Peak memory 290432 kb
Host smart-262a35ec-aed0-4d89-926e-8a1b4bee47cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685134614 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3685134614
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2967816086
Short name T487
Test name
Test status
Simulation time 11834165525 ps
CPU time 1213.22 seconds
Started Jul 11 06:48:47 PM PDT 24
Finished Jul 11 07:09:02 PM PDT 24
Peak memory 287096 kb
Host smart-520040e3-4a72-433b-88af-9ab5d8c7e9a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967816086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2967816086
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.511435061
Short name T398
Test name
Test status
Simulation time 1937795153 ps
CPU time 140.04 seconds
Started Jul 11 06:48:46 PM PDT 24
Finished Jul 11 06:51:06 PM PDT 24
Peak memory 252324 kb
Host smart-3c73e303-38d8-452d-9032-4acabd1a24e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51143
5061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.511435061
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1694686281
Short name T442
Test name
Test status
Simulation time 433238404 ps
CPU time 8.15 seconds
Started Jul 11 06:48:34 PM PDT 24
Finished Jul 11 06:48:43 PM PDT 24
Peak memory 249248 kb
Host smart-dabf9b9c-bca2-44e3-b75b-46022d05415f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
86281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1694686281
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1467264652
Short name T347
Test name
Test status
Simulation time 38747533972 ps
CPU time 1383.19 seconds
Started Jul 11 06:48:45 PM PDT 24
Finished Jul 11 07:11:49 PM PDT 24
Peak memory 273632 kb
Host smart-60c85dd2-b63a-4110-9e18-584318daafea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467264652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1467264652
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2396914555
Short name T106
Test name
Test status
Simulation time 33427361714 ps
CPU time 1980.73 seconds
Started Jul 11 06:48:45 PM PDT 24
Finished Jul 11 07:21:46 PM PDT 24
Peak memory 282296 kb
Host smart-05282e95-8c0c-49c0-8c88-284dd9bb3c8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396914555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2396914555
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1236959990
Short name T314
Test name
Test status
Simulation time 21793748000 ps
CPU time 457.12 seconds
Started Jul 11 06:48:47 PM PDT 24
Finished Jul 11 06:56:25 PM PDT 24
Peak memory 249400 kb
Host smart-f36c25a6-e57c-4db9-932d-fa23daf1d224
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236959990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1236959990
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4050405288
Short name T458
Test name
Test status
Simulation time 1449689083 ps
CPU time 50.72 seconds
Started Jul 11 06:48:36 PM PDT 24
Finished Jul 11 06:49:28 PM PDT 24
Peak memory 256588 kb
Host smart-467760fb-1b2d-4bc3-a4ef-177e4989f296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40504
05288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4050405288
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1194183994
Short name T375
Test name
Test status
Simulation time 227494428 ps
CPU time 13.12 seconds
Started Jul 11 06:48:35 PM PDT 24
Finished Jul 11 06:48:50 PM PDT 24
Peak memory 248796 kb
Host smart-9a6a191d-8586-429d-b116-93ded37cd708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11941
83994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1194183994
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.952346354
Short name T498
Test name
Test status
Simulation time 268516112 ps
CPU time 16.74 seconds
Started Jul 11 06:48:44 PM PDT 24
Finished Jul 11 06:49:02 PM PDT 24
Peak memory 248716 kb
Host smart-f21f3be5-3edc-46d0-9898-fc44be78e900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95234
6354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.952346354
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3271136284
Short name T365
Test name
Test status
Simulation time 1955770397 ps
CPU time 53.14 seconds
Started Jul 11 06:48:35 PM PDT 24
Finished Jul 11 06:49:30 PM PDT 24
Peak memory 257396 kb
Host smart-2e97e48a-dc69-4ee8-bdc1-accd28c45296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32711
36284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3271136284
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3137888552
Short name T580
Test name
Test status
Simulation time 30203006167 ps
CPU time 904.98 seconds
Started Jul 11 06:48:55 PM PDT 24
Finished Jul 11 07:04:01 PM PDT 24
Peak memory 273948 kb
Host smart-36fd562d-8dbb-40db-9082-5b9ef4332a61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137888552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3137888552
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1715589493
Short name T685
Test name
Test status
Simulation time 1908993260 ps
CPU time 41.25 seconds
Started Jul 11 06:48:53 PM PDT 24
Finished Jul 11 06:49:35 PM PDT 24
Peak memory 257000 kb
Host smart-2496607d-ff28-4822-a6ff-491720c50125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17155
89493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1715589493
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.965644225
Short name T47
Test name
Test status
Simulation time 253606653 ps
CPU time 20.37 seconds
Started Jul 11 06:48:49 PM PDT 24
Finished Jul 11 06:49:10 PM PDT 24
Peak memory 249896 kb
Host smart-372e4d5f-42b4-46ba-b7d4-59cab0b63f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96564
4225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.965644225
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3863642551
Short name T334
Test name
Test status
Simulation time 11728043182 ps
CPU time 1285.29 seconds
Started Jul 11 06:48:57 PM PDT 24
Finished Jul 11 07:10:23 PM PDT 24
Peak memory 284160 kb
Host smart-d92d6e9e-7c86-4539-b2ea-3be4442fbcee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863642551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3863642551
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4038893505
Short name T462
Test name
Test status
Simulation time 12253619661 ps
CPU time 727.47 seconds
Started Jul 11 06:48:59 PM PDT 24
Finished Jul 11 07:01:07 PM PDT 24
Peak memory 273888 kb
Host smart-28f2844d-41d3-42a9-a14a-18292129fd5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038893505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4038893505
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.168371571
Short name T694
Test name
Test status
Simulation time 2113608206 ps
CPU time 69.81 seconds
Started Jul 11 06:48:50 PM PDT 24
Finished Jul 11 06:50:01 PM PDT 24
Peak memory 256800 kb
Host smart-1ad4c740-720c-460c-90b1-a75a74cc3f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
1571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.168371571
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4248233477
Short name T589
Test name
Test status
Simulation time 4374792702 ps
CPU time 88.01 seconds
Started Jul 11 06:48:52 PM PDT 24
Finished Jul 11 06:50:21 PM PDT 24
Peak memory 249468 kb
Host smart-7673e306-8b87-438e-937f-ae3e4d2a33bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42482
33477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4248233477
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.156985021
Short name T20
Test name
Test status
Simulation time 1255490314 ps
CPU time 20.17 seconds
Started Jul 11 06:48:57 PM PDT 24
Finished Jul 11 06:49:17 PM PDT 24
Peak memory 256716 kb
Host smart-f3f5d3d0-25de-4d1c-a5ae-362cd202a08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15698
5021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.156985021
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.825343742
Short name T466
Test name
Test status
Simulation time 6490069952 ps
CPU time 56.31 seconds
Started Jul 11 06:48:49 PM PDT 24
Finished Jul 11 06:49:46 PM PDT 24
Peak memory 257076 kb
Host smart-dba6d51d-84bc-4050-95e7-374c788fe5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82534
3742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.825343742
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.85208656
Short name T533
Test name
Test status
Simulation time 1322154021 ps
CPU time 141.72 seconds
Started Jul 11 06:49:04 PM PDT 24
Finished Jul 11 06:51:27 PM PDT 24
Peak memory 257480 kb
Host smart-d8c6c9a9-64d0-4fb5-8815-1b58a3bd92be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85208656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_hand
ler_stress_all.85208656
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3855901685
Short name T482
Test name
Test status
Simulation time 72942611815 ps
CPU time 1190.03 seconds
Started Jul 11 06:49:12 PM PDT 24
Finished Jul 11 07:09:03 PM PDT 24
Peak memory 265836 kb
Host smart-23a61624-e10e-45f1-82f7-c0c61409f0b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855901685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3855901685
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1336197919
Short name T448
Test name
Test status
Simulation time 100755106890 ps
CPU time 273 seconds
Started Jul 11 06:49:12 PM PDT 24
Finished Jul 11 06:53:46 PM PDT 24
Peak memory 257620 kb
Host smart-f5f3183c-538f-4534-95ef-df912a27dc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
97919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1336197919
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3855387583
Short name T569
Test name
Test status
Simulation time 1595132751 ps
CPU time 34.09 seconds
Started Jul 11 06:49:11 PM PDT 24
Finished Jul 11 06:49:46 PM PDT 24
Peak memory 249252 kb
Host smart-e68d3298-3ac3-4733-9aa0-5326994791aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
87583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3855387583
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1872645298
Short name T202
Test name
Test status
Simulation time 68478460992 ps
CPU time 1142.93 seconds
Started Jul 11 06:49:10 PM PDT 24
Finished Jul 11 07:08:14 PM PDT 24
Peak memory 273464 kb
Host smart-927a436c-c11a-4384-95c6-8db6baf53937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872645298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1872645298
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3290246160
Short name T578
Test name
Test status
Simulation time 6537207466 ps
CPU time 264.78 seconds
Started Jul 11 06:49:12 PM PDT 24
Finished Jul 11 06:53:38 PM PDT 24
Peak memory 255844 kb
Host smart-7b5f52ad-c1d2-4d95-a769-387e8461d3e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290246160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3290246160
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.679042156
Short name T607
Test name
Test status
Simulation time 127078258 ps
CPU time 4.09 seconds
Started Jul 11 06:49:05 PM PDT 24
Finished Jul 11 06:49:10 PM PDT 24
Peak memory 241064 kb
Host smart-e69df593-57ab-483f-862e-1951356a1dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67904
2156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.679042156
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2352963538
Short name T399
Test name
Test status
Simulation time 503147927 ps
CPU time 17.04 seconds
Started Jul 11 06:49:08 PM PDT 24
Finished Jul 11 06:49:25 PM PDT 24
Peak memory 255288 kb
Host smart-5ff60091-0d33-4153-9c0c-6eee95b2b4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23529
63538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2352963538
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.252346456
Short name T267
Test name
Test status
Simulation time 902331569 ps
CPU time 51.22 seconds
Started Jul 11 06:49:13 PM PDT 24
Finished Jul 11 06:50:04 PM PDT 24
Peak memory 256996 kb
Host smart-ed25518a-a12f-44ca-b2cd-130b36cb9c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25234
6456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.252346456
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3016100386
Short name T495
Test name
Test status
Simulation time 309307280 ps
CPU time 28.25 seconds
Started Jul 11 06:49:09 PM PDT 24
Finished Jul 11 06:49:38 PM PDT 24
Peak memory 249228 kb
Host smart-d9803e4d-1ccc-4fec-9f3d-23d96c9fafcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30161
00386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3016100386
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1902996368
Short name T403
Test name
Test status
Simulation time 140858656849 ps
CPU time 2086.88 seconds
Started Jul 11 06:49:15 PM PDT 24
Finished Jul 11 07:24:03 PM PDT 24
Peak memory 283384 kb
Host smart-5801a195-b5f9-4d8a-abd5-abd06ae52e6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902996368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1902996368
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2692930272
Short name T233
Test name
Test status
Simulation time 147003353 ps
CPU time 4.29 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:44:32 PM PDT 24
Peak memory 249516 kb
Host smart-78e8289b-6bda-4f47-b8a9-db43d63feb1d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2692930272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2692930272
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1176289523
Short name T497
Test name
Test status
Simulation time 50943403872 ps
CPU time 2547.42 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 07:26:56 PM PDT 24
Peak memory 290388 kb
Host smart-5a2d5699-51e0-4492-9a47-04a77a573044
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176289523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1176289523
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1625682020
Short name T541
Test name
Test status
Simulation time 203784515 ps
CPU time 6.56 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:44:35 PM PDT 24
Peak memory 249252 kb
Host smart-baf2470a-60fd-4263-9f85-98acb30d40ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1625682020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1625682020
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2663907150
Short name T588
Test name
Test status
Simulation time 1076960437 ps
CPU time 67.04 seconds
Started Jul 11 06:44:23 PM PDT 24
Finished Jul 11 06:45:32 PM PDT 24
Peak memory 257040 kb
Host smart-53149e17-bdf8-41f8-83f5-2a005f7f86ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
07150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2663907150
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.277183529
Short name T68
Test name
Test status
Simulation time 1410569140 ps
CPU time 19.74 seconds
Started Jul 11 06:44:26 PM PDT 24
Finished Jul 11 06:44:47 PM PDT 24
Peak memory 256112 kb
Host smart-1e03f806-9691-4f64-a94d-6fb31f3c422c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27718
3529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.277183529
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4161819970
Short name T240
Test name
Test status
Simulation time 93766017501 ps
CPU time 1139.83 seconds
Started Jul 11 06:44:22 PM PDT 24
Finished Jul 11 07:03:23 PM PDT 24
Peak memory 273864 kb
Host smart-9cd746fe-a9e5-4200-85a5-b0f55d0c98a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161819970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4161819970
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3046939110
Short name T504
Test name
Test status
Simulation time 49247840117 ps
CPU time 1244.38 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 07:05:13 PM PDT 24
Peak memory 273012 kb
Host smart-9edc98df-5b66-4893-bb97-ec67784c3421
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046939110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3046939110
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1253805701
Short name T390
Test name
Test status
Simulation time 119588455 ps
CPU time 14.52 seconds
Started Jul 11 06:44:18 PM PDT 24
Finished Jul 11 06:44:34 PM PDT 24
Peak memory 249324 kb
Host smart-0ecbf9f0-bfb7-44f6-bbf1-392ade416513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538
05701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1253805701
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1813682456
Short name T381
Test name
Test status
Simulation time 205698092 ps
CPU time 16.88 seconds
Started Jul 11 06:44:19 PM PDT 24
Finished Jul 11 06:44:38 PM PDT 24
Peak memory 256412 kb
Host smart-9bba4171-e8e7-4e54-a52c-bdfb1e024838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18136
82456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1813682456
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.679505690
Short name T38
Test name
Test status
Simulation time 544601814 ps
CPU time 24.34 seconds
Started Jul 11 06:44:23 PM PDT 24
Finished Jul 11 06:44:48 PM PDT 24
Peak memory 274900 kb
Host smart-1bab09e1-6f04-4a70-ba89-a281643ffce9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=679505690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.679505690
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3801833043
Short name T645
Test name
Test status
Simulation time 2933565781 ps
CPU time 53.39 seconds
Started Jul 11 06:44:23 PM PDT 24
Finished Jul 11 06:45:18 PM PDT 24
Peak memory 249392 kb
Host smart-b0319041-17ce-49ae-83d9-e6aff3dc5e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38018
33043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3801833043
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3806317312
Short name T630
Test name
Test status
Simulation time 714945458 ps
CPU time 44.87 seconds
Started Jul 11 06:44:20 PM PDT 24
Finished Jul 11 06:45:07 PM PDT 24
Peak memory 257336 kb
Host smart-403bd0f4-0863-43fd-9382-6a9262a98127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
17312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3806317312
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1639224823
Short name T116
Test name
Test status
Simulation time 141596381156 ps
CPU time 2316.01 seconds
Started Jul 11 06:44:25 PM PDT 24
Finished Jul 11 07:23:02 PM PDT 24
Peak memory 290376 kb
Host smart-a9b9597c-f7f7-4ef3-9681-a1fd67da5ea5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639224823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1639224823
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.850126068
Short name T388
Test name
Test status
Simulation time 25216041162 ps
CPU time 1578.56 seconds
Started Jul 11 06:49:29 PM PDT 24
Finished Jul 11 07:15:49 PM PDT 24
Peak memory 273772 kb
Host smart-a594341d-3b98-4ec8-962e-a42fac8107a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850126068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.850126068
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1229528839
Short name T444
Test name
Test status
Simulation time 235706568 ps
CPU time 20.39 seconds
Started Jul 11 06:49:23 PM PDT 24
Finished Jul 11 06:49:44 PM PDT 24
Peak memory 256776 kb
Host smart-0be20c72-c8e6-42fc-8271-722a7d309eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12295
28839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1229528839
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2270000527
Short name T534
Test name
Test status
Simulation time 1943098009 ps
CPU time 34.24 seconds
Started Jul 11 06:49:24 PM PDT 24
Finished Jul 11 06:49:58 PM PDT 24
Peak memory 257024 kb
Host smart-0d88e4c0-68b9-46d0-a6f3-f4b72961f4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22700
00527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2270000527
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3522663530
Short name T598
Test name
Test status
Simulation time 195225194476 ps
CPU time 3020.1 seconds
Started Jul 11 06:49:29 PM PDT 24
Finished Jul 11 07:39:51 PM PDT 24
Peak memory 289336 kb
Host smart-c990dc36-fde5-4a3d-964d-f6424853eff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522663530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3522663530
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4011661999
Short name T392
Test name
Test status
Simulation time 170220895250 ps
CPU time 2233.89 seconds
Started Jul 11 06:49:28 PM PDT 24
Finished Jul 11 07:26:42 PM PDT 24
Peak memory 289464 kb
Host smart-36474ee8-e231-46fc-8a30-cc6ed87996d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011661999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4011661999
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2942907084
Short name T321
Test name
Test status
Simulation time 35329507629 ps
CPU time 377.53 seconds
Started Jul 11 06:49:29 PM PDT 24
Finished Jul 11 06:55:48 PM PDT 24
Peak memory 249416 kb
Host smart-3053d93d-89e0-410f-a29f-6a4a4b8b3ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942907084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2942907084
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2175414076
Short name T366
Test name
Test status
Simulation time 1077250726 ps
CPU time 31.74 seconds
Started Jul 11 06:49:20 PM PDT 24
Finished Jul 11 06:49:52 PM PDT 24
Peak memory 256792 kb
Host smart-f54a0a5d-9287-4041-b8c1-8ac3b76eb848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754
14076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2175414076
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1935106633
Short name T77
Test name
Test status
Simulation time 362239773 ps
CPU time 44.4 seconds
Started Jul 11 06:49:18 PM PDT 24
Finished Jul 11 06:50:03 PM PDT 24
Peak memory 249272 kb
Host smart-5068fb38-01d6-4626-8000-7eb7156f086a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
06633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1935106633
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.472118778
Short name T109
Test name
Test status
Simulation time 540762983 ps
CPU time 37.56 seconds
Started Jul 11 06:49:25 PM PDT 24
Finished Jul 11 06:50:03 PM PDT 24
Peak memory 249892 kb
Host smart-5374a58d-2495-4edf-afd7-80c08cfc4035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47211
8778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.472118778
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1848442690
Short name T654
Test name
Test status
Simulation time 306906529 ps
CPU time 31.37 seconds
Started Jul 11 06:49:15 PM PDT 24
Finished Jul 11 06:49:47 PM PDT 24
Peak memory 257220 kb
Host smart-59e6e2f8-ce76-4680-8b32-3a4689674105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
42690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1848442690
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.279147069
Short name T499
Test name
Test status
Simulation time 11667166429 ps
CPU time 1448.38 seconds
Started Jul 11 06:49:29 PM PDT 24
Finished Jul 11 07:13:39 PM PDT 24
Peak memory 290356 kb
Host smart-6aa5e9f4-f78b-4173-90f0-5d54d231fd4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279147069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.279147069
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3686991335
Short name T66
Test name
Test status
Simulation time 165618294191 ps
CPU time 4666.08 seconds
Started Jul 11 06:49:28 PM PDT 24
Finished Jul 11 08:07:16 PM PDT 24
Peak memory 338704 kb
Host smart-3f0a1e1a-3d63-4a4f-81c8-aa03f316af85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686991335 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3686991335
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.921850536
Short name T104
Test name
Test status
Simulation time 160764965884 ps
CPU time 1223.82 seconds
Started Jul 11 06:49:37 PM PDT 24
Finished Jul 11 07:10:02 PM PDT 24
Peak memory 289648 kb
Host smart-1873114a-d8f4-472d-bddb-6a52e8211434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921850536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.921850536
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2388731205
Short name T614
Test name
Test status
Simulation time 3248498244 ps
CPU time 183.54 seconds
Started Jul 11 06:49:37 PM PDT 24
Finished Jul 11 06:52:41 PM PDT 24
Peak memory 257156 kb
Host smart-6d5a2348-2b3e-4aeb-a382-9a57346460a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23887
31205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2388731205
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2883614906
Short name T483
Test name
Test status
Simulation time 1726886671 ps
CPU time 34.31 seconds
Started Jul 11 06:49:35 PM PDT 24
Finished Jul 11 06:50:10 PM PDT 24
Peak memory 248720 kb
Host smart-42fd7286-d8de-40e9-89ad-b8379693cad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28836
14906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2883614906
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1073092627
Short name T553
Test name
Test status
Simulation time 83797942996 ps
CPU time 1223.94 seconds
Started Jul 11 06:49:41 PM PDT 24
Finished Jul 11 07:10:06 PM PDT 24
Peak memory 265700 kb
Host smart-f152cf27-d73a-4713-a187-091ff4aff2ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073092627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1073092627
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1067104083
Short name T526
Test name
Test status
Simulation time 11678576548 ps
CPU time 492.84 seconds
Started Jul 11 06:49:39 PM PDT 24
Finished Jul 11 06:57:53 PM PDT 24
Peak memory 249460 kb
Host smart-b90e1700-509b-430b-aba4-8d568f02002a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067104083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1067104083
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3097063919
Short name T1
Test name
Test status
Simulation time 703931444 ps
CPU time 15.66 seconds
Started Jul 11 06:49:34 PM PDT 24
Finished Jul 11 06:49:50 PM PDT 24
Peak memory 249348 kb
Host smart-bcde00b0-2e09-45e9-802f-52c2c43c755c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30970
63919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3097063919
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1440460850
Short name T673
Test name
Test status
Simulation time 223896441 ps
CPU time 20.53 seconds
Started Jul 11 06:49:35 PM PDT 24
Finished Jul 11 06:49:56 PM PDT 24
Peak memory 256904 kb
Host smart-78350cd5-e6cb-49a8-a24c-719630441e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14404
60850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1440460850
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1095786643
Short name T697
Test name
Test status
Simulation time 438281220 ps
CPU time 29.6 seconds
Started Jul 11 06:49:37 PM PDT 24
Finished Jul 11 06:50:07 PM PDT 24
Peak memory 248764 kb
Host smart-13014f65-a01a-4d1f-86b4-c88464186700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
86643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1095786643
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2218776663
Short name T678
Test name
Test status
Simulation time 3629966696 ps
CPU time 56.9 seconds
Started Jul 11 06:49:34 PM PDT 24
Finished Jul 11 06:50:31 PM PDT 24
Peak memory 257568 kb
Host smart-d54f74bf-b251-408f-9c7e-18a63d3232fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22187
76663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2218776663
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3319564821
Short name T422
Test name
Test status
Simulation time 39354614656 ps
CPU time 1650 seconds
Started Jul 11 06:49:41 PM PDT 24
Finished Jul 11 07:17:12 PM PDT 24
Peak memory 290380 kb
Host smart-0ded2340-7e69-45f4-baf6-d5eb4bc69aee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319564821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3319564821
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.722200475
Short name T80
Test name
Test status
Simulation time 22260036643 ps
CPU time 1433.72 seconds
Started Jul 11 06:49:40 PM PDT 24
Finished Jul 11 07:13:35 PM PDT 24
Peak memory 290404 kb
Host smart-3c07c408-25ba-44f5-84bc-f05d47075b8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722200475 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.722200475
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3699703456
Short name T705
Test name
Test status
Simulation time 3952603095 ps
CPU time 294.38 seconds
Started Jul 11 06:49:49 PM PDT 24
Finished Jul 11 06:54:44 PM PDT 24
Peak memory 257512 kb
Host smart-3254cbd3-7775-4b86-9977-15015696566b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36997
03456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3699703456
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1002564592
Short name T367
Test name
Test status
Simulation time 233823968 ps
CPU time 22.53 seconds
Started Jul 11 06:49:51 PM PDT 24
Finished Jul 11 06:50:14 PM PDT 24
Peak memory 248852 kb
Host smart-3568a662-d79f-4b68-80c6-af79d7b654fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10025
64592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1002564592
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3856106983
Short name T507
Test name
Test status
Simulation time 12064165023 ps
CPU time 1024.36 seconds
Started Jul 11 06:49:56 PM PDT 24
Finished Jul 11 07:07:01 PM PDT 24
Peak memory 273828 kb
Host smart-2f37c71b-8c09-4e58-a736-1284929dbe27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856106983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3856106983
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1773278576
Short name T493
Test name
Test status
Simulation time 110205410361 ps
CPU time 815.03 seconds
Started Jul 11 06:49:57 PM PDT 24
Finished Jul 11 07:03:33 PM PDT 24
Peak memory 270884 kb
Host smart-3b44217a-3837-419c-bbb5-70c029266c6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773278576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1773278576
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.980293603
Short name T316
Test name
Test status
Simulation time 22916767921 ps
CPU time 445.78 seconds
Started Jul 11 06:49:56 PM PDT 24
Finished Jul 11 06:57:23 PM PDT 24
Peak memory 248252 kb
Host smart-7082cddd-f6c7-4356-847c-b8ea28b482b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980293603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.980293603
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3835251063
Short name T130
Test name
Test status
Simulation time 1019553672 ps
CPU time 32.69 seconds
Started Jul 11 06:49:46 PM PDT 24
Finished Jul 11 06:50:19 PM PDT 24
Peak memory 256672 kb
Host smart-e62e8267-2ac0-44be-b46b-824333b70b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352
51063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3835251063
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1648374327
Short name T113
Test name
Test status
Simulation time 1000405681 ps
CPU time 20.87 seconds
Started Jul 11 06:49:46 PM PDT 24
Finished Jul 11 06:50:08 PM PDT 24
Peak memory 248668 kb
Host smart-d155a210-746c-4e31-ad40-9d3c7f7d7551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16483
74327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1648374327
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3137122686
Short name T461
Test name
Test status
Simulation time 685621788 ps
CPU time 27.77 seconds
Started Jul 11 06:49:57 PM PDT 24
Finished Jul 11 06:50:26 PM PDT 24
Peak memory 256792 kb
Host smart-3bc182d1-c3b5-40fa-a3e0-578c20690521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31371
22686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3137122686
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.677570346
Short name T241
Test name
Test status
Simulation time 63556035 ps
CPU time 6.26 seconds
Started Jul 11 06:49:48 PM PDT 24
Finished Jul 11 06:49:54 PM PDT 24
Peak memory 249236 kb
Host smart-485ce22a-8b81-4476-83cf-180cfe07ae4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67757
0346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.677570346
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2122526127
Short name T416
Test name
Test status
Simulation time 53348933077 ps
CPU time 1055.15 seconds
Started Jul 11 06:49:56 PM PDT 24
Finished Jul 11 07:07:32 PM PDT 24
Peak memory 289272 kb
Host smart-b5f62012-fb68-4d66-a380-27c829d16725
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122526127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2122526127
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3964517143
Short name T456
Test name
Test status
Simulation time 43069964560 ps
CPU time 2285.28 seconds
Started Jul 11 06:50:02 PM PDT 24
Finished Jul 11 07:28:08 PM PDT 24
Peak memory 290508 kb
Host smart-d957302b-aba5-4c4e-9b51-2c843d1e1bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964517143 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3964517143
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.109596502
Short name T291
Test name
Test status
Simulation time 52919926496 ps
CPU time 2844.8 seconds
Started Jul 11 06:50:06 PM PDT 24
Finished Jul 11 07:37:32 PM PDT 24
Peak memory 290324 kb
Host smart-cacc235d-ccd2-430b-9f9f-55e3c340146c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109596502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.109596502
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2391466028
Short name T519
Test name
Test status
Simulation time 278540718 ps
CPU time 8.33 seconds
Started Jul 11 06:50:09 PM PDT 24
Finished Jul 11 06:50:18 PM PDT 24
Peak memory 255216 kb
Host smart-3c3b2059-25cb-4a6f-a35c-d403a4a7c2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23914
66028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2391466028
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.297895583
Short name T45
Test name
Test status
Simulation time 2011658583 ps
CPU time 67.23 seconds
Started Jul 11 06:50:07 PM PDT 24
Finished Jul 11 06:51:15 PM PDT 24
Peak memory 249268 kb
Host smart-0af913cc-00fd-4691-b2bd-b8681f44339f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29789
5583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.297895583
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1509966611
Short name T618
Test name
Test status
Simulation time 40420010245 ps
CPU time 2613.28 seconds
Started Jul 11 06:50:15 PM PDT 24
Finished Jul 11 07:33:50 PM PDT 24
Peak memory 289620 kb
Host smart-5309ffb2-71e1-404f-8e33-418527fd66f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509966611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1509966611
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3116403906
Short name T286
Test name
Test status
Simulation time 140896786992 ps
CPU time 1748.63 seconds
Started Jul 11 06:50:15 PM PDT 24
Finished Jul 11 07:19:25 PM PDT 24
Peak memory 290524 kb
Host smart-0bd6dd1d-4f12-4a41-b2af-ab120f9f2c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116403906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3116403906
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.4676000
Short name T647
Test name
Test status
Simulation time 45425746495 ps
CPU time 425.07 seconds
Started Jul 11 06:50:09 PM PDT 24
Finished Jul 11 06:57:15 PM PDT 24
Peak memory 256032 kb
Host smart-dc073d48-7994-439f-b120-db2c6ceb6f63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4676000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.4676000
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3499804440
Short name T389
Test name
Test status
Simulation time 322663625 ps
CPU time 31.76 seconds
Started Jul 11 06:50:08 PM PDT 24
Finished Jul 11 06:50:40 PM PDT 24
Peak memory 257112 kb
Host smart-1a6e1cb9-6735-4219-adf9-0b4d58fa9858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998
04440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3499804440
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1978126191
Short name T421
Test name
Test status
Simulation time 14168609659 ps
CPU time 40.88 seconds
Started Jul 11 06:50:08 PM PDT 24
Finished Jul 11 06:50:50 PM PDT 24
Peak memory 256692 kb
Host smart-03426998-134b-4a83-a320-84264247d998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19781
26191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1978126191
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2908940638
Short name T275
Test name
Test status
Simulation time 539995763 ps
CPU time 12.63 seconds
Started Jul 11 06:50:05 PM PDT 24
Finished Jul 11 06:50:19 PM PDT 24
Peak memory 249312 kb
Host smart-f4c0e697-3f6c-48f9-9a23-fffbbe311167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29089
40638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2908940638
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3832433589
Short name T408
Test name
Test status
Simulation time 3388748299 ps
CPU time 58.75 seconds
Started Jul 11 06:50:03 PM PDT 24
Finished Jul 11 06:51:03 PM PDT 24
Peak memory 257544 kb
Host smart-1240a028-0d49-4f6f-8861-9374aa9d75c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38324
33589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3832433589
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.210892475
Short name T606
Test name
Test status
Simulation time 16906908664 ps
CPU time 1157.83 seconds
Started Jul 11 06:50:14 PM PDT 24
Finished Jul 11 07:09:32 PM PDT 24
Peak memory 273884 kb
Host smart-bedb68a8-e74f-4b7c-ae33-d8418ce7c924
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210892475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.210892475
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2158652827
Short name T615
Test name
Test status
Simulation time 123074159856 ps
CPU time 1888.05 seconds
Started Jul 11 06:50:27 PM PDT 24
Finished Jul 11 07:21:56 PM PDT 24
Peak memory 285092 kb
Host smart-83d92425-2931-427a-b480-7b90b7832e9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158652827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2158652827
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2663032116
Short name T429
Test name
Test status
Simulation time 710441045 ps
CPU time 45.98 seconds
Started Jul 11 06:50:22 PM PDT 24
Finished Jul 11 06:51:09 PM PDT 24
Peak memory 256984 kb
Host smart-b92aee60-3b63-4f71-824f-3667638d33a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
32116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2663032116
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.423709209
Short name T413
Test name
Test status
Simulation time 1044114185 ps
CPU time 64.95 seconds
Started Jul 11 06:50:22 PM PDT 24
Finished Jul 11 06:51:28 PM PDT 24
Peak memory 256568 kb
Host smart-355aa7fc-d79c-4ae0-9988-4bcb45134640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42370
9209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.423709209
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2000911546
Short name T94
Test name
Test status
Simulation time 86984204447 ps
CPU time 1220.68 seconds
Started Jul 11 06:50:26 PM PDT 24
Finished Jul 11 07:10:47 PM PDT 24
Peak memory 273940 kb
Host smart-504476bc-f66c-4298-a4fa-67896c4b7571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000911546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2000911546
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1226709256
Short name T10
Test name
Test status
Simulation time 8050171343 ps
CPU time 345.96 seconds
Started Jul 11 06:50:27 PM PDT 24
Finished Jul 11 06:56:14 PM PDT 24
Peak memory 249428 kb
Host smart-5686129f-5e8e-4bd1-9a9a-6a6d7a390350
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226709256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1226709256
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2130123958
Short name T26
Test name
Test status
Simulation time 258103517 ps
CPU time 13.83 seconds
Started Jul 11 06:50:22 PM PDT 24
Finished Jul 11 06:50:37 PM PDT 24
Peak memory 249320 kb
Host smart-9d857be4-86ea-46af-80c9-0a536b5ba2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
23958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2130123958
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3361173303
Short name T683
Test name
Test status
Simulation time 3794963102 ps
CPU time 65.32 seconds
Started Jul 11 06:50:26 PM PDT 24
Finished Jul 11 06:51:32 PM PDT 24
Peak memory 257116 kb
Host smart-d8248ed2-0e59-4e40-a607-2fd3f676edbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33611
73303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3361173303
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1813948761
Short name T374
Test name
Test status
Simulation time 269509472 ps
CPU time 15.79 seconds
Started Jul 11 06:50:22 PM PDT 24
Finished Jul 11 06:50:39 PM PDT 24
Peak memory 257368 kb
Host smart-901e83a5-b626-4ed8-b331-4dc63c044bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
48761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1813948761
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2108909324
Short name T584
Test name
Test status
Simulation time 8319061227 ps
CPU time 1035.15 seconds
Started Jul 11 06:50:27 PM PDT 24
Finished Jul 11 07:07:43 PM PDT 24
Peak memory 283948 kb
Host smart-deb94394-05d9-4430-acb0-18078c4ecc62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108909324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2108909324
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2975227963
Short name T431
Test name
Test status
Simulation time 10874533797 ps
CPU time 1117.36 seconds
Started Jul 11 06:50:39 PM PDT 24
Finished Jul 11 07:09:17 PM PDT 24
Peak memory 289956 kb
Host smart-f1c2b8cf-1587-421a-ba12-de50cfbb39f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975227963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2975227963
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1007402776
Short name T663
Test name
Test status
Simulation time 1789730003 ps
CPU time 96.4 seconds
Started Jul 11 06:50:31 PM PDT 24
Finished Jul 11 06:52:08 PM PDT 24
Peak memory 256956 kb
Host smart-27dd92e1-cb08-4053-94e4-fc39c7ca86d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10074
02776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1007402776
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3893271650
Short name T368
Test name
Test status
Simulation time 196744084 ps
CPU time 18.38 seconds
Started Jul 11 06:50:34 PM PDT 24
Finished Jul 11 06:50:53 PM PDT 24
Peak memory 249720 kb
Host smart-083495c9-400f-44a1-badf-a425d372a8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932
71650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3893271650
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3914169839
Short name T333
Test name
Test status
Simulation time 19168558954 ps
CPU time 1207.68 seconds
Started Jul 11 06:50:38 PM PDT 24
Finished Jul 11 07:10:47 PM PDT 24
Peak memory 273120 kb
Host smart-d7b305c6-0389-4c01-bdc7-0b0903ee5ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914169839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3914169839
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.772344468
Short name T96
Test name
Test status
Simulation time 39969213460 ps
CPU time 2454.67 seconds
Started Jul 11 06:50:37 PM PDT 24
Finished Jul 11 07:31:33 PM PDT 24
Peak memory 289532 kb
Host smart-e1a62c1a-7f04-4e68-acde-ae0d80b61550
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772344468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.772344468
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2999073367
Short name T544
Test name
Test status
Simulation time 139197584002 ps
CPU time 484.11 seconds
Started Jul 11 06:50:38 PM PDT 24
Finished Jul 11 06:58:43 PM PDT 24
Peak memory 249392 kb
Host smart-e8c81ec0-5de8-452f-8b82-4dca4e5772c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999073367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2999073367
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2944532293
Short name T460
Test name
Test status
Simulation time 1692514280 ps
CPU time 32.79 seconds
Started Jul 11 06:50:32 PM PDT 24
Finished Jul 11 06:51:05 PM PDT 24
Peak memory 256872 kb
Host smart-33d14eab-57de-41dc-aa00-c7ba86854218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29445
32293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2944532293
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.891729890
Short name T397
Test name
Test status
Simulation time 170474942 ps
CPU time 11.96 seconds
Started Jul 11 06:50:30 PM PDT 24
Finished Jul 11 06:50:43 PM PDT 24
Peak memory 249312 kb
Host smart-12522dc4-380e-4c83-b8ac-7e483fb29fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89172
9890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.891729890
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.279931203
Short name T269
Test name
Test status
Simulation time 1164998478 ps
CPU time 37.34 seconds
Started Jul 11 06:50:32 PM PDT 24
Finished Jul 11 06:51:10 PM PDT 24
Peak memory 257484 kb
Host smart-05dd5286-a0a7-4e7a-9634-e63d5cea3a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
1203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.279931203
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1630921546
Short name T632
Test name
Test status
Simulation time 2975706371 ps
CPU time 43.28 seconds
Started Jul 11 06:50:32 PM PDT 24
Finished Jul 11 06:51:16 PM PDT 24
Peak memory 256644 kb
Host smart-18ed906a-e74a-4089-aa5c-3bb4bace46b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
21546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1630921546
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3982870983
Short name T293
Test name
Test status
Simulation time 39747904425 ps
CPU time 2021.37 seconds
Started Jul 11 06:50:37 PM PDT 24
Finished Jul 11 07:24:19 PM PDT 24
Peak memory 298208 kb
Host smart-67514f34-296c-49ab-acd3-e365637b4725
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982870983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3982870983
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1854919977
Short name T35
Test name
Test status
Simulation time 15605072660 ps
CPU time 1894.69 seconds
Started Jul 11 06:50:48 PM PDT 24
Finished Jul 11 07:22:23 PM PDT 24
Peak memory 290180 kb
Host smart-65c64fe6-fd36-4173-b722-12778c361447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854919977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1854919977
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.217298985
Short name T295
Test name
Test status
Simulation time 11809909247 ps
CPU time 342.53 seconds
Started Jul 11 06:50:41 PM PDT 24
Finished Jul 11 06:56:25 PM PDT 24
Peak memory 257100 kb
Host smart-598fce89-8136-4d13-9866-ec9b4ca277a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21729
8985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.217298985
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2396802441
Short name T370
Test name
Test status
Simulation time 1615557411 ps
CPU time 50.83 seconds
Started Jul 11 06:50:41 PM PDT 24
Finished Jul 11 06:51:32 PM PDT 24
Peak memory 257444 kb
Host smart-3c1dca9f-d02c-479d-be2f-a7ec25a7808c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23968
02441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2396802441
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3450537592
Short name T336
Test name
Test status
Simulation time 155822713958 ps
CPU time 2239.14 seconds
Started Jul 11 06:50:46 PM PDT 24
Finished Jul 11 07:28:06 PM PDT 24
Peak memory 283684 kb
Host smart-5b0fc0e3-29e3-4efe-b01b-7cddbc679562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450537592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3450537592
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3809684660
Short name T624
Test name
Test status
Simulation time 97010813263 ps
CPU time 1441.76 seconds
Started Jul 11 06:50:52 PM PDT 24
Finished Jul 11 07:14:55 PM PDT 24
Peak memory 282220 kb
Host smart-37a8b00c-338e-4124-a45c-7a1ace04f4f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809684660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3809684660
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2165713583
Short name T676
Test name
Test status
Simulation time 6792714470 ps
CPU time 313.29 seconds
Started Jul 11 06:50:48 PM PDT 24
Finished Jul 11 06:56:02 PM PDT 24
Peak memory 249232 kb
Host smart-e9e4c792-09c6-45c6-b634-81010b06961b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165713583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2165713583
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4240065415
Short name T452
Test name
Test status
Simulation time 1568406499 ps
CPU time 23.88 seconds
Started Jul 11 06:50:43 PM PDT 24
Finished Jul 11 06:51:08 PM PDT 24
Peak memory 256532 kb
Host smart-3cb492fb-e2a6-4766-9a52-7c2019a90204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
65415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4240065415
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1650348187
Short name T640
Test name
Test status
Simulation time 506479615 ps
CPU time 16.87 seconds
Started Jul 11 06:50:43 PM PDT 24
Finished Jul 11 06:51:00 PM PDT 24
Peak memory 249328 kb
Host smart-c6e0a787-00b1-4efe-b26e-2378f5d6b34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503
48187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1650348187
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2686513561
Short name T87
Test name
Test status
Simulation time 521848529 ps
CPU time 37.62 seconds
Started Jul 11 06:50:46 PM PDT 24
Finished Jul 11 06:51:25 PM PDT 24
Peak memory 249256 kb
Host smart-ff5ab39f-6a15-4788-8ede-b0e7f797b6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26865
13561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2686513561
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3764691773
Short name T532
Test name
Test status
Simulation time 260512251 ps
CPU time 20.95 seconds
Started Jul 11 06:50:41 PM PDT 24
Finished Jul 11 06:51:02 PM PDT 24
Peak memory 257484 kb
Host smart-b9cda040-4c0b-467f-9153-17f6e52c1ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
91773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3764691773
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3447969432
Short name T119
Test name
Test status
Simulation time 55230631607 ps
CPU time 3333.33 seconds
Started Jul 11 06:50:51 PM PDT 24
Finished Jul 11 07:46:25 PM PDT 24
Peak memory 302144 kb
Host smart-28a72413-116c-4090-a461-f4a60d5f433c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447969432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3447969432
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.813160049
Short name T510
Test name
Test status
Simulation time 146137869007 ps
CPU time 1495.44 seconds
Started Jul 11 06:50:52 PM PDT 24
Finished Jul 11 07:15:48 PM PDT 24
Peak memory 290524 kb
Host smart-3efa14c7-900f-4dab-88bc-3158e4d369cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813160049 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.813160049
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1216657132
Short name T668
Test name
Test status
Simulation time 44858524454 ps
CPU time 1344.44 seconds
Started Jul 11 06:50:56 PM PDT 24
Finished Jul 11 07:13:21 PM PDT 24
Peak memory 288644 kb
Host smart-5b05385c-ca3c-45f4-bbfd-73b048ffe419
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216657132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1216657132
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4115471409
Short name T565
Test name
Test status
Simulation time 4460735120 ps
CPU time 270.96 seconds
Started Jul 11 06:50:57 PM PDT 24
Finished Jul 11 06:55:29 PM PDT 24
Peak memory 257152 kb
Host smart-2946a1b1-ac09-4cfd-b5ba-a0a4856429bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
71409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4115471409
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1662334764
Short name T464
Test name
Test status
Simulation time 377289504 ps
CPU time 28.47 seconds
Started Jul 11 06:50:56 PM PDT 24
Finished Jul 11 06:51:25 PM PDT 24
Peak memory 249856 kb
Host smart-961c7c86-6c60-4db4-b13d-4200a42cefc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16623
34764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1662334764
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3303902430
Short name T126
Test name
Test status
Simulation time 474343247090 ps
CPU time 2990.25 seconds
Started Jul 11 06:51:01 PM PDT 24
Finished Jul 11 07:40:52 PM PDT 24
Peak memory 289772 kb
Host smart-cd56176c-2fbb-40bd-8ef8-911aa8560c84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303902430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3303902430
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2245989641
Short name T558
Test name
Test status
Simulation time 2469377363 ps
CPU time 92.49 seconds
Started Jul 11 06:51:03 PM PDT 24
Finished Jul 11 06:52:36 PM PDT 24
Peak memory 256188 kb
Host smart-7c7a3836-b153-42d9-90f9-15f2728c66c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245989641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2245989641
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2224879390
Short name T471
Test name
Test status
Simulation time 1164500256 ps
CPU time 34.1 seconds
Started Jul 11 06:50:57 PM PDT 24
Finished Jul 11 06:51:32 PM PDT 24
Peak memory 256752 kb
Host smart-c97bef28-2f75-4502-a4b7-5495678b504a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248
79390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2224879390
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2753297730
Short name T616
Test name
Test status
Simulation time 5719839063 ps
CPU time 44.95 seconds
Started Jul 11 06:50:55 PM PDT 24
Finished Jul 11 06:51:40 PM PDT 24
Peak memory 256472 kb
Host smart-fa3789af-4785-4211-b5ea-4ffb015a0111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
97730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2753297730
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1025345952
Short name T570
Test name
Test status
Simulation time 251704734 ps
CPU time 30.66 seconds
Started Jul 11 06:50:57 PM PDT 24
Finished Jul 11 06:51:29 PM PDT 24
Peak memory 249260 kb
Host smart-5307472f-9de9-44da-96a2-2b5299feb7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10253
45952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1025345952
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2177453153
Short name T641
Test name
Test status
Simulation time 196589201 ps
CPU time 5.13 seconds
Started Jul 11 06:50:52 PM PDT 24
Finished Jul 11 06:50:58 PM PDT 24
Peak memory 249172 kb
Host smart-d405ef29-76bc-428b-9b75-a49e1259bec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21774
53153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2177453153
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3187862203
Short name T611
Test name
Test status
Simulation time 116731748487 ps
CPU time 3739.99 seconds
Started Jul 11 06:51:07 PM PDT 24
Finished Jul 11 07:53:28 PM PDT 24
Peak memory 306320 kb
Host smart-c37f5c33-02c0-4202-9351-132134db15d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187862203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3187862203
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2713266232
Short name T434
Test name
Test status
Simulation time 24496479226 ps
CPU time 1387.5 seconds
Started Jul 11 06:51:12 PM PDT 24
Finished Jul 11 07:14:20 PM PDT 24
Peak memory 289468 kb
Host smart-b929f82a-70ad-418a-a05d-5bd912aca6c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713266232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2713266232
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1162623716
Short name T407
Test name
Test status
Simulation time 80625785 ps
CPU time 3.74 seconds
Started Jul 11 06:51:11 PM PDT 24
Finished Jul 11 06:51:15 PM PDT 24
Peak memory 240192 kb
Host smart-094de509-d602-4ef6-b9ff-81c124e1be2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626
23716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1162623716
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3584605722
Short name T597
Test name
Test status
Simulation time 977014998 ps
CPU time 22.16 seconds
Started Jul 11 06:51:06 PM PDT 24
Finished Jul 11 06:51:29 PM PDT 24
Peak memory 249248 kb
Host smart-ea7877f3-6174-4a53-b7e2-8b7edf6b6313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
05722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3584605722
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3215426870
Short name T574
Test name
Test status
Simulation time 31526668670 ps
CPU time 2294.29 seconds
Started Jul 11 06:51:17 PM PDT 24
Finished Jul 11 07:29:32 PM PDT 24
Peak memory 285692 kb
Host smart-770d8fe9-0a67-4e19-ba8e-7c43ec80df46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215426870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3215426870
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.46221835
Short name T637
Test name
Test status
Simulation time 172745571112 ps
CPU time 2765.75 seconds
Started Jul 11 06:51:18 PM PDT 24
Finished Jul 11 07:37:25 PM PDT 24
Peak memory 287284 kb
Host smart-48d7a937-dd44-4883-9b50-4b18f4478cd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46221835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.46221835
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3889618139
Short name T105
Test name
Test status
Simulation time 2478954153 ps
CPU time 106.1 seconds
Started Jul 11 06:51:19 PM PDT 24
Finished Jul 11 06:53:06 PM PDT 24
Peak memory 249384 kb
Host smart-ac80f311-8b86-49af-9446-69e235a04785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889618139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3889618139
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3479971487
Short name T639
Test name
Test status
Simulation time 688407153 ps
CPU time 17.87 seconds
Started Jul 11 06:51:08 PM PDT 24
Finished Jul 11 06:51:27 PM PDT 24
Peak memory 256796 kb
Host smart-b88bf105-3290-4476-b3ba-3d9b0f480147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799
71487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3479971487
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2647400125
Short name T437
Test name
Test status
Simulation time 184368151 ps
CPU time 4.49 seconds
Started Jul 11 06:51:08 PM PDT 24
Finished Jul 11 06:51:13 PM PDT 24
Peak memory 241060 kb
Host smart-9566f7be-5e2f-44d9-87c6-0cceedfa992f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26474
00125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2647400125
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1975810001
Short name T509
Test name
Test status
Simulation time 75895232 ps
CPU time 3.32 seconds
Started Jul 11 06:51:12 PM PDT 24
Finished Jul 11 06:51:16 PM PDT 24
Peak memory 241116 kb
Host smart-17695ac6-2907-4ace-bc17-314ce5aba600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758
10001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1975810001
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.129154539
Short name T385
Test name
Test status
Simulation time 765751662 ps
CPU time 19.25 seconds
Started Jul 11 06:51:06 PM PDT 24
Finished Jul 11 06:51:27 PM PDT 24
Peak memory 249244 kb
Host smart-a251687f-c32b-433a-8cbb-79b054402adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12915
4539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.129154539
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3079242615
Short name T207
Test name
Test status
Simulation time 14304395112 ps
CPU time 1599.21 seconds
Started Jul 11 06:51:23 PM PDT 24
Finished Jul 11 07:18:03 PM PDT 24
Peak memory 289476 kb
Host smart-63764800-0ce9-46f8-a010-19776c19679f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079242615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3079242615
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2553907430
Short name T608
Test name
Test status
Simulation time 15929426827 ps
CPU time 1458.23 seconds
Started Jul 11 06:51:34 PM PDT 24
Finished Jul 11 07:15:53 PM PDT 24
Peak memory 289584 kb
Host smart-704c5927-57c0-4f13-93f7-b6aa21797a62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553907430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2553907430
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.703986235
Short name T414
Test name
Test status
Simulation time 2304009302 ps
CPU time 69.38 seconds
Started Jul 11 06:51:31 PM PDT 24
Finished Jul 11 06:52:40 PM PDT 24
Peak memory 257624 kb
Host smart-41aaf5fc-30c5-4de8-a23f-e7b0b7b67b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70398
6235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.703986235
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4030357131
Short name T479
Test name
Test status
Simulation time 1022406392 ps
CPU time 16.98 seconds
Started Jul 11 06:51:30 PM PDT 24
Finished Jul 11 06:51:47 PM PDT 24
Peak memory 249332 kb
Host smart-0908e5ff-def7-45b2-9be0-dfc0e11c5da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40303
57131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4030357131
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1346214718
Short name T217
Test name
Test status
Simulation time 60268529976 ps
CPU time 1249.72 seconds
Started Jul 11 06:51:35 PM PDT 24
Finished Jul 11 07:12:26 PM PDT 24
Peak memory 282608 kb
Host smart-ec2e9ed6-7faa-41a3-8510-65fb5fbc81bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346214718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1346214718
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3536565524
Short name T546
Test name
Test status
Simulation time 43883513863 ps
CPU time 967.91 seconds
Started Jul 11 06:51:35 PM PDT 24
Finished Jul 11 07:07:43 PM PDT 24
Peak memory 273988 kb
Host smart-dee48c6a-ee55-41cc-ad58-8a58b7e2e582
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536565524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3536565524
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2933087446
Short name T310
Test name
Test status
Simulation time 19146258444 ps
CPU time 210.92 seconds
Started Jul 11 06:51:34 PM PDT 24
Finished Jul 11 06:55:05 PM PDT 24
Peak memory 249220 kb
Host smart-b7d60b30-67fb-411b-b26e-cb2d5b7992b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933087446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2933087446
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.202988458
Short name T506
Test name
Test status
Simulation time 301012302 ps
CPU time 14.06 seconds
Started Jul 11 06:51:30 PM PDT 24
Finished Jul 11 06:51:45 PM PDT 24
Peak memory 256784 kb
Host smart-0542e931-ed82-4b0b-9bc2-3c6847a440ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20298
8458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.202988458
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3786126249
Short name T566
Test name
Test status
Simulation time 53161506 ps
CPU time 6.97 seconds
Started Jul 11 06:51:32 PM PDT 24
Finished Jul 11 06:51:39 PM PDT 24
Peak memory 248588 kb
Host smart-c39bdf99-f1c1-448d-8ea3-5d79da0f6707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
26249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3786126249
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2832529882
Short name T82
Test name
Test status
Simulation time 379928269 ps
CPU time 25.14 seconds
Started Jul 11 06:51:30 PM PDT 24
Finished Jul 11 06:51:56 PM PDT 24
Peak memory 256604 kb
Host smart-c2bfe9c2-cb56-40db-9b88-4f0f71c46a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28325
29882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2832529882
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1921504276
Short name T669
Test name
Test status
Simulation time 1621275422 ps
CPU time 25.61 seconds
Started Jul 11 06:51:30 PM PDT 24
Finished Jul 11 06:51:56 PM PDT 24
Peak memory 256568 kb
Host smart-d0145434-72d5-421e-a193-b65e348c8fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
04276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1921504276
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2549125888
Short name T128
Test name
Test status
Simulation time 49190851641 ps
CPU time 1084.89 seconds
Started Jul 11 06:51:35 PM PDT 24
Finished Jul 11 07:09:41 PM PDT 24
Peak memory 284136 kb
Host smart-7e10a731-acce-4d14-a912-cf226273f783
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549125888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2549125888
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.66828275
Short name T247
Test name
Test status
Simulation time 168805812187 ps
CPU time 2065.08 seconds
Started Jul 11 06:51:35 PM PDT 24
Finished Jul 11 07:26:01 PM PDT 24
Peak memory 282368 kb
Host smart-71a6ee9c-7f4d-4376-bf8f-36722c0187f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66828275 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.66828275
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1415346649
Short name T231
Test name
Test status
Simulation time 53541987 ps
CPU time 4.03 seconds
Started Jul 11 06:44:29 PM PDT 24
Finished Jul 11 06:44:34 PM PDT 24
Peak memory 249576 kb
Host smart-c2c553ce-917f-4fcd-867c-8f1625929ff6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1415346649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1415346649
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.623775642
Short name T586
Test name
Test status
Simulation time 93673412662 ps
CPU time 1662.75 seconds
Started Jul 11 06:44:29 PM PDT 24
Finished Jul 11 07:12:14 PM PDT 24
Peak memory 273764 kb
Host smart-9a1c6993-4e88-4752-b4de-3020e48d47e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623775642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.623775642
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3058344685
Short name T215
Test name
Test status
Simulation time 136680624 ps
CPU time 8.76 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:44:37 PM PDT 24
Peak memory 249188 kb
Host smart-2b93e98f-5243-46d9-9b19-c5719e96a407
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3058344685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3058344685
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1958829951
Short name T90
Test name
Test status
Simulation time 42834201204 ps
CPU time 360.82 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:50:29 PM PDT 24
Peak memory 257656 kb
Host smart-406b1895-ea53-4ae7-80b4-5794fe457213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19588
29951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1958829951
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2818279678
Short name T675
Test name
Test status
Simulation time 610042176 ps
CPU time 19.71 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 06:44:53 PM PDT 24
Peak memory 256860 kb
Host smart-a53f362f-7fb7-4cd0-b99d-858147a8817a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28182
79678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2818279678
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.628267059
Short name T627
Test name
Test status
Simulation time 21535166029 ps
CPU time 1464.4 seconds
Started Jul 11 06:44:30 PM PDT 24
Finished Jul 11 07:08:56 PM PDT 24
Peak memory 273352 kb
Host smart-b8a857e6-7995-4be2-9194-5c100f841b50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628267059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.628267059
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2061989333
Short name T238
Test name
Test status
Simulation time 26735315236 ps
CPU time 1650.06 seconds
Started Jul 11 06:44:29 PM PDT 24
Finished Jul 11 07:12:01 PM PDT 24
Peak memory 273904 kb
Host smart-c9e228a5-6e06-44c7-9bf3-1a24b209324f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061989333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2061989333
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1035652011
Short name T325
Test name
Test status
Simulation time 10730710324 ps
CPU time 116.83 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 06:46:27 PM PDT 24
Peak memory 248344 kb
Host smart-a1dd0387-d083-4fd9-8c57-344541d1d36e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035652011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1035652011
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4224620753
Short name T700
Test name
Test status
Simulation time 90342567 ps
CPU time 4.59 seconds
Started Jul 11 06:44:25 PM PDT 24
Finished Jul 11 06:44:31 PM PDT 24
Peak memory 241040 kb
Host smart-8aad2b5d-1f28-4fbf-894f-8557756bba5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42246
20753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4224620753
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3333415522
Short name T508
Test name
Test status
Simulation time 657784319 ps
CPU time 41.46 seconds
Started Jul 11 06:44:22 PM PDT 24
Finished Jul 11 06:45:05 PM PDT 24
Peak memory 256580 kb
Host smart-43e46443-9050-4d16-a7cd-982cfbca6ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33334
15522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3333415522
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4051108339
Short name T674
Test name
Test status
Simulation time 219047294 ps
CPU time 19.02 seconds
Started Jul 11 06:44:30 PM PDT 24
Finished Jul 11 06:44:50 PM PDT 24
Peak memory 257448 kb
Host smart-76345755-b956-4bed-ad4f-aba06380f163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
08339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4051108339
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.799494552
Short name T577
Test name
Test status
Simulation time 1684632334 ps
CPU time 31.44 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 249292 kb
Host smart-b1fe1efa-f190-44bc-aed1-231d17520d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79949
4552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.799494552
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2986005346
Short name T64
Test name
Test status
Simulation time 139744738611 ps
CPU time 2391.09 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 07:24:21 PM PDT 24
Peak memory 290264 kb
Host smart-111aaaaa-9b77-4de1-8b62-8d789407b32a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986005346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2986005346
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4107721399
Short name T232
Test name
Test status
Simulation time 510122949 ps
CPU time 3.46 seconds
Started Jul 11 06:44:30 PM PDT 24
Finished Jul 11 06:44:35 PM PDT 24
Peak memory 249556 kb
Host smart-02c73762-262a-4668-bd27-30019f9ace4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4107721399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4107721399
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1052115977
Short name T298
Test name
Test status
Simulation time 22352142822 ps
CPU time 1575.64 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 07:10:45 PM PDT 24
Peak memory 273908 kb
Host smart-c291ed27-1a45-4327-8444-9bbfa600e4c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052115977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1052115977
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.486657607
Short name T563
Test name
Test status
Simulation time 1268110661 ps
CPU time 54.08 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 06:45:27 PM PDT 24
Peak memory 249308 kb
Host smart-5713c13e-fe68-4d3c-91f9-d77e227efa99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=486657607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.486657607
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3126231169
Short name T49
Test name
Test status
Simulation time 6680885446 ps
CPU time 94.69 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 06:46:04 PM PDT 24
Peak memory 257572 kb
Host smart-ea3fce10-b879-4b54-b94d-790575ec2634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31262
31169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3126231169
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.609571930
Short name T83
Test name
Test status
Simulation time 1028295417 ps
CPU time 63.24 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 06:45:33 PM PDT 24
Peak memory 256116 kb
Host smart-089bd8d3-b99f-438d-973d-a29a50b301e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60957
1930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.609571930
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3350833827
Short name T324
Test name
Test status
Simulation time 38729538488 ps
CPU time 1915.61 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 07:16:41 PM PDT 24
Peak memory 273904 kb
Host smart-67b9fb41-7dcc-447a-96a9-82c98812cc7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350833827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3350833827
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2597093273
Short name T213
Test name
Test status
Simulation time 193360290511 ps
CPU time 3106.58 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 07:36:20 PM PDT 24
Peak memory 290104 kb
Host smart-d3c6bb40-83cb-4d76-83f9-e0415a261ba4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597093273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2597093273
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3045123130
Short name T12
Test name
Test status
Simulation time 9328962842 ps
CPU time 353.13 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:50:22 PM PDT 24
Peak memory 249404 kb
Host smart-c7278761-530b-40ad-b687-5499b606f005
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045123130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3045123130
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.971803801
Short name T457
Test name
Test status
Simulation time 1170535657 ps
CPU time 28.96 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 06:44:59 PM PDT 24
Peak memory 249192 kb
Host smart-16db71f2-7fd0-43e2-b677-7982d6d94f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97180
3801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.971803801
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3291492561
Short name T691
Test name
Test status
Simulation time 1188055918 ps
CPU time 31.16 seconds
Started Jul 11 06:44:27 PM PDT 24
Finished Jul 11 06:44:59 PM PDT 24
Peak memory 249216 kb
Host smart-171d7f92-a4e3-4033-b8fd-79ccf37f8fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
92561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3291492561
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3127977317
Short name T278
Test name
Test status
Simulation time 1101556529 ps
CPU time 62.85 seconds
Started Jul 11 06:44:28 PM PDT 24
Finished Jul 11 06:45:32 PM PDT 24
Peak memory 256844 kb
Host smart-36a6e880-183d-4402-a809-3aa6f3e1e326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31279
77317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3127977317
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2714501033
Short name T670
Test name
Test status
Simulation time 1129955901 ps
CPU time 19.76 seconds
Started Jul 11 06:44:26 PM PDT 24
Finished Jul 11 06:44:47 PM PDT 24
Peak memory 256592 kb
Host smart-a82258f9-c077-4995-a751-2e4741e79afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27145
01033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2714501033
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.670417992
Short name T634
Test name
Test status
Simulation time 4297712957 ps
CPU time 253.96 seconds
Started Jul 11 06:44:44 PM PDT 24
Finished Jul 11 06:49:00 PM PDT 24
Peak memory 257572 kb
Host smart-a87554ca-010c-4420-813a-be5ffbe416be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670417992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.670417992
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.725495377
Short name T60
Test name
Test status
Simulation time 1255301917011 ps
CPU time 8893.44 seconds
Started Jul 11 06:44:32 PM PDT 24
Finished Jul 11 09:12:48 PM PDT 24
Peak memory 371776 kb
Host smart-97e7168f-db17-4de7-8916-8e9004d5703b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725495377 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.725495377
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.963335266
Short name T224
Test name
Test status
Simulation time 34904746 ps
CPU time 3.92 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 06:44:36 PM PDT 24
Peak memory 249604 kb
Host smart-238acd5d-8c0f-473b-8a8e-201d576f7a9c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=963335266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.963335266
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3787769423
Short name T572
Test name
Test status
Simulation time 48313577499 ps
CPU time 1501.48 seconds
Started Jul 11 06:44:33 PM PDT 24
Finished Jul 11 07:09:36 PM PDT 24
Peak memory 273944 kb
Host smart-14657af1-9cef-44ab-98b8-02959beea6c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787769423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3787769423
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3560033182
Short name T214
Test name
Test status
Simulation time 4876043131 ps
CPU time 56.8 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 06:45:30 PM PDT 24
Peak memory 249396 kb
Host smart-c0dbd9d4-4b4a-4dc0-9301-a408f2df0ac0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3560033182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3560033182
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.4135247879
Short name T93
Test name
Test status
Simulation time 6197375291 ps
CPU time 154.42 seconds
Started Jul 11 06:44:32 PM PDT 24
Finished Jul 11 06:47:08 PM PDT 24
Peak memory 257160 kb
Host smart-25bb5d9d-ad03-496b-a3d0-69266c1b9cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
47879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.4135247879
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2284118514
Short name T79
Test name
Test status
Simulation time 528383590 ps
CPU time 34.72 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:45:17 PM PDT 24
Peak memory 257032 kb
Host smart-cabf8d2a-1a17-4f4b-a51d-346ac61e2110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22841
18514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2284118514
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1480743438
Short name T345
Test name
Test status
Simulation time 9129062445 ps
CPU time 692.98 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:56:13 PM PDT 24
Peak memory 272900 kb
Host smart-9b354760-84e8-4894-b454-5f94e2338731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480743438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1480743438
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2980311424
Short name T315
Test name
Test status
Simulation time 56569699043 ps
CPU time 634.34 seconds
Started Jul 11 06:44:32 PM PDT 24
Finished Jul 11 06:55:08 PM PDT 24
Peak memory 249420 kb
Host smart-87f9253a-0694-4035-9043-0fb1b50c3ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980311424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2980311424
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.43552886
Short name T386
Test name
Test status
Simulation time 226176678 ps
CPU time 14.85 seconds
Started Jul 11 06:44:40 PM PDT 24
Finished Jul 11 06:44:56 PM PDT 24
Peak memory 249312 kb
Host smart-a2e17a93-9075-446d-872d-fd1259e9873f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43552
886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.43552886
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3680175339
Short name T274
Test name
Test status
Simulation time 320696258 ps
CPU time 20.19 seconds
Started Jul 11 06:44:32 PM PDT 24
Finished Jul 11 06:44:54 PM PDT 24
Peak memory 248936 kb
Host smart-1a82f53c-c641-49ea-934b-70e3ca5f3d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
75339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3680175339
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1587947337
Short name T417
Test name
Test status
Simulation time 1773543032 ps
CPU time 26.22 seconds
Started Jul 11 06:44:33 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 256900 kb
Host smart-c8f31924-221c-4ab8-834f-f479ce0f8674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
47337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1587947337
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1704294095
Short name T364
Test name
Test status
Simulation time 486727701 ps
CPU time 8.9 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 06:44:41 PM PDT 24
Peak memory 251516 kb
Host smart-534a1748-067a-4101-8a6d-f9dcbeb86e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17042
94095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1704294095
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2115684140
Short name T107
Test name
Test status
Simulation time 51410511469 ps
CPU time 1288.38 seconds
Started Jul 11 06:44:31 PM PDT 24
Finished Jul 11 07:06:01 PM PDT 24
Peak memory 286508 kb
Host smart-0e173f21-4e74-4e04-8281-5e8acaac0236
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115684140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2115684140
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1800849497
Short name T101
Test name
Test status
Simulation time 120444050063 ps
CPU time 3343.43 seconds
Started Jul 11 06:44:32 PM PDT 24
Finished Jul 11 07:40:17 PM PDT 24
Peak memory 339232 kb
Host smart-4740006c-bb84-4b62-a5c6-7a228e1ebc37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800849497 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1800849497
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1754284559
Short name T219
Test name
Test status
Simulation time 64732752 ps
CPU time 3.7 seconds
Started Jul 11 06:44:40 PM PDT 24
Finished Jul 11 06:44:45 PM PDT 24
Peak memory 249608 kb
Host smart-5b52eb36-13cd-4eb0-a94f-8a004c59d5d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1754284559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1754284559
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3609726037
Short name T549
Test name
Test status
Simulation time 459864925709 ps
CPU time 2990.37 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 07:34:35 PM PDT 24
Peak memory 290324 kb
Host smart-6e45fdd4-cd90-40af-badd-e12dd843c71b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609726037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3609726037
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2687647780
Short name T445
Test name
Test status
Simulation time 838988994 ps
CPU time 20.99 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:45:01 PM PDT 24
Peak memory 249216 kb
Host smart-2474410d-9ddc-421f-84fc-01f12107863a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2687647780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2687647780
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1315779830
Short name T39
Test name
Test status
Simulation time 84352152 ps
CPU time 9.56 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:44:50 PM PDT 24
Peak memory 256664 kb
Host smart-d5c6909f-d15d-4636-b044-4e49c66a455a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157
79830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1315779830
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1875029726
Short name T693
Test name
Test status
Simulation time 366566632 ps
CPU time 20.41 seconds
Started Jul 11 06:44:37 PM PDT 24
Finished Jul 11 06:44:58 PM PDT 24
Peak memory 256596 kb
Host smart-88ce13ef-a42a-4452-8997-97603ee6ab0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
29726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1875029726
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.561791880
Short name T343
Test name
Test status
Simulation time 374840735270 ps
CPU time 2190.49 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 07:21:15 PM PDT 24
Peak memory 283148 kb
Host smart-9b578b0e-a3cf-4496-9bf3-8476e25ceca6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561791880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.561791880
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1120682351
Short name T301
Test name
Test status
Simulation time 33064005170 ps
CPU time 2223.39 seconds
Started Jul 11 06:44:40 PM PDT 24
Finished Jul 11 07:21:44 PM PDT 24
Peak memory 289684 kb
Host smart-12e59e0e-a1b9-4531-a1f4-7ff5de27f257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120682351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1120682351
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2465617871
Short name T661
Test name
Test status
Simulation time 10330929579 ps
CPU time 259.47 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:49:02 PM PDT 24
Peak memory 249344 kb
Host smart-eb7a7f38-4297-4a96-9a43-93ba8780ee7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465617871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2465617871
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2431418701
Short name T559
Test name
Test status
Simulation time 3207638804 ps
CPU time 52.16 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 06:45:36 PM PDT 24
Peak memory 256828 kb
Host smart-a38ae8bd-aa1c-46c8-9978-8c9e8d21d8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24314
18701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2431418701
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1371913124
Short name T61
Test name
Test status
Simulation time 1635792604 ps
CPU time 27.29 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:45:07 PM PDT 24
Peak memory 256012 kb
Host smart-126afb1a-b92a-4333-9bd2-bbaf87fef95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13719
13124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1371913124
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1620779933
Short name T562
Test name
Test status
Simulation time 704322012 ps
CPU time 17.65 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 249140 kb
Host smart-933e490a-9957-4f3d-950a-deb6983f7f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16207
79933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1620779933
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3884223603
Short name T557
Test name
Test status
Simulation time 4971400099 ps
CPU time 61.06 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 06:45:44 PM PDT 24
Peak memory 257512 kb
Host smart-b12850a5-c40d-47b7-9e3d-4e9283fbd8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
23603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3884223603
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2666049671
Short name T114
Test name
Test status
Simulation time 39942265387 ps
CPU time 1532.66 seconds
Started Jul 11 06:44:41 PM PDT 24
Finished Jul 11 07:10:16 PM PDT 24
Peak memory 289760 kb
Host smart-c7d53409-d703-4759-a7a4-df9b8064f7b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666049671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2666049671
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1993284302
Short name T63
Test name
Test status
Simulation time 299581388637 ps
CPU time 5899.45 seconds
Started Jul 11 06:44:46 PM PDT 24
Finished Jul 11 08:23:08 PM PDT 24
Peak memory 355252 kb
Host smart-9f0a433a-f656-4388-ac0c-0b5e519ca58c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993284302 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1993284302
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1821854420
Short name T225
Test name
Test status
Simulation time 30082224 ps
CPU time 2.9 seconds
Started Jul 11 06:44:45 PM PDT 24
Finished Jul 11 06:44:50 PM PDT 24
Peak memory 249508 kb
Host smart-0afe2da7-5c2e-448c-bf34-5fde6fdfbaa9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1821854420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1821854420
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2240242324
Short name T435
Test name
Test status
Simulation time 17986674700 ps
CPU time 622.69 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:55:02 PM PDT 24
Peak memory 265744 kb
Host smart-102b9d10-2566-44ac-90c0-4a273d4550b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240242324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2240242324
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1056929391
Short name T438
Test name
Test status
Simulation time 131681503 ps
CPU time 8.44 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:44:49 PM PDT 24
Peak memory 249292 kb
Host smart-e76d2cf4-42af-4939-8012-2a6d74b6f70d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1056929391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1056929391
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3409757592
Short name T520
Test name
Test status
Simulation time 1564839484 ps
CPU time 60.99 seconds
Started Jul 11 06:44:35 PM PDT 24
Finished Jul 11 06:45:36 PM PDT 24
Peak memory 256764 kb
Host smart-353b12be-3610-44d0-9c57-b5628fadbbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
57592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3409757592
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1117160134
Short name T554
Test name
Test status
Simulation time 224165137 ps
CPU time 7.05 seconds
Started Jul 11 06:44:38 PM PDT 24
Finished Jul 11 06:44:46 PM PDT 24
Peak memory 249208 kb
Host smart-6e4130e5-5bfa-4c0e-b488-d51a8e479758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
60134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1117160134
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.118783529
Short name T309
Test name
Test status
Simulation time 46512365785 ps
CPU time 534.66 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:53:34 PM PDT 24
Peak memory 256064 kb
Host smart-f641fc44-67bf-4bff-8023-619e92ec21a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118783529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.118783529
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.805965312
Short name T602
Test name
Test status
Simulation time 470808843 ps
CPU time 27.93 seconds
Started Jul 11 06:44:39 PM PDT 24
Finished Jul 11 06:45:08 PM PDT 24
Peak memory 257412 kb
Host smart-0bd8aec1-0fce-4f35-b5cc-6e9e5db7ed85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80596
5312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.805965312
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3505174575
Short name T531
Test name
Test status
Simulation time 1053542124 ps
CPU time 70.35 seconds
Started Jul 11 06:44:38 PM PDT 24
Finished Jul 11 06:45:49 PM PDT 24
Peak memory 257512 kb
Host smart-03e5cd08-9f45-470e-9682-dbbc50bb4514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35051
74575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3505174575
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.100537836
Short name T260
Test name
Test status
Simulation time 768250485 ps
CPU time 15.75 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 06:45:00 PM PDT 24
Peak memory 256896 kb
Host smart-d8ebe288-0e44-4661-920e-f5981162c4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053
7836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.100537836
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3814313328
Short name T203
Test name
Test status
Simulation time 654019666 ps
CPU time 11.85 seconds
Started Jul 11 06:44:46 PM PDT 24
Finished Jul 11 06:44:59 PM PDT 24
Peak memory 256572 kb
Host smart-17bb3265-4edb-493e-8235-70a2e0a6deb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143
13328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3814313328
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2829651211
Short name T2
Test name
Test status
Simulation time 16050806094 ps
CPU time 332.79 seconds
Started Jul 11 06:44:42 PM PDT 24
Finished Jul 11 06:50:16 PM PDT 24
Peak memory 257640 kb
Host smart-8a775d2e-beee-449a-9c7c-5a49c54e5240
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829651211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2829651211
Directory /workspace/9.alert_handler_stress_all/latest
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