Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	96220	1			T5	1		T35	6		T20	726
class_i[0x1]	54474	1			T2	15		T38	916		T22	36
class_i[0x2]	64140	1			T5	8		T8	4724		T35	6
class_i[0x3]	71391	1			T2	7		T38	1848		T10	11

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	70394	1			T2	10		T5	3		T8	1149
alert[0x1]	74233	1			T2	4		T5	3		T8	1136
alert[0x2]	71248	1			T2	2		T5	2		T8	1187
alert[0x3]	70350	1			T2	6		T5	1		T8	1252

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

285952

1

T2

15

T8

4724

T35

12

esc_ping_fail

273

1

T2

7

T5

9

T10

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	70312	1			T2	7		T8	1149		T35	2
esc_integrity_fail	alert[0x1]	74170	1			T2	3		T8	1136		T35	1
esc_integrity_fail	alert[0x2]	71173	1			T2	1		T8	1187		T35	7
esc_integrity_fail	alert[0x3]	70297	1			T2	4		T8	1252		T35	2
esc_ping_fail	alert[0x0]	82	1			T2	3		T5	3		T10	2
esc_ping_fail	alert[0x1]	63	1			T2	1		T5	3		T16	3
esc_ping_fail	alert[0x2]	75	1			T2	1		T5	2		T10	1
esc_ping_fail	alert[0x3]	53	1			T2	2		T5	1		T220	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	96160	1			T35	6		T20	726		T22	26
esc_integrity_fail	class_i[0x1]	54425	1			T2	15		T38	916		T22	36
esc_integrity_fail	class_i[0x2]	64040	1			T8	4724		T35	6		T22	46
esc_integrity_fail	class_i[0x3]	71327	1			T38	1848		T10	8		T22	2678
esc_ping_fail	class_i[0x0]	60	1			T5	1		T285	4		T267	6
esc_ping_fail	class_i[0x1]	49	1			T220	8		T271	1		T286	1
esc_ping_fail	class_i[0x2]	100	1			T5	8		T16	8		T271	7
esc_ping_fail	class_i[0x3]	64	1			T2	7		T10	3		T291	1