Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	696279621	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	696279621	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	696279621	696143932	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	696279621	696143932	0	0
tb.dut.EdnKnownO_A	0	0	696279621	696143932	0	0
tb.dut.EscPKnownO_A	0	0	696279621	696143932	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	696279621	50	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	696279621	50	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	696279621	50	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	696279621	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	696279621	50	0	0
tb.dut.IrqAKnownO_A	0	0	696279621	696143932	0	0
tb.dut.IrqBKnownO_A	0	0	696279621	696143932	0	0
tb.dut.IrqCKnownO_A	0	0	696279621	696143932	0	0
tb.dut.IrqDKnownO_A	0	0	696279621	696143932	0	0
tb.dut.TlAReadyKnownO_A	0	0	696279621	696143932	0	0
tb.dut.TlDValidKnownO_A	0	0	696279621	696143932	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	718980586	2589959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	718980586	8297	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	718980586	9560	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	718980586	8813	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	718980586	8999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	718980586	10487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	718980586	7977	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	718980586	8277	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	718980586	8209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	718980586	8141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	718980586	9350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	718980586	8299	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	718980586	10208	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	718980586	9392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	718980586	8246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	718980586	10004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	718980586	8164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	718980586	10483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	718980586	9550	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	718980586	9831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	718980586	8628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	718980586	9424	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	718980586	9838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	718980586	9142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	718980586	8118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	718980586	8672	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	718980586	8338	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	718980586	9921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	718980586	8136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	718980586	8184	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	718980586	8862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	718980586	8703	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	718980586	9233	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	718980586	8242	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	718980586	8646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	718980586	8458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	718980586	9707	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	718980586	9189	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	718980586	9231	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	718980586	8912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	718980586	8336	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	718980586	9383	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	718980586	8264	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	718980586	8326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	718980586	8940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	718980586	9845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	718980586	8355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	718980586	8855	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	718980586	8117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	718980586	8960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	718980586	9130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	718980586	9218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	718980586	9925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	718980586	8303	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	718980586	9186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	718980586	7904	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	718980586	7845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	718980586	9454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	718980586	9726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	718980586	9539	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	718980586	8239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	718980586	8990	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	718980586	8682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	718980586	10302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	718980586	8426	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	718980586	9366	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	718980586	9335	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	718980586	9252	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	718980586	10078	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	718980586	9403	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	718980586	13714	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	718980586	8342	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	718980586	8320	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	718980586	10283	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	718980586	8987	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	718980586	8320	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	718980586	8221	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	718980586	8442	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	718980586	8565	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	696279621	1883	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	696279621	267392	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	696279621	328686840	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	696279621	162	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	696279621	824	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	696279621	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	696279621	398	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	696137851	249546393	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	696279621	922	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	696279621	895	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	696279621	869	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	696279621	845	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	696279621	2105	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	696279621	238412	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	696279621	1997	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	696279621	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696279621	863	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	696279621	713	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	696136492	696064516	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	696279621	696143932	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	696279621	7784	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	696279621	211772	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	696279621	406000781	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	696279621	178	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	696279621	485	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	696279621	24	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	696279621	236	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	696137851	327059724	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	696279621	564	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	696279621	551	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	696279621	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	696279621	524	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	696279621	1059	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	696279621	133088	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	696279621	969	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	696279621	65	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696279621	950	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	696279621	800	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	696136492	696064516	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	696279621	696143932	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	696279621	3065	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	696279621	174554	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	696279621	392671794	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	696279621	183	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	696279621	504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	696279621	29	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	696279621	225	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	696137851	285867215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	696279621	588	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	696279621	584	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	696279621	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	696279621	563	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	696279621	1838	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	696279621	134191	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	696279621	1745	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	696279621	63	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696279621	879	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	696279621	729	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	696136492	696064516	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	696279621	696143932	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	696279621	50	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	696279621	5001	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	696279621	238596	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	696279621	379189343	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	696279621	186	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	696279621	542	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	696279621	21	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	696279621	256	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	696137851	287833970	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	696279621	614	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	696279621	606	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	696279621	596	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	696279621	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	696279621	1346	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	696279621	156260	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	696279621	1262	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	696279621	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696279621	903	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	696279621	753	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	696136492	696064516	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	696279621	696143932	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	718980586	122889220	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	718980586	718327222	0	0
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