Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T19	1		T38	1		T22	1
class_index[0x1]	65	1			T20	1		T22	2		T70	1
class_index[0x2]	63	1			T18	1		T38	1		T22	2
class_index[0x3]	62	1			T38	1		T22	1		T44	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T19	1		T20	1		T38	2
intr_timeout_cnt[1]	61	1			T18	1		T38	1		T22	1
intr_timeout_cnt[2]	22	1			T22	2		T28	1		T79	2
intr_timeout_cnt[3]	22	1			T29	2		T81	4		T112	1
intr_timeout_cnt[4]	18	1			T67	1		T112	1		T232	1
intr_timeout_cnt[5]	10	1			T80	1		T231	1		T58	1
intr_timeout_cnt[6]	3	1			T233	1		T234	1		T235	1
intr_timeout_cnt[7]	9	1			T44	1		T86	1		T236	1
intr_timeout_cnt[8]	5	1			T29	1		T237	1		T107	1
intr_timeout_cnt[9]	4	1			T22	1		T44	1		T81	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T19	1		T38	1		T45	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T48	2		T238	1		T239	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T22	1		T87	1		T240	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T29	2		T81	1		T241	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T242	1		T224	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T80	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T233	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T243	1		T244	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T237	1		T107	1		T245	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T81	1		T246	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	29	1			T20	1		T70	1		T75	1
class_index[0x1]	intr_timeout_cnt[1]	11	1			T22	1		T28	5		T78	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T87	2		T247	2		-	-
class_index[0x1]	intr_timeout_cnt[3]	7	1			T81	2		T85	1		T87	1
class_index[0x1]	intr_timeout_cnt[4]	7	1			T232	1		T87	1		T244	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T248	1		T249	1		T235	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T86	1		T236	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T29	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T22	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	30	1			T22	2		T74	1		T51	2
class_index[0x2]	intr_timeout_cnt[1]	13	1			T18	1		T38	1		T78	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T28	1		T79	1		T173	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T112	1		T223	1		T245	3
class_index[0x2]	intr_timeout_cnt[4]	4	1			T67	1		T250	1		T245	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T234	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T246	2		T224	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T44	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	12	1			T38	1		T53	1		T110	1
class_index[0x3]	intr_timeout_cnt[1]	25	1			T79	1		T80	1		T81	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T22	1		T79	1		T109	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T81	1		T58	1		T251	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T112	1		T86	1		T252	1
class_index[0x3]	intr_timeout_cnt[5]	6	1			T231	1		T58	1		T253	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T235	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T44	1		T254	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T255	1		-	-		-	-