Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343101	1			T1	25		T2	53		T6	5
all_values[1]	343101	1			T1	25		T2	53		T6	5
all_values[2]	343101	1			T1	25		T2	53		T6	5
all_values[3]	343101	1			T1	25		T2	53		T6	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684154

1

T1

37

T6

15

T17

10

auto[1]

688250

1

T1

63

T2

212

T6

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

808103

1

T1

52

T2

179

T6

12

auto[1]

564301

1

T1

48

T2

33

T6

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97766	1			T1	3		T6	1		T17	2
all_values[0]	auto[0]	auto[1]	73184	1			T1	3		T6	1		T17	2
all_values[0]	auto[1]	auto[0]	98774	1			T1	10		T2	38		T6	2
all_values[0]	auto[1]	auto[1]	73377	1			T1	9		T2	15		T6	1
all_values[1]	auto[0]	auto[0]	101994	1			T1	7		T6	3		T17	2
all_values[1]	auto[0]	auto[1]	69221	1			T1	6		T6	2		T4	91
all_values[1]	auto[1]	auto[0]	102709	1			T1	6		T2	45		T17	7
all_values[1]	auto[1]	auto[1]	69177	1			T1	6		T2	8		T4	108
all_values[2]	auto[0]	auto[0]	100735	1			T1	3		T6	2		T17	4
all_values[2]	auto[0]	auto[1]	70423	1			T1	3		T6	1		T4	205
all_values[2]	auto[1]	auto[0]	101957	1			T1	10		T2	52		T6	1
all_values[2]	auto[1]	auto[1]	69986	1			T1	9		T2	1		T6	1
all_values[3]	auto[0]	auto[0]	101324	1			T1	6		T6	3		T4	219
all_values[3]	auto[0]	auto[1]	69507	1			T1	6		T6	2		T4	206
all_values[3]	auto[1]	auto[0]	102844	1			T1	7		T2	44		T17	9
all_values[3]	auto[1]	auto[1]	69426	1			T1	6		T2	9		T4	205