Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343101	1			T1	25		T2	53		T6	5
all_pins[1]	343101	1			T1	25		T2	53		T6	5
all_pins[2]	343101	1			T1	25		T2	53		T6	5
all_pins[3]	343101	1			T1	25		T2	53		T6	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1090438	1			T1	70		T2	179		T6	18
values[0x1]	281966	1			T1	30		T2	33		T6	2
transitions[0x0=>0x1]	187153	1			T1	16		T2	32		T6	2
transitions[0x1=>0x0]	187406	1			T1	16		T2	33		T6	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	269724	1			T1	16		T2	38		T6	4
all_pins[0]	values[0x1]	73377	1			T1	9		T2	15		T6	1
all_pins[0]	transitions[0x0=>0x1]	72738	1			T1	9		T2	14		T6	1
all_pins[0]	transitions[0x1=>0x0]	69040	1			T1	6		T2	9		T4	205
all_pins[1]	values[0x0]	273924	1			T1	19		T2	45		T6	5
all_pins[1]	values[0x1]	69177	1			T1	6		T2	8		T4	108
all_pins[1]	transitions[0x0=>0x1]	37629	1			T1	2		T2	8		T4	45
all_pins[1]	transitions[0x1=>0x0]	41829	1			T1	5		T2	15		T6	1
all_pins[2]	values[0x0]	273115	1			T1	16		T2	52		T6	4
all_pins[2]	values[0x1]	69986	1			T1	9		T2	1		T6	1
all_pins[2]	transitions[0x0=>0x1]	38934	1			T1	5		T2	1		T6	1
all_pins[2]	transitions[0x1=>0x0]	38125	1			T1	2		T2	8		T4	48
all_pins[3]	values[0x0]	273675	1			T1	19		T2	44		T6	5
all_pins[3]	values[0x1]	69426	1			T1	6		T2	9		T4	205
all_pins[3]	transitions[0x0=>0x1]	37852	1			T2	9		T4	105		T18	2
all_pins[3]	transitions[0x1=>0x0]	38412	1			T1	3		T2	1		T6	1