Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	85079	1			T4	78		T8	73		T22	104
accum_cnt_1000	222719	1			T4	1044		T8	1096		T14	88
accum_cnt_100	26899	1			T4	59		T8	56		T14	52
accum_cnt_50	64509	1			T1	40		T2	13		T4	50
accum_cnt_10	187797	1			T1	27		T2	91		T6	5
accum_cnt_0	373630	1			T1	29		T2	52		T6	11

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	253506	1			T1	24		T2	39		T6	4
class_index[0x1]	253506	1			T1	24		T2	39		T6	4
class_index[0x2]	253506	1			T1	24		T2	39		T6	4
class_index[0x3]	253506	1			T1	24		T2	39		T6	4

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22704	1			T42	77		T30	177		T43	518
class_index[0x0]	accum_cnt_1000	56648	1			T20	195		T15	1005		T22	63
class_index[0x0]	accum_cnt_100	6955	1			T20	22		T15	73		T38	18
class_index[0x0]	accum_cnt_50	17095	1			T1	14		T2	9		T8	39
class_index[0x0]	accum_cnt_10	56041	1			T1	8		T2	30		T6	1
class_index[0x0]	accum_cnt_0	77163	1			T1	2		T6	3		T17	1
class_index[0x1]	accum_cnt_2000	20209	1			T64	480		T65	279		T27	194
class_index[0x1]	accum_cnt_1000	50639	1			T9	1103		T22	50		T64	432
class_index[0x1]	accum_cnt_100	5646	1			T9	153		T39	20		T22	22
class_index[0x1]	accum_cnt_50	19376	1			T2	4		T8	16		T20	5
class_index[0x1]	accum_cnt_10	34900	1			T2	31		T6	2		T4	620
class_index[0x1]	accum_cnt_0	110836	1			T1	24		T2	4		T6	2
class_index[0x2]	accum_cnt_2000	20871	1			T4	78		T219	372		T43	507
class_index[0x2]	accum_cnt_1000	57986	1			T4	486		T14	50		T9	1258
class_index[0x2]	accum_cnt_100	6914	1			T4	29		T14	22		T9	77
class_index[0x2]	accum_cnt_50	15346	1			T1	12		T4	24		T18	16
class_index[0x2]	accum_cnt_10	48886	1			T1	10		T2	30		T6	2
class_index[0x2]	accum_cnt_0	93841	1			T1	2		T2	9		T6	2
class_index[0x3]	accum_cnt_2000	21295	1			T8	73		T22	104		T42	530
class_index[0x3]	accum_cnt_1000	57446	1			T4	558		T8	1096		T14	38
class_index[0x3]	accum_cnt_100	7384	1			T4	30		T8	56		T14	30
class_index[0x3]	accum_cnt_50	12692	1			T1	14		T4	26		T8	64
class_index[0x3]	accum_cnt_10	47970	1			T1	9		T4	7		T18	18
class_index[0x3]	accum_cnt_0	91790	1			T1	1		T2	39		T6	4