Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8366	1			T22	1878		T28	4		T220	1
alert[0x1]	5211	1			T22	595		T42	34		T67	3
alert[0x2]	17985	1			T22	990		T42	7265		T220	1
alert[0x3]	6070	1			T16	1		T22	1		T42	75
alert[0x4]	10079	1			T5	1		T38	18		T42	135
alert[0x5]	12922	1			T5	1		T9	1		T10	1
alert[0x6]	5586	1			T16	1		T74	27		T45	62
alert[0x7]	6405	1			T2	1		T5	1		T38	6
alert[0x8]	3828	1			T16	1		T42	44		T30	1
alert[0x9]	5129	1			T22	1		T74	1517		T75	63
alert[0xa]	6342	1			T16	2		T65	8		T74	866
alert[0xb]	8202	1			T16	1		T22	10		T28	40
alert[0xc]	14594	1			T10	1		T65	3		T67	4
alert[0xd]	11922	1			T38	1		T16	1		T42	5
alert[0xe]	3411	1			T38	3		T10	1		T16	1
alert[0xf]	6330	1			T2	1		T74	19		T75	5
alert[0x10]	3768	1			T22	14		T42	11		T28	3
alert[0x11]	16270	1			T2	1		T38	1		T22	59
alert[0x12]	18639	1			T65	15		T43	1445		T45	28
alert[0x13]	9458	1			T5	2		T16	1		T43	21
alert[0x14]	6336	1			T2	3		T15	1		T38	2
alert[0x15]	7797	1			T5	1		T22	218		T43	30
alert[0x16]	9585	1			T38	1		T42	14		T43	133
alert[0x17]	11186	1			T5	3		T22	47		T42	147
alert[0x18]	6250	1			T2	1		T67	1		T30	3
alert[0x19]	3678	1			T30	1		T285	1		T45	70
alert[0x1a]	4096	1			T10	1		T28	6		T43	8
alert[0x1b]	17480	1			T16	1		T28	6		T74	14
alert[0x1c]	7950	1			T2	1		T43	117		T45	192
alert[0x1d]	9567	1			T2	2		T16	1		T22	25
alert[0x1e]	3762	1			T22	127		T220	1		T43	59
alert[0x1f]	4173	1			T2	1		T22	26		T42	170
alert[0x20]	7314	1			T10	1		T22	13		T42	1886
alert[0x21]	6525	1			T16	1		T42	60		T67	1
alert[0x22]	3767	1			T38	9		T42	777		T43	103
alert[0x23]	6935	1			T2	1		T10	1		T42	1197
alert[0x24]	13003	1			T2	1		T5	1		T22	71
alert[0x25]	9892	1			T38	2		T42	451		T74	16
alert[0x26]	7250	1			T2	1		T43	567		T74	4135
alert[0x27]	7720	1			T43	58		T108	18		T45	3
alert[0x28]	9716	1			T28	20		T75	339		T95	321
alert[0x29]	6589	1			T2	1		T5	1		T16	1
alert[0x2a]	6394	1			T16	1		T22	112		T42	137
alert[0x2b]	10884	1			T22	5		T42	9		T220	1
alert[0x2c]	7247	1			T2	1		T38	5		T65	1
alert[0x2d]	3335	1			T38	2		T42	1553		T43	63
alert[0x2e]	7978	1			T22	171		T75	168		T271	1
alert[0x2f]	4151	1			T2	1		T38	31		T10	1
alert[0x30]	7129	1			T2	1		T5	1		T42	582
alert[0x31]	4426	1			T2	1		T28	3		T220	1
alert[0x32]	5050	1			T38	2		T22	10		T28	2
alert[0x33]	8802	1			T16	1		T22	36		T42	88
alert[0x34]	2988	1			T8	1		T22	56		T28	94
alert[0x35]	8100	1			T5	1		T38	9		T22	19
alert[0x36]	10667	1			T10	1		T22	302		T42	100
alert[0x37]	10996	1			T22	19		T42	563		T74	3
alert[0x38]	2622	1			T38	2		T22	91		T30	2
alert[0x39]	7703	1			T5	2		T16	1		T42	932
alert[0x3a]	6602	1			T10	1		T16	1		T42	171
alert[0x3b]	3275	1			T16	1		T22	80		T220	1
alert[0x3c]	2749	1			T38	2		T42	181		T28	7
alert[0x3d]	8773	1			T5	1		T16	2		T22	818
alert[0x3e]	3305	1			T28	17		T74	35		T45	144
alert[0x3f]	10823	1			T22	12		T42	548		T28	2
alert[0x40]	8710	1			T42	367		T28	5		T43	139

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	127875	1			T2	15		T5	16		T38	17
class_i[0x1]	122789	1			T2	1		T8	1		T9	1
class_i[0x2]	101993	1			T2	1		T65	33		T67	83
class_i[0x3]	151140	1			T2	2		T15	1		T38	61

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

503142

1

T8

1

T38

96

T22

5857

alert_ping_fail

655

1

T2

19

T5

16

T9

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8360	1			T22	1878		T28	4		T43	115
alert_integrity_fail	alert[0x1]	5198	1			T22	595		T42	34		T67	3
alert_integrity_fail	alert[0x2]	17975	1			T22	990		T42	7265		T43	1179
alert_integrity_fail	alert[0x3]	6060	1			T22	1		T42	75		T75	23
alert_integrity_fail	alert[0x4]	10069	1			T38	18		T42	135		T28	1
alert_integrity_fail	alert[0x5]	12907	1			T28	28		T74	35		T108	84
alert_integrity_fail	alert[0x6]	5573	1			T74	27		T45	62		T51	2
alert_integrity_fail	alert[0x7]	6391	1			T38	6		T22	25		T43	193
alert_integrity_fail	alert[0x8]	3815	1			T42	44		T30	1		T74	140
alert_integrity_fail	alert[0x9]	5118	1			T22	1		T74	1517		T75	63
alert_integrity_fail	alert[0xa]	6331	1			T65	8		T74	866		T75	1
alert_integrity_fail	alert[0xb]	8191	1			T22	10		T28	40		T43	299
alert_integrity_fail	alert[0xc]	14584	1			T65	3		T67	4		T43	47
alert_integrity_fail	alert[0xd]	11910	1			T38	1		T42	5		T28	112
alert_integrity_fail	alert[0xe]	3400	1			T38	3		T22	21		T42	1
alert_integrity_fail	alert[0xf]	6327	1			T74	19		T75	5		T29	3
alert_integrity_fail	alert[0x10]	3756	1			T22	14		T42	11		T28	3
alert_integrity_fail	alert[0x11]	16261	1			T38	1		T22	59		T42	621
alert_integrity_fail	alert[0x12]	18632	1			T65	15		T43	1445		T45	28
alert_integrity_fail	alert[0x13]	9444	1			T43	21		T74	31		T45	13
alert_integrity_fail	alert[0x14]	6324	1			T38	2		T43	138		T75	344
alert_integrity_fail	alert[0x15]	7783	1			T22	218		T43	30		T74	292
alert_integrity_fail	alert[0x16]	9576	1			T38	1		T42	14		T43	133
alert_integrity_fail	alert[0x17]	11175	1			T22	47		T42	147		T67	74
alert_integrity_fail	alert[0x18]	6239	1			T67	1		T30	3		T74	248
alert_integrity_fail	alert[0x19]	3668	1			T30	1		T45	70		T31	31
alert_integrity_fail	alert[0x1a]	4085	1			T28	6		T43	8		T45	108
alert_integrity_fail	alert[0x1b]	17464	1			T28	6		T74	14		T108	963
alert_integrity_fail	alert[0x1c]	7942	1			T43	117		T45	192		T51	3
alert_integrity_fail	alert[0x1d]	9557	1			T22	25		T43	577		T95	427
alert_integrity_fail	alert[0x1e]	3754	1			T22	127		T43	59		T74	43
alert_integrity_fail	alert[0x1f]	4162	1			T22	26		T42	170		T65	2
alert_integrity_fail	alert[0x20]	7306	1			T22	13		T42	1886		T43	14
alert_integrity_fail	alert[0x21]	6513	1			T42	60		T67	1		T45	412
alert_integrity_fail	alert[0x22]	3754	1			T38	9		T42	777		T43	103
alert_integrity_fail	alert[0x23]	6926	1			T42	1197		T65	1		T28	486
alert_integrity_fail	alert[0x24]	12994	1			T22	71		T65	4		T75	80
alert_integrity_fail	alert[0x25]	9887	1			T38	2		T42	451		T74	16
alert_integrity_fail	alert[0x26]	7239	1			T43	567		T74	4135		T217	1
alert_integrity_fail	alert[0x27]	7712	1			T43	58		T108	18		T45	3
alert_integrity_fail	alert[0x28]	9707	1			T28	20		T75	339		T95	321
alert_integrity_fail	alert[0x29]	6576	1			T43	24		T75	1		T29	9
alert_integrity_fail	alert[0x2a]	6380	1			T22	112		T42	137		T43	45
alert_integrity_fail	alert[0x2b]	10880	1			T22	5		T42	9		T43	3794
alert_integrity_fail	alert[0x2c]	7237	1			T38	5		T65	1		T28	1
alert_integrity_fail	alert[0x2d]	3320	1			T38	2		T42	1553		T43	63
alert_integrity_fail	alert[0x2e]	7966	1			T22	171		T75	168		T53	3
alert_integrity_fail	alert[0x2f]	4137	1			T38	31		T22	5		T28	1
alert_integrity_fail	alert[0x30]	7114	1			T42	582		T31	28		T272	1
alert_integrity_fail	alert[0x31]	4414	1			T28	3		T43	52		T74	9
alert_integrity_fail	alert[0x32]	5046	1			T38	2		T22	10		T28	2
alert_integrity_fail	alert[0x33]	8793	1			T22	36		T42	88		T28	1
alert_integrity_fail	alert[0x34]	2979	1			T8	1		T22	56		T28	94
alert_integrity_fail	alert[0x35]	8093	1			T38	9		T22	19		T74	6
alert_integrity_fail	alert[0x36]	10664	1			T22	302		T42	100		T43	308
alert_integrity_fail	alert[0x37]	10987	1			T22	19		T42	563		T74	3
alert_integrity_fail	alert[0x38]	2611	1			T38	2		T22	91		T30	2
alert_integrity_fail	alert[0x39]	7691	1			T42	932		T28	3		T74	209
alert_integrity_fail	alert[0x3a]	6591	1			T42	171		T30	88		T74	67
alert_integrity_fail	alert[0x3b]	3270	1			T22	80		T43	221		T74	21
alert_integrity_fail	alert[0x3c]	2738	1			T38	2		T42	181		T28	7
alert_integrity_fail	alert[0x3d]	8763	1			T22	818		T65	2		T28	161
alert_integrity_fail	alert[0x3e]	3296	1			T28	17		T74	35		T45	144
alert_integrity_fail	alert[0x3f]	10820	1			T22	12		T42	548		T28	2
alert_integrity_fail	alert[0x40]	8707	1			T42	367		T28	5		T43	139
alert_ping_fail	alert[0x0]	6	1			T220	1		T286	2		T287	1
alert_ping_fail	alert[0x1]	13	1			T220	2		T288	1		T289	1
alert_ping_fail	alert[0x2]	10	1			T220	1		T267	1		T290	1
alert_ping_fail	alert[0x3]	10	1			T16	1		T291	1		T292	1
alert_ping_fail	alert[0x4]	10	1			T5	1		T271	2		T286	2
alert_ping_fail	alert[0x5]	15	1			T5	1		T9	1		T10	1
alert_ping_fail	alert[0x6]	13	1			T16	1		T256	2		T286	1
alert_ping_fail	alert[0x7]	14	1			T2	1		T5	1		T256	1
alert_ping_fail	alert[0x8]	13	1			T16	1		T286	1		T279	1
alert_ping_fail	alert[0x9]	11	1			T271	1		T256	1		T293	1
alert_ping_fail	alert[0xa]	11	1			T16	2		T286	1		T294	1
alert_ping_fail	alert[0xb]	11	1			T16	1		T285	1		T286	2
alert_ping_fail	alert[0xc]	10	1			T10	1		T267	2		T295	2
alert_ping_fail	alert[0xd]	12	1			T16	1		T220	1		T294	1
alert_ping_fail	alert[0xe]	11	1			T10	1		T16	1		T220	1
alert_ping_fail	alert[0xf]	3	1			T2	1		T296	1		T297	1
alert_ping_fail	alert[0x10]	12	1			T271	1		T256	1		T288	1
alert_ping_fail	alert[0x11]	9	1			T2	1		T267	1		T298	1
alert_ping_fail	alert[0x12]	7	1			T294	1		T292	1		T299	1
alert_ping_fail	alert[0x13]	14	1			T5	2		T16	1		T271	1
alert_ping_fail	alert[0x14]	12	1			T2	3		T15	1		T256	1
alert_ping_fail	alert[0x15]	14	1			T5	1		T294	1		T288	2
alert_ping_fail	alert[0x16]	9	1			T100	1		T191	1		T300	1
alert_ping_fail	alert[0x17]	11	1			T5	3		T220	1		T100	2
alert_ping_fail	alert[0x18]	11	1			T2	1		T271	1		T256	1
alert_ping_fail	alert[0x19]	10	1			T285	1		T294	1		T289	1
alert_ping_fail	alert[0x1a]	11	1			T10	1		T256	1		T301	1
alert_ping_fail	alert[0x1b]	16	1			T16	1		T267	1		T288	1
alert_ping_fail	alert[0x1c]	8	1			T2	1		T280	1		T256	1
alert_ping_fail	alert[0x1d]	10	1			T2	2		T16	1		T285	1
alert_ping_fail	alert[0x1e]	8	1			T220	1		T267	1		T299	2
alert_ping_fail	alert[0x1f]	11	1			T2	1		T302	1		T290	1
alert_ping_fail	alert[0x20]	8	1			T10	1		T292	1		T295	2
alert_ping_fail	alert[0x21]	12	1			T16	1		T285	1		T271	1
alert_ping_fail	alert[0x22]	13	1			T282	1		T303	2		T262	1
alert_ping_fail	alert[0x23]	9	1			T2	1		T10	1		T271	1
alert_ping_fail	alert[0x24]	9	1			T2	1		T5	1		T285	1
alert_ping_fail	alert[0x25]	5	1			T271	1		T294	1		T301	1
alert_ping_fail	alert[0x26]	11	1			T2	1		T267	3		T304	1
alert_ping_fail	alert[0x27]	8	1			T290	1		T305	1		T306	1
alert_ping_fail	alert[0x28]	9	1			T267	1		T282	2		T286	1
alert_ping_fail	alert[0x29]	13	1			T2	1		T5	1		T16	1
alert_ping_fail	alert[0x2a]	14	1			T16	1		T286	1		T288	1
alert_ping_fail	alert[0x2b]	4	1			T220	1		T307	1		T308	1
alert_ping_fail	alert[0x2c]	10	1			T2	1		T288	1		T308	2
alert_ping_fail	alert[0x2d]	15	1			T256	1		T286	1		T294	2
alert_ping_fail	alert[0x2e]	12	1			T271	1		T289	1		T301	1
alert_ping_fail	alert[0x2f]	14	1			T2	1		T10	1		T285	1
alert_ping_fail	alert[0x30]	15	1			T2	1		T5	1		T267	2
alert_ping_fail	alert[0x31]	12	1			T2	1		T220	1		T293	1
alert_ping_fail	alert[0x32]	4	1			T290	1		T292	1		T309	1
alert_ping_fail	alert[0x33]	9	1			T16	1		T256	1		T289	1
alert_ping_fail	alert[0x34]	9	1			T267	3		T288	1		T289	1
alert_ping_fail	alert[0x35]	7	1			T5	1		T271	1		T256	1
alert_ping_fail	alert[0x36]	3	1			T10	1		T271	1		T310	1
alert_ping_fail	alert[0x37]	9	1			T271	1		T267	2		T286	1
alert_ping_fail	alert[0x38]	11	1			T291	1		T267	1		T256	1
alert_ping_fail	alert[0x39]	12	1			T5	2		T16	1		T271	1
alert_ping_fail	alert[0x3a]	11	1			T10	1		T16	1		T220	1
alert_ping_fail	alert[0x3b]	5	1			T16	1		T220	1		T256	1
alert_ping_fail	alert[0x3c]	11	1			T267	1		T256	1		T286	1
alert_ping_fail	alert[0x3d]	10	1			T5	1		T16	2		T220	1
alert_ping_fail	alert[0x3e]	9	1			T288	1		T301	1		T295	1
alert_ping_fail	alert[0x3f]	3	1			T299	1		T309	1		T311	1
alert_ping_fail	alert[0x40]	3	1			T308	1		T312	1		T313	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	127714	1			T38	17		T22	52		T42	18022
alert_integrity_fail	class_i[0x1]	122580	1			T8	1		T38	18		T22	7
alert_integrity_fail	class_i[0x2]	101846	1			T65	33		T67	83		T30	91
alert_integrity_fail	class_i[0x3]	151002	1			T38	61		T22	5798		T42	11
alert_ping_fail	class_i[0x0]	161	1			T2	15		T5	16		T10	9
alert_ping_fail	class_i[0x1]	209	1			T2	1		T9	1		T16	20
alert_ping_fail	class_i[0x2]	147	1			T2	1		T220	1		T280	1
alert_ping_fail	class_i[0x3]	138	1			T2	2		T15	1		T220	1