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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.73 100.00 100.00 100.00 99.38 99.56


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.408255263 Jul 12 05:58:49 PM PDT 24 Jul 12 05:59:24 PM PDT 24 132449503 ps
T772 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1922137777 Jul 12 05:59:05 PM PDT 24 Jul 12 05:59:38 PM PDT 24 176637237 ps
T773 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2066862566 Jul 12 05:58:33 PM PDT 24 Jul 12 05:59:08 PM PDT 24 140696881 ps
T774 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3292627130 Jul 12 05:58:28 PM PDT 24 Jul 12 06:00:12 PM PDT 24 2320004495 ps
T775 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3046000239 Jul 12 05:58:34 PM PDT 24 Jul 12 05:59:05 PM PDT 24 6477919 ps
T165 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1258955839 Jul 12 05:58:34 PM PDT 24 Jul 12 05:59:06 PM PDT 24 52510316 ps
T124 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2116487401 Jul 12 05:58:23 PM PDT 24 Jul 12 06:05:14 PM PDT 24 34246421512 ps
T776 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.611426723 Jul 12 05:59:26 PM PDT 24 Jul 12 05:59:36 PM PDT 24 12273868 ps
T777 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2617983323 Jul 12 05:58:27 PM PDT 24 Jul 12 06:02:11 PM PDT 24 10558892766 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2863265358 Jul 12 05:58:34 PM PDT 24 Jul 12 05:59:11 PM PDT 24 124129522 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.19254177 Jul 12 05:58:51 PM PDT 24 Jul 12 05:59:21 PM PDT 24 236385820 ps
T139 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3241856283 Jul 12 05:59:04 PM PDT 24 Jul 12 06:04:50 PM PDT 24 4892397705 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1593119437 Jul 12 05:58:43 PM PDT 24 Jul 12 05:59:17 PM PDT 24 275121616 ps
T781 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.918684668 Jul 12 05:58:53 PM PDT 24 Jul 12 05:59:38 PM PDT 24 307769249 ps
T782 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1873010849 Jul 12 05:58:59 PM PDT 24 Jul 12 05:59:31 PM PDT 24 319388424 ps
T783 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3939551040 Jul 12 05:58:54 PM PDT 24 Jul 12 05:59:20 PM PDT 24 28618392 ps
T140 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2983836897 Jul 12 05:58:38 PM PDT 24 Jul 12 06:09:26 PM PDT 24 8237055970 ps
T784 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2847081645 Jul 12 05:59:20 PM PDT 24 Jul 12 05:59:34 PM PDT 24 9670556 ps
T785 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2367890844 Jul 12 05:59:11 PM PDT 24 Jul 12 05:59:55 PM PDT 24 346761051 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3682048214 Jul 12 05:58:48 PM PDT 24 Jul 12 05:59:20 PM PDT 24 105827129 ps
T787 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3010127062 Jul 12 05:59:17 PM PDT 24 Jul 12 05:59:33 PM PDT 24 11076786 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1452378652 Jul 12 05:58:59 PM PDT 24 Jul 12 05:59:25 PM PDT 24 14043277 ps
T164 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.484119942 Jul 12 05:58:30 PM PDT 24 Jul 12 05:59:02 PM PDT 24 33410605 ps
T789 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3568057592 Jul 12 05:58:44 PM PDT 24 Jul 12 05:59:11 PM PDT 24 6449478 ps
T170 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3870593093 Jul 12 05:58:54 PM PDT 24 Jul 12 05:59:56 PM PDT 24 1203607243 ps
T790 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2651818366 Jul 12 05:58:46 PM PDT 24 Jul 12 05:59:12 PM PDT 24 10786990 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1394045079 Jul 12 05:59:02 PM PDT 24 Jul 12 05:59:44 PM PDT 24 1445764795 ps
T147 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1643743161 Jul 12 05:58:46 PM PDT 24 Jul 12 06:09:23 PM PDT 24 31671260347 ps
T141 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2901858805 Jul 12 05:58:35 PM PDT 24 Jul 12 06:13:44 PM PDT 24 12703387259 ps
T792 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3097854712 Jul 12 05:58:48 PM PDT 24 Jul 12 05:59:27 PM PDT 24 128913285 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.752800053 Jul 12 05:58:26 PM PDT 24 Jul 12 05:59:38 PM PDT 24 1467972698 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2363375647 Jul 12 05:58:34 PM PDT 24 Jul 12 05:59:08 PM PDT 24 126934356 ps
T795 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1716689051 Jul 12 05:58:33 PM PDT 24 Jul 12 06:03:29 PM PDT 24 6350552607 ps
T796 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.190790236 Jul 12 05:58:33 PM PDT 24 Jul 12 05:59:10 PM PDT 24 364134725 ps
T158 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.635113490 Jul 12 05:59:00 PM PDT 24 Jul 12 06:00:22 PM PDT 24 4007399971 ps
T797 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3999758794 Jul 12 05:58:55 PM PDT 24 Jul 12 05:59:20 PM PDT 24 10854492 ps
T159 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1164484899 Jul 12 05:58:34 PM PDT 24 Jul 12 05:59:07 PM PDT 24 264244733 ps
T143 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1905350843 Jul 12 05:59:00 PM PDT 24 Jul 12 06:01:43 PM PDT 24 2219856291 ps
T798 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4064469390 Jul 12 05:58:54 PM PDT 24 Jul 12 05:59:32 PM PDT 24 583179526 ps
T799 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3769552546 Jul 12 05:58:48 PM PDT 24 Jul 12 06:00:00 PM PDT 24 699376680 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.622803916 Jul 12 05:59:04 PM PDT 24 Jul 12 05:59:32 PM PDT 24 350646591 ps
T801 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.506027704 Jul 12 05:59:21 PM PDT 24 Jul 12 05:59:34 PM PDT 24 15758715 ps
T802 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3319903770 Jul 12 05:58:39 PM PDT 24 Jul 12 05:59:09 PM PDT 24 8756937 ps
T803 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.956358787 Jul 12 05:58:38 PM PDT 24 Jul 12 06:00:54 PM PDT 24 6739420659 ps
T157 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3898981421 Jul 12 05:58:38 PM PDT 24 Jul 12 06:00:20 PM PDT 24 4500942797 ps
T804 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3327956315 Jul 12 05:59:28 PM PDT 24 Jul 12 05:59:37 PM PDT 24 10503816 ps
T805 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1225880008 Jul 12 05:59:22 PM PDT 24 Jul 12 05:59:35 PM PDT 24 8404051 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1579954276 Jul 12 05:58:34 PM PDT 24 Jul 12 05:59:24 PM PDT 24 942521400 ps
T144 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1743546635 Jul 12 05:59:06 PM PDT 24 Jul 12 06:01:17 PM PDT 24 1709402559 ps
T807 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1590896200 Jul 12 05:59:15 PM PDT 24 Jul 12 05:59:32 PM PDT 24 13691977 ps
T155 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3879903413 Jul 12 05:58:53 PM PDT 24 Jul 12 05:59:21 PM PDT 24 56806859 ps
T146 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3996712573 Jul 12 05:59:10 PM PDT 24 Jul 12 06:04:33 PM PDT 24 5674459761 ps
T145 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3364288174 Jul 12 05:58:49 PM PDT 24 Jul 12 06:03:52 PM PDT 24 3699998204 ps
T808 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1490109322 Jul 12 05:59:16 PM PDT 24 Jul 12 05:59:33 PM PDT 24 8801543 ps
T809 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2523219163 Jul 12 05:59:26 PM PDT 24 Jul 12 05:59:36 PM PDT 24 7271454 ps
T810 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.543654191 Jul 12 05:58:37 PM PDT 24 Jul 12 05:59:11 PM PDT 24 120965927 ps
T811 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3780049396 Jul 12 05:58:44 PM PDT 24 Jul 12 05:59:20 PM PDT 24 567020701 ps
T812 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.923898841 Jul 12 05:59:23 PM PDT 24 Jul 12 05:59:35 PM PDT 24 18490636 ps
T813 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3046135833 Jul 12 05:59:03 PM PDT 24 Jul 12 05:59:31 PM PDT 24 138177053 ps
T814 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2671606102 Jul 12 05:58:59 PM PDT 24 Jul 12 05:59:28 PM PDT 24 33620146 ps
T815 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3156241583 Jul 12 05:58:51 PM PDT 24 Jul 12 05:59:37 PM PDT 24 1406778700 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1508470709 Jul 12 05:58:55 PM PDT 24 Jul 12 05:59:28 PM PDT 24 462466046 ps
T817 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2542075501 Jul 12 05:59:27 PM PDT 24 Jul 12 05:59:36 PM PDT 24 8276571 ps
T818 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.529970565 Jul 12 05:59:07 PM PDT 24 Jul 12 05:59:37 PM PDT 24 108128474 ps
T819 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.469368014 Jul 12 05:59:06 PM PDT 24 Jul 12 05:59:28 PM PDT 24 11768896 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1358056745 Jul 12 05:59:02 PM PDT 24 Jul 12 05:59:50 PM PDT 24 171357808 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.254582564 Jul 12 05:58:49 PM PDT 24 Jul 12 06:06:34 PM PDT 24 6007193312 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3556867791 Jul 12 05:59:00 PM PDT 24 Jul 12 05:59:32 PM PDT 24 115110483 ps
T823 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3489196535 Jul 12 05:58:51 PM PDT 24 Jul 12 05:59:31 PM PDT 24 113526920 ps
T199 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1255460421 Jul 12 05:58:38 PM PDT 24 Jul 12 06:09:46 PM PDT 24 85143691680 ps
T824 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.874364338 Jul 12 05:58:48 PM PDT 24 Jul 12 06:04:29 PM PDT 24 12794192362 ps
T825 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1719702900 Jul 12 05:58:31 PM PDT 24 Jul 12 06:00:42 PM PDT 24 9451797183 ps
T154 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.650662369 Jul 12 05:58:49 PM PDT 24 Jul 12 06:00:32 PM PDT 24 2216225701 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4095279315 Jul 12 05:58:35 PM PDT 24 Jul 12 05:59:05 PM PDT 24 18762375 ps
T827 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2815293880 Jul 12 05:59:07 PM PDT 24 Jul 12 05:59:33 PM PDT 24 48576202 ps
T828 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.638111317 Jul 12 05:59:18 PM PDT 24 Jul 12 05:59:33 PM PDT 24 16624920 ps
T343 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2584661942 Jul 12 05:58:32 PM PDT 24 Jul 12 06:04:45 PM PDT 24 4294008771 ps
T129 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2742021386 Jul 12 05:58:33 PM PDT 24 Jul 12 06:02:02 PM PDT 24 2850708139 ps
T829 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1602695003 Jul 12 05:59:11 PM PDT 24 Jul 12 05:59:34 PM PDT 24 187572950 ps
T830 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1606477681 Jul 12 05:58:28 PM PDT 24 Jul 12 06:00:43 PM PDT 24 3407551808 ps
T831 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2773269987 Jul 12 05:59:22 PM PDT 24 Jul 12 05:59:35 PM PDT 24 18235858 ps

Test location /workspace/coverage/default/7.alert_handler_stress_all.3760753500
Short name T8
Test name
Test status
Simulation time 148547408338 ps
CPU time 2603.51 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 289696 kb
Host smart-e26354e7-b6c3-4b2c-ae7f-fcf034eb98cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760753500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3760753500
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1327927933
Short name T20
Test name
Test status
Simulation time 96795782952 ps
CPU time 1380.04 seconds
Started Jul 12 04:46:42 PM PDT 24
Finished Jul 12 05:09:42 PM PDT 24
Peak memory 289720 kb
Host smart-270b1962-e459-464e-aa4f-9ddaa10f271c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327927933 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1327927933
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3484803998
Short name T11
Test name
Test status
Simulation time 435872918 ps
CPU time 12.89 seconds
Started Jul 12 04:45:14 PM PDT 24
Finished Jul 12 04:45:28 PM PDT 24
Peak memory 274952 kb
Host smart-96587a11-a281-4bdd-ba3d-0cafbb4f5682
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3484803998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3484803998
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2946344165
Short name T22
Test name
Test status
Simulation time 258123627337 ps
CPU time 3063.07 seconds
Started Jul 12 04:47:07 PM PDT 24
Finished Jul 12 05:38:11 PM PDT 24
Peak memory 289144 kb
Host smart-351e78b9-7893-4ed9-954f-f6dacb9fcd3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946344165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2946344165
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2631271485
Short name T149
Test name
Test status
Simulation time 552181139 ps
CPU time 35.72 seconds
Started Jul 12 05:58:54 PM PDT 24
Finished Jul 12 05:59:55 PM PDT 24
Peak memory 237656 kb
Host smart-ad5ec518-42a7-4790-9ee5-393619a0818b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2631271485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2631271485
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2319180118
Short name T31
Test name
Test status
Simulation time 99514454903 ps
CPU time 3053.97 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 05:38:10 PM PDT 24
Peak memory 289824 kb
Host smart-64225b27-554c-473b-9147-f80da38cc059
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319180118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2319180118
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2057452436
Short name T118
Test name
Test status
Simulation time 4153004751 ps
CPU time 293.22 seconds
Started Jul 12 05:59:10 PM PDT 24
Finished Jul 12 06:04:22 PM PDT 24
Peak memory 265424 kb
Host smart-0a49e6ad-b7d9-46bb-8f8e-ab8055d287b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2057452436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2057452436
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.4095826620
Short name T28
Test name
Test status
Simulation time 465591929933 ps
CPU time 3903.95 seconds
Started Jul 12 04:45:17 PM PDT 24
Finished Jul 12 05:50:23 PM PDT 24
Peak memory 306208 kb
Host smart-e2bb1ef6-cf5f-40bc-b7f9-d024e59b5811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095826620 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.4095826620
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.563887054
Short name T9
Test name
Test status
Simulation time 44051879921 ps
CPU time 2643.86 seconds
Started Jul 12 04:46:34 PM PDT 24
Finished Jul 12 05:30:38 PM PDT 24
Peak memory 288716 kb
Host smart-619a9390-3f5a-4aff-b337-93ed8414a400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563887054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.563887054
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.406973664
Short name T104
Test name
Test status
Simulation time 83295246089 ps
CPU time 1507.89 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 05:11:01 PM PDT 24
Peak memory 265772 kb
Host smart-aac50262-a4eb-4dce-99a5-aaa7c4ffb648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406973664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.406973664
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1214995081
Short name T90
Test name
Test status
Simulation time 176193867760 ps
CPU time 2825.52 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 05:33:53 PM PDT 24
Peak memory 289692 kb
Host smart-0a1e263e-4b26-4ad4-80e3-bf6f66260d13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214995081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1214995081
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3435947662
Short name T132
Test name
Test status
Simulation time 4424342429 ps
CPU time 672.41 seconds
Started Jul 12 05:58:48 PM PDT 24
Finished Jul 12 06:10:26 PM PDT 24
Peak memory 265376 kb
Host smart-089881fd-9bc3-46ca-b132-651f97448f4c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435947662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3435947662
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1178812047
Short name T74
Test name
Test status
Simulation time 196185561919 ps
CPU time 2786.18 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 286744 kb
Host smart-e40a47d0-6f0a-4d9a-990a-88cb48006159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178812047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1178812047
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.258212040
Short name T125
Test name
Test status
Simulation time 2913734051 ps
CPU time 215.29 seconds
Started Jul 12 05:58:50 PM PDT 24
Finished Jul 12 06:02:50 PM PDT 24
Peak memory 272516 kb
Host smart-6f1c00d9-d639-47f2-aaa4-9e3cb3d4583d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258212040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.258212040
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2089884064
Short name T315
Test name
Test status
Simulation time 214116965574 ps
CPU time 2758.64 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 05:32:28 PM PDT 24
Peak memory 290084 kb
Host smart-a2fc9c9e-8ca6-4bf4-bfd2-00e3d78d9ae0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089884064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2089884064
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1063401964
Short name T87
Test name
Test status
Simulation time 43047433977 ps
CPU time 2595.93 seconds
Started Jul 12 04:45:21 PM PDT 24
Finished Jul 12 05:28:38 PM PDT 24
Peak memory 298416 kb
Host smart-a6abdb34-1f81-4d21-8609-cf85d871d7cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063401964 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1063401964
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3296004246
Short name T530
Test name
Test status
Simulation time 10952216281 ps
CPU time 215.74 seconds
Started Jul 12 04:45:28 PM PDT 24
Finished Jul 12 04:49:06 PM PDT 24
Peak memory 255808 kb
Host smart-2e525ad5-004f-4fd5-aeb0-86dd113331d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296004246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3296004246
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1532404130
Short name T137
Test name
Test status
Simulation time 4264480379 ps
CPU time 619.45 seconds
Started Jul 12 05:58:46 PM PDT 24
Finished Jul 12 06:09:31 PM PDT 24
Peak memory 265344 kb
Host smart-b12cc48d-cd09-49a8-9e84-fa3ef3190116
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532404130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1532404130
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3998813510
Short name T334
Test name
Test status
Simulation time 10902618 ps
CPU time 1.39 seconds
Started Jul 12 05:59:05 PM PDT 24
Finished Jul 12 05:59:28 PM PDT 24
Peak memory 236700 kb
Host smart-967cc3f9-ea6c-48c4-ab82-443bf556f21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3998813510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3998813510
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1705298463
Short name T191
Test name
Test status
Simulation time 151832718043 ps
CPU time 2311.53 seconds
Started Jul 12 04:46:33 PM PDT 24
Finished Jul 12 05:25:06 PM PDT 24
Peak memory 273820 kb
Host smart-96ac5828-1ac9-473f-9598-1122a703bb6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705298463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1705298463
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2820072783
Short name T256
Test name
Test status
Simulation time 11502734147 ps
CPU time 488.13 seconds
Started Jul 12 04:46:06 PM PDT 24
Finished Jul 12 04:54:16 PM PDT 24
Peak memory 249356 kb
Host smart-c217b81e-ea7c-4313-bc21-a87486dab8a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820072783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2820072783
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2157178576
Short name T114
Test name
Test status
Simulation time 13481058964 ps
CPU time 351.54 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 06:05:14 PM PDT 24
Peak memory 265572 kb
Host smart-aed54acd-818f-4e4a-af24-6c3bb5c43116
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2157178576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2157178576
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3292848315
Short name T81
Test name
Test status
Simulation time 362112591881 ps
CPU time 6458.33 seconds
Started Jul 12 04:46:06 PM PDT 24
Finished Jul 12 06:33:47 PM PDT 24
Peak memory 323184 kb
Host smart-b6ee5db8-5a88-4f6b-a046-c1af516eb5b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292848315 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3292848315
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.522628153
Short name T262
Test name
Test status
Simulation time 100405847698 ps
CPU time 1529.19 seconds
Started Jul 12 04:46:24 PM PDT 24
Finished Jul 12 05:11:55 PM PDT 24
Peak memory 273364 kb
Host smart-89c2e9e4-89fc-4cec-a5d9-443ec11494ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522628153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.522628153
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1255460421
Short name T199
Test name
Test status
Simulation time 85143691680 ps
CPU time 641.06 seconds
Started Jul 12 05:58:38 PM PDT 24
Finished Jul 12 06:09:46 PM PDT 24
Peak memory 265364 kb
Host smart-c0daa704-e20d-4241-a5c2-97ee1621a4ea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255460421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1255460421
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2562029996
Short name T16
Test name
Test status
Simulation time 53736704633 ps
CPU time 536.56 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:54:41 PM PDT 24
Peak memory 249344 kb
Host smart-85ca693f-ad07-45f4-b6de-94f739bfcae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562029996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2562029996
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2928922821
Short name T130
Test name
Test status
Simulation time 78833160785 ps
CPU time 957.55 seconds
Started Jul 12 05:58:45 PM PDT 24
Finished Jul 12 06:15:08 PM PDT 24
Peak memory 265384 kb
Host smart-5fa68692-10e2-4d8d-aea4-e51441630dfd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928922821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2928922821
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2694982010
Short name T160
Test name
Test status
Simulation time 349991097 ps
CPU time 41.45 seconds
Started Jul 12 05:59:18 PM PDT 24
Finished Jul 12 06:00:13 PM PDT 24
Peak memory 248728 kb
Host smart-d5cfde37-99e3-4d37-8b41-302728480ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2694982010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2694982010
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.760042351
Short name T10
Test name
Test status
Simulation time 12700630434 ps
CPU time 210.46 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 04:49:39 PM PDT 24
Peak memory 256384 kb
Host smart-1d218816-4109-4048-8bc1-1db35a84aba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760042351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.760042351
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1384695518
Short name T120
Test name
Test status
Simulation time 25464942912 ps
CPU time 194.66 seconds
Started Jul 12 05:58:38 PM PDT 24
Finished Jul 12 06:02:20 PM PDT 24
Peak memory 265588 kb
Host smart-15ee7aa0-6fb2-4646-a12c-0fb5e0782708
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1384695518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1384695518
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1852712808
Short name T308
Test name
Test status
Simulation time 33619366733 ps
CPU time 658.59 seconds
Started Jul 12 04:46:16 PM PDT 24
Finished Jul 12 04:57:15 PM PDT 24
Peak memory 249256 kb
Host smart-c5b69e33-355c-4026-a9e1-d8739a8bf3bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852712808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1852712808
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3301121760
Short name T279
Test name
Test status
Simulation time 163511985038 ps
CPU time 2218.17 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 05:23:46 PM PDT 24
Peak memory 273928 kb
Host smart-b12235c4-ac40-4e7d-8144-c9617deaf5f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301121760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3301121760
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2089379621
Short name T245
Test name
Test status
Simulation time 56217583573 ps
CPU time 4700.98 seconds
Started Jul 12 04:45:48 PM PDT 24
Finished Jul 12 06:04:10 PM PDT 24
Peak memory 321860 kb
Host smart-e43a2557-4bc8-47c4-ba21-9495c534ff46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089379621 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2089379621
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.167912641
Short name T244
Test name
Test status
Simulation time 72999950318 ps
CPU time 4294.96 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 05:57:28 PM PDT 24
Peak memory 298540 kb
Host smart-1a62f632-70e4-4ae3-81f9-b5a4ad2b485a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167912641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.167912641
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4212388253
Short name T136
Test name
Test status
Simulation time 1505578422 ps
CPU time 97.57 seconds
Started Jul 12 05:58:41 PM PDT 24
Finished Jul 12 06:00:45 PM PDT 24
Peak memory 265364 kb
Host smart-a2930cb3-ce6c-4e05-abd4-5ab84e16c852
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4212388253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.4212388253
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1259080243
Short name T280
Test name
Test status
Simulation time 75822909487 ps
CPU time 1242.31 seconds
Started Jul 12 04:46:24 PM PDT 24
Finished Jul 12 05:07:08 PM PDT 24
Peak memory 273216 kb
Host smart-2e46f838-b4bb-4463-9f26-aec8737ccfc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259080243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1259080243
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1677630835
Short name T286
Test name
Test status
Simulation time 17026808574 ps
CPU time 637.59 seconds
Started Jul 12 04:46:17 PM PDT 24
Finished Jul 12 04:56:55 PM PDT 24
Peak memory 256124 kb
Host smart-2fd8e978-143c-47f3-a862-949048080f2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677630835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1677630835
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.467955708
Short name T122
Test name
Test status
Simulation time 4588635970 ps
CPU time 275.31 seconds
Started Jul 12 05:58:30 PM PDT 24
Finished Jul 12 06:03:35 PM PDT 24
Peak memory 265460 kb
Host smart-0358c677-6a13-4314-bf36-374fefbfdaf4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467955708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.467955708
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.674699796
Short name T338
Test name
Test status
Simulation time 22996514 ps
CPU time 1.53 seconds
Started Jul 12 05:59:18 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 237544 kb
Host smart-718aeb20-fd20-4d07-97f6-f1bd1bd8b351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=674699796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.674699796
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1401395666
Short name T51
Test name
Test status
Simulation time 329995566919 ps
CPU time 1758.75 seconds
Started Jul 12 04:46:20 PM PDT 24
Finished Jul 12 05:15:39 PM PDT 24
Peak memory 289788 kb
Host smart-bd9fb6a4-702c-4b8c-a56d-b47259a03a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401395666 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1401395666
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1235623311
Short name T585
Test name
Test status
Simulation time 73598131433 ps
CPU time 1407.43 seconds
Started Jul 12 04:45:42 PM PDT 24
Finished Jul 12 05:09:10 PM PDT 24
Peak memory 289636 kb
Host smart-267411c3-aabd-4b4e-9535-158aa2e88c50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235623311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1235623311
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2338690751
Short name T224
Test name
Test status
Simulation time 48132925886 ps
CPU time 1566.42 seconds
Started Jul 12 04:46:48 PM PDT 24
Finished Jul 12 05:12:55 PM PDT 24
Peak memory 285512 kb
Host smart-beb0dbfd-770b-49f2-b93f-69ddd70c4c62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338690751 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2338690751
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1700246094
Short name T320
Test name
Test status
Simulation time 60541692829 ps
CPU time 1594.59 seconds
Started Jul 12 04:47:00 PM PDT 24
Finished Jul 12 05:13:36 PM PDT 24
Peak memory 290300 kb
Host smart-a7a39612-9dcc-419b-a461-18798d547929
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700246094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1700246094
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1986423330
Short name T38
Test name
Test status
Simulation time 4786960555 ps
CPU time 468.64 seconds
Started Jul 12 04:45:21 PM PDT 24
Finished Jul 12 04:53:11 PM PDT 24
Peak memory 268048 kb
Host smart-d869d9c0-a876-4876-955b-9691ffa99533
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986423330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1986423330
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2901858805
Short name T141
Test name
Test status
Simulation time 12703387259 ps
CPU time 880.54 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 06:13:44 PM PDT 24
Peak memory 265392 kb
Host smart-40ffe6c4-8b31-4b90-bd27-b4565383ed20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901858805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2901858805
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.399855359
Short name T235
Test name
Test status
Simulation time 359264028 ps
CPU time 39.7 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:46:16 PM PDT 24
Peak memory 248808 kb
Host smart-51d98599-4ba6-47b2-98ac-8ed327b69428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39985
5359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.399855359
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2416058297
Short name T622
Test name
Test status
Simulation time 25606802548 ps
CPU time 557.18 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 04:55:00 PM PDT 24
Peak memory 248424 kb
Host smart-2a0ba398-1967-4617-92d5-7f1a3f2e89fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416058297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2416058297
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2899468944
Short name T309
Test name
Test status
Simulation time 8639707978 ps
CPU time 330.41 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 04:51:59 PM PDT 24
Peak memory 248328 kb
Host smart-eee4431b-44e3-4996-821e-00c2e029d15e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899468944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2899468944
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3221859132
Short name T150
Test name
Test status
Simulation time 591274322 ps
CPU time 4.3 seconds
Started Jul 12 05:58:54 PM PDT 24
Finished Jul 12 05:59:23 PM PDT 24
Peak memory 237796 kb
Host smart-e07020c1-fe17-4e53-9315-438e33e1af02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3221859132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3221859132
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3890035037
Short name T134
Test name
Test status
Simulation time 4729190517 ps
CPU time 707.14 seconds
Started Jul 12 05:58:58 PM PDT 24
Finished Jul 12 06:11:09 PM PDT 24
Peak memory 273552 kb
Host smart-5b0f6400-e23e-4cc4-8a2b-b8208e8899ec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890035037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3890035037
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1623131114
Short name T212
Test name
Test status
Simulation time 18055290 ps
CPU time 2.83 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:08 PM PDT 24
Peak memory 249484 kb
Host smart-7a7e4985-f519-4436-a4d5-8795e9569394
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1623131114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1623131114
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2549254463
Short name T3
Test name
Test status
Simulation time 106023300 ps
CPU time 2.91 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 04:45:11 PM PDT 24
Peak memory 249444 kb
Host smart-00908b96-c74d-421f-8a35-4363bbccca67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2549254463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2549254463
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4192713218
Short name T59
Test name
Test status
Simulation time 22227306 ps
CPU time 2.82 seconds
Started Jul 12 04:45:26 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 249484 kb
Host smart-2106380c-28d2-429b-b371-d0cddb5eddb0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4192713218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4192713218
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1879251936
Short name T205
Test name
Test status
Simulation time 37972310 ps
CPU time 3.73 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 04:45:36 PM PDT 24
Peak memory 249476 kb
Host smart-fda806b6-dfa3-46a4-86ce-d6301c18abf2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1879251936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1879251936
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.78989303
Short name T303
Test name
Test status
Simulation time 36144347894 ps
CPU time 2041.15 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 05:19:12 PM PDT 24
Peak memory 286644 kb
Host smart-77ffd5c2-18e1-4c8a-b3e0-c169df18d558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78989303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.78989303
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4263128080
Short name T86
Test name
Test status
Simulation time 224894560591 ps
CPU time 2789.18 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 319948 kb
Host smart-176a5ed9-041a-4671-ba5a-7f1239517d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263128080 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4263128080
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2894146017
Short name T44
Test name
Test status
Simulation time 1441625747 ps
CPU time 25.26 seconds
Started Jul 12 04:46:30 PM PDT 24
Finished Jul 12 04:46:57 PM PDT 24
Peak memory 248792 kb
Host smart-c8244b3b-948d-4bfa-9e0a-6e379bc015dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28941
46017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2894146017
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.68444989
Short name T73
Test name
Test status
Simulation time 154310162674 ps
CPU time 2719.45 seconds
Started Jul 12 04:47:06 PM PDT 24
Finished Jul 12 05:32:27 PM PDT 24
Peak memory 290064 kb
Host smart-5539bd47-de90-4a97-a46d-9ea7e5e68297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68444989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.68444989
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1598028719
Short name T13
Test name
Test status
Simulation time 1064032613 ps
CPU time 15.36 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:18 PM PDT 24
Peak memory 271068 kb
Host smart-b8767788-b87b-43b3-bf92-60ad68972d5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1598028719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1598028719
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2007975806
Short name T161
Test name
Test status
Simulation time 3678791767 ps
CPU time 62.49 seconds
Started Jul 12 05:58:40 PM PDT 24
Finished Jul 12 06:00:10 PM PDT 24
Peak memory 240556 kb
Host smart-797f1e34-e28d-4002-8d1c-9eb50223a32d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2007975806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2007975806
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.497379960
Short name T335
Test name
Test status
Simulation time 11476906 ps
CPU time 1.3 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 05:59:24 PM PDT 24
Peak memory 236572 kb
Host smart-b4bbc1ab-5f88-4acc-8c52-d6ecd1278056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=497379960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.497379960
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2172465102
Short name T702
Test name
Test status
Simulation time 26698012212 ps
CPU time 238.13 seconds
Started Jul 12 04:45:07 PM PDT 24
Finished Jul 12 04:49:08 PM PDT 24
Peak memory 249280 kb
Host smart-ee76f494-d91f-42c5-9775-174a953cb2df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172465102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2172465102
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1702843257
Short name T316
Test name
Test status
Simulation time 42577317547 ps
CPU time 2637.22 seconds
Started Jul 12 04:45:26 PM PDT 24
Finished Jul 12 05:29:25 PM PDT 24
Peak memory 289900 kb
Host smart-e3d93ba2-13ed-46ec-8067-dbff0ba18f73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702843257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1702843257
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2551711596
Short name T633
Test name
Test status
Simulation time 95117653456 ps
CPU time 2857.73 seconds
Started Jul 12 04:45:39 PM PDT 24
Finished Jul 12 05:33:18 PM PDT 24
Peak memory 290192 kb
Host smart-4c3a530e-5ac4-45fe-83b0-3858712fa792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551711596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2551711596
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1635039752
Short name T659
Test name
Test status
Simulation time 112049163473 ps
CPU time 1258.58 seconds
Started Jul 12 04:45:42 PM PDT 24
Finished Jul 12 05:06:42 PM PDT 24
Peak memory 285620 kb
Host smart-83a5c281-687d-4999-aabc-719fc0e4bfac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635039752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1635039752
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3707801414
Short name T281
Test name
Test status
Simulation time 72524321523 ps
CPU time 1191.86 seconds
Started Jul 12 04:45:47 PM PDT 24
Finished Jul 12 05:05:40 PM PDT 24
Peak memory 271996 kb
Host smart-31b824a2-40be-4986-ae2f-cb3c9a81cb22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707801414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3707801414
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1107430942
Short name T301
Test name
Test status
Simulation time 11134789538 ps
CPU time 243.11 seconds
Started Jul 12 04:45:44 PM PDT 24
Finished Jul 12 04:49:49 PM PDT 24
Peak memory 249280 kb
Host smart-b0ccab74-66db-4a61-87f3-bbe04c7fdce9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107430942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1107430942
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.617340764
Short name T29
Test name
Test status
Simulation time 309220318 ps
CPU time 18.13 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:47:15 PM PDT 24
Peak memory 255944 kb
Host smart-31047cc6-e52d-4c5e-9ec1-283b399e9904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61734
0764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.617340764
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3901282176
Short name T297
Test name
Test status
Simulation time 53928462113 ps
CPU time 402.7 seconds
Started Jul 12 04:45:05 PM PDT 24
Finished Jul 12 04:51:51 PM PDT 24
Peak memory 249236 kb
Host smart-9fd5b6c2-1c82-43f7-af20-60fee5e6da39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901282176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3901282176
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.983583787
Short name T278
Test name
Test status
Simulation time 93379783400 ps
CPU time 2743.19 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 288820 kb
Host smart-22c48f17-5cd2-4f08-882d-3f65d8bcf1f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983583787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.983583787
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.25772738
Short name T233
Test name
Test status
Simulation time 62283723532 ps
CPU time 2265.47 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 05:23:32 PM PDT 24
Peak memory 289560 kb
Host smart-946cf780-7d4f-44e3-9ee3-f967f98d1af9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25772738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_hand
ler_stress_all.25772738
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2807430882
Short name T261
Test name
Test status
Simulation time 829528898332 ps
CPU time 2594.16 seconds
Started Jul 12 04:46:13 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 289804 kb
Host smart-f0934284-ed8a-4a90-b3ab-7d253778247d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807430882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2807430882
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1137632416
Short name T255
Test name
Test status
Simulation time 1527236382 ps
CPU time 45.22 seconds
Started Jul 12 04:46:19 PM PDT 24
Finished Jul 12 04:47:04 PM PDT 24
Peak memory 249140 kb
Host smart-def71bc3-0afd-423e-84b7-5a804fdc1174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11376
32416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1137632416
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.8104554
Short name T80
Test name
Test status
Simulation time 685937218 ps
CPU time 42.25 seconds
Started Jul 12 04:47:20 PM PDT 24
Finished Jul 12 04:48:03 PM PDT 24
Peak memory 249188 kb
Host smart-24109652-d138-4516-9a72-f4cb4aa1aecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81045
54 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.8104554
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1520040476
Short name T234
Test name
Test status
Simulation time 40305917888 ps
CPU time 2350.78 seconds
Started Jul 12 04:47:26 PM PDT 24
Finished Jul 12 05:26:37 PM PDT 24
Peak memory 289696 kb
Host smart-95860444-cdb2-49c0-a896-745b30aaa061
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520040476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1520040476
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.874364338
Short name T824
Test name
Test status
Simulation time 12794192362 ps
CPU time 315.65 seconds
Started Jul 12 05:58:48 PM PDT 24
Finished Jul 12 06:04:29 PM PDT 24
Peak memory 265440 kb
Host smart-a7f188af-4b40-4d0f-8901-f335253c322c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=874364338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.874364338
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2742021386
Short name T129
Test name
Test status
Simulation time 2850708139 ps
CPU time 179.42 seconds
Started Jul 12 05:58:33 PM PDT 24
Finished Jul 12 06:02:02 PM PDT 24
Peak memory 267108 kb
Host smart-3c877768-b200-4356-b3c4-1d090d42e11a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2742021386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2742021386
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1164484899
Short name T159
Test name
Test status
Simulation time 264244733 ps
CPU time 3.76 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:07 PM PDT 24
Peak memory 237612 kb
Host smart-88108ef4-9dd9-4daf-affc-194d02db7487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1164484899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1164484899
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3898981421
Short name T157
Test name
Test status
Simulation time 4500942797 ps
CPU time 75.15 seconds
Started Jul 12 05:58:38 PM PDT 24
Finished Jul 12 06:00:20 PM PDT 24
Peak memory 240524 kb
Host smart-c1bdf0d7-97ba-4d54-bbde-6f240183f7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3898981421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3898981421
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3879903413
Short name T155
Test name
Test status
Simulation time 56806859 ps
CPU time 4.37 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 237556 kb
Host smart-41a104cf-002b-478c-a2e5-1684ea19821c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3879903413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3879903413
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.650662369
Short name T154
Test name
Test status
Simulation time 2216225701 ps
CPU time 77.67 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 06:00:32 PM PDT 24
Peak memory 246132 kb
Host smart-8d4e130a-2113-4e00-a097-52e3ffb638b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=650662369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.650662369
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3870593093
Short name T170
Test name
Test status
Simulation time 1203607243 ps
CPU time 36.65 seconds
Started Jul 12 05:58:54 PM PDT 24
Finished Jul 12 05:59:56 PM PDT 24
Peak memory 240504 kb
Host smart-0006ad38-71bb-4dae-b9cc-d82c913e3464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3870593093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3870593093
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1882136183
Short name T131
Test name
Test status
Simulation time 55437712010 ps
CPU time 990.62 seconds
Started Jul 12 05:59:05 PM PDT 24
Finished Jul 12 06:15:57 PM PDT 24
Peak memory 265372 kb
Host smart-d88f83dc-baf0-446d-adef-7c842bc38cea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882136183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1882136183
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.635113490
Short name T158
Test name
Test status
Simulation time 4007399971 ps
CPU time 59.71 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 06:00:22 PM PDT 24
Peak memory 238780 kb
Host smart-cf979ebc-2639-4539-ad63-60ac2b4a9fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=635113490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.635113490
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1292636596
Short name T126
Test name
Test status
Simulation time 51350053299 ps
CPU time 1017.5 seconds
Started Jul 12 05:58:59 PM PDT 24
Finished Jul 12 06:16:19 PM PDT 24
Peak memory 265332 kb
Host smart-cce0b54f-950e-4e9c-b555-7861c5377f05
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292636596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1292636596
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2175488109
Short name T166
Test name
Test status
Simulation time 1304933275 ps
CPU time 84.31 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 06:00:47 PM PDT 24
Peak memory 246228 kb
Host smart-45be459b-40a2-4cfe-b7cf-252e1625661d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2175488109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2175488109
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3860655299
Short name T162
Test name
Test status
Simulation time 88187177 ps
CPU time 5.26 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:08 PM PDT 24
Peak memory 237392 kb
Host smart-509e1bdd-a040-4b6b-bc53-da3743789520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3860655299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3860655299
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.484119942
Short name T164
Test name
Test status
Simulation time 33410605 ps
CPU time 2.19 seconds
Started Jul 12 05:58:30 PM PDT 24
Finished Jul 12 05:59:02 PM PDT 24
Peak memory 237556 kb
Host smart-4f8cae25-0ad5-4f59-99e3-fe1e14f89af7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=484119942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.484119942
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3204589548
Short name T163
Test name
Test status
Simulation time 189139819 ps
CPU time 3.59 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 05:59:01 PM PDT 24
Peak memory 237940 kb
Host smart-1e441dde-e432-4cd9-acfb-0c457bee7dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3204589548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3204589548
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1258955839
Short name T165
Test name
Test status
Simulation time 52510316 ps
CPU time 2.66 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:06 PM PDT 24
Peak memory 237980 kb
Host smart-4086af6f-bb33-4251-940e-7b8d8933828b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1258955839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1258955839
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1859320171
Short name T24
Test name
Test status
Simulation time 266569839563 ps
CPU time 2001.56 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 05:18:59 PM PDT 24
Peak memory 306688 kb
Host smart-432d5576-cd19-4509-9752-73433dde1a4f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859320171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1859320171
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3217635809
Short name T759
Test name
Test status
Simulation time 16888791127 ps
CPU time 262.1 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 06:03:19 PM PDT 24
Peak memory 240588 kb
Host smart-30479a5d-eda2-4ecb-adfd-9ff8c4740f67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3217635809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3217635809
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2617983323
Short name T777
Test name
Test status
Simulation time 10558892766 ps
CPU time 195.45 seconds
Started Jul 12 05:58:27 PM PDT 24
Finished Jul 12 06:02:11 PM PDT 24
Peak memory 237644 kb
Host smart-76b3f0fa-954c-426f-9614-818cb3266119
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2617983323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2617983323
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4069196217
Short name T216
Test name
Test status
Simulation time 21859174 ps
CPU time 4.03 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 05:59:01 PM PDT 24
Peak memory 248672 kb
Host smart-301e66fc-4434-414f-b4ff-bc65bcb8bffa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4069196217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4069196217
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.638938732
Short name T715
Test name
Test status
Simulation time 120454741 ps
CPU time 9.54 seconds
Started Jul 12 05:58:26 PM PDT 24
Finished Jul 12 05:59:05 PM PDT 24
Peak memory 256948 kb
Host smart-186c888a-4187-4206-aaff-de7ed0398513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638938732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.638938732
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2363375647
Short name T794
Test name
Test status
Simulation time 126934356 ps
CPU time 5.29 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:08 PM PDT 24
Peak memory 237532 kb
Host smart-2e81f277-8573-489b-b857-7e53db5b206f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2363375647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2363375647
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2790115925
Short name T752
Test name
Test status
Simulation time 10926906 ps
CPU time 1.39 seconds
Started Jul 12 05:58:27 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 237532 kb
Host smart-a8485cb8-1e20-4492-b6ec-fcc89c8083a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2790115925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2790115925
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.752800053
Short name T793
Test name
Test status
Simulation time 1467972698 ps
CPU time 42.47 seconds
Started Jul 12 05:58:26 PM PDT 24
Finished Jul 12 05:59:38 PM PDT 24
Peak memory 245760 kb
Host smart-c07119c4-e4c2-490a-8361-fa5963ab186a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=752800053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.752800053
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2116487401
Short name T124
Test name
Test status
Simulation time 34246421512 ps
CPU time 382.25 seconds
Started Jul 12 05:58:23 PM PDT 24
Finished Jul 12 06:05:14 PM PDT 24
Peak memory 265404 kb
Host smart-432af5b1-54f7-40ec-8518-93c86b121e90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2116487401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2116487401
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3681233185
Short name T142
Test name
Test status
Simulation time 17669355503 ps
CPU time 649.68 seconds
Started Jul 12 05:58:23 PM PDT 24
Finished Jul 12 06:09:42 PM PDT 24
Peak memory 265384 kb
Host smart-8ce5edbf-40ec-481a-a3a2-948d8f312419
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681233185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3681233185
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2917213641
Short name T735
Test name
Test status
Simulation time 191150182 ps
CPU time 13.07 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 05:59:03 PM PDT 24
Peak memory 248204 kb
Host smart-2c3bc1a2-f87f-46a6-a8d8-3aa1fd076899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2917213641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2917213641
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3292627130
Short name T774
Test name
Test status
Simulation time 2320004495 ps
CPU time 74.02 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 06:00:12 PM PDT 24
Peak memory 237624 kb
Host smart-e4ffa346-414a-47cb-aed3-0289e9f4b205
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3292627130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3292627130
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1606477681
Short name T830
Test name
Test status
Simulation time 3407551808 ps
CPU time 105.52 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 06:00:43 PM PDT 24
Peak memory 237620 kb
Host smart-5569c9a1-4349-43fc-9c5e-84da3400d563
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1606477681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1606477681
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.331700894
Short name T721
Test name
Test status
Simulation time 39129135 ps
CPU time 6.24 seconds
Started Jul 12 05:58:29 PM PDT 24
Finished Jul 12 05:59:04 PM PDT 24
Peak memory 248696 kb
Host smart-48df11b2-1114-4e83-8817-007e5c989857
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=331700894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.331700894
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2863265358
Short name T778
Test name
Test status
Simulation time 124129522 ps
CPU time 8.16 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 253980 kb
Host smart-07b8a8a4-9683-4e35-8529-0f71f0cf34dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863265358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2863265358
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1451448072
Short name T729
Test name
Test status
Simulation time 66934159 ps
CPU time 5.05 seconds
Started Jul 12 05:58:27 PM PDT 24
Finished Jul 12 05:59:01 PM PDT 24
Peak memory 237504 kb
Host smart-bcb19b7b-0cb3-47f1-ab24-130c61f40c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1451448072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1451448072
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3956112223
Short name T751
Test name
Test status
Simulation time 6825062 ps
CPU time 1.44 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 05:58:59 PM PDT 24
Peak memory 236556 kb
Host smart-8f9f6750-edcd-4610-8b79-063a7c31d364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3956112223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3956112223
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.4232471311
Short name T725
Test name
Test status
Simulation time 399156274 ps
CPU time 22.5 seconds
Started Jul 12 05:58:29 PM PDT 24
Finished Jul 12 05:59:22 PM PDT 24
Peak memory 245744 kb
Host smart-83e8e6e1-2c80-407d-babd-6edb15b6e421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4232471311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.4232471311
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1696060897
Short name T127
Test name
Test status
Simulation time 1051629166 ps
CPU time 109.79 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 06:00:47 PM PDT 24
Peak memory 257116 kb
Host smart-cd8e8e3b-ee13-4214-9e9e-c5ea431305a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1696060897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1696060897
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.417441982
Short name T135
Test name
Test status
Simulation time 2297634876 ps
CPU time 365.91 seconds
Started Jul 12 05:58:30 PM PDT 24
Finished Jul 12 06:05:06 PM PDT 24
Peak memory 265328 kb
Host smart-fb60b576-a686-4b5a-b6ee-d72b3a6a2883
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417441982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.417441982
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.40717469
Short name T723
Test name
Test status
Simulation time 436399256 ps
CPU time 15.29 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 05:59:13 PM PDT 24
Peak memory 254728 kb
Host smart-631a3fb6-ccee-4ec0-a462-0d921d58c86b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=40717469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.40717469
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.19254177
Short name T779
Test name
Test status
Simulation time 236385820 ps
CPU time 6.02 seconds
Started Jul 12 05:58:51 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 240540 kb
Host smart-c9d843d0-fdce-4d86-bc19-e706aff2d56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19254177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.alert_handler_csr_mem_rw_with_rand_reset.19254177
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3682048214
Short name T786
Test name
Test status
Simulation time 105827129 ps
CPU time 7.13 seconds
Started Jul 12 05:58:48 PM PDT 24
Finished Jul 12 05:59:20 PM PDT 24
Peak memory 240504 kb
Host smart-4cddd144-b196-4f03-91ad-2af50ecaa214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3682048214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3682048214
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2649199667
Short name T336
Test name
Test status
Simulation time 8113334 ps
CPU time 1.53 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 05:59:16 PM PDT 24
Peak memory 237552 kb
Host smart-723c7e87-22d9-4c45-a447-477f87e0f34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2649199667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2649199667
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3489196535
Short name T823
Test name
Test status
Simulation time 113526920 ps
CPU time 14.45 seconds
Started Jul 12 05:58:51 PM PDT 24
Finished Jul 12 05:59:31 PM PDT 24
Peak memory 248680 kb
Host smart-ca890da2-8054-4d90-9ae6-a69c16917e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3489196535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3489196535
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1150830428
Short name T748
Test name
Test status
Simulation time 52830150 ps
CPU time 7.07 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 05:59:22 PM PDT 24
Peak memory 248720 kb
Host smart-6d9365e0-f7a3-4f6b-bde6-c622201973f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1150830428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1150830428
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1808386705
Short name T226
Test name
Test status
Simulation time 238598892 ps
CPU time 8.57 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 05:59:27 PM PDT 24
Peak memory 240564 kb
Host smart-1bd787c4-ff69-4d50-81ef-1dad560e26ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808386705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1808386705
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1855522461
Short name T767
Test name
Test status
Simulation time 23036725 ps
CPU time 3.83 seconds
Started Jul 12 05:58:55 PM PDT 24
Finished Jul 12 05:59:23 PM PDT 24
Peak memory 237524 kb
Host smart-b0828a23-2458-41fd-b14e-d33b73791b16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1855522461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1855522461
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3939551040
Short name T783
Test name
Test status
Simulation time 28618392 ps
CPU time 1.36 seconds
Started Jul 12 05:58:54 PM PDT 24
Finished Jul 12 05:59:20 PM PDT 24
Peak memory 237548 kb
Host smart-ab15d29e-38f4-4845-890b-9cb1d47c0704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939551040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3939551040
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4064469390
Short name T798
Test name
Test status
Simulation time 583179526 ps
CPU time 13.5 seconds
Started Jul 12 05:58:54 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 245760 kb
Host smart-1d38af18-b295-4c7a-bf4c-b8bc9c92faac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4064469390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4064469390
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3364288174
Short name T145
Test name
Test status
Simulation time 3699998204 ps
CPU time 277.22 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 06:03:52 PM PDT 24
Peak memory 271028 kb
Host smart-3d29fbc3-8d0e-4f32-affc-66211e5d1808
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364288174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3364288174
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.254582564
Short name T821
Test name
Test status
Simulation time 6007193312 ps
CPU time 438.78 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 06:06:34 PM PDT 24
Peak memory 268140 kb
Host smart-da293fc3-86f5-4c69-8813-ccd36b695707
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254582564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.254582564
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3156241583
Short name T815
Test name
Test status
Simulation time 1406778700 ps
CPU time 21.31 seconds
Started Jul 12 05:58:51 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 255340 kb
Host smart-a74b19a6-db8c-4c71-82fe-07f1278d894f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3156241583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3156241583
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4206753152
Short name T770
Test name
Test status
Simulation time 281494406 ps
CPU time 10.03 seconds
Started Jul 12 05:58:55 PM PDT 24
Finished Jul 12 05:59:29 PM PDT 24
Peak memory 239496 kb
Host smart-1f565e14-dca6-4475-87e9-e8a0e4ddf2e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206753152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4206753152
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1508470709
Short name T816
Test name
Test status
Simulation time 462466046 ps
CPU time 8.93 seconds
Started Jul 12 05:58:55 PM PDT 24
Finished Jul 12 05:59:28 PM PDT 24
Peak memory 237572 kb
Host smart-a8d54654-d4e8-4831-b751-9ee163c069d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1508470709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1508470709
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3575108947
Short name T152
Test name
Test status
Simulation time 12606252 ps
CPU time 1.65 seconds
Started Jul 12 05:58:55 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 236628 kb
Host smart-10c04dea-5aa0-4b1d-8c8a-4e8b9f9dddd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575108947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3575108947
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.918684668
Short name T781
Test name
Test status
Simulation time 307769249 ps
CPU time 21.25 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 05:59:38 PM PDT 24
Peak memory 244668 kb
Host smart-828df1bd-5706-42c1-b409-f36a951e1b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=918684668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.918684668
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2761166812
Short name T119
Test name
Test status
Simulation time 6294301540 ps
CPU time 351.49 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 06:05:09 PM PDT 24
Peak memory 265560 kb
Host smart-fecffd3a-b594-4e52-bc43-2a0ddd1d31a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2761166812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2761166812
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.764992179
Short name T712
Test name
Test status
Simulation time 226770395 ps
CPU time 16.1 seconds
Started Jul 12 05:58:54 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 253916 kb
Host smart-cb7a8378-4629-4efa-a4e9-00de1d3881ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=764992179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.764992179
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3556867791
Short name T822
Test name
Test status
Simulation time 115110483 ps
CPU time 9.72 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 256936 kb
Host smart-c8b9ea9f-e3fc-48fc-9865-268058f55d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556867791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3556867791
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3096818930
Short name T750
Test name
Test status
Simulation time 565768033 ps
CPU time 7.87 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 05:59:30 PM PDT 24
Peak memory 240472 kb
Host smart-45e91460-a408-4c38-8f07-e6e4a7ce7269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3096818930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3096818930
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3999758794
Short name T797
Test name
Test status
Simulation time 10854492 ps
CPU time 1.33 seconds
Started Jul 12 05:58:55 PM PDT 24
Finished Jul 12 05:59:20 PM PDT 24
Peak memory 236612 kb
Host smart-5bb94691-bf24-4c0f-af8e-17ae53ab5228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3999758794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3999758794
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1394045079
Short name T791
Test name
Test status
Simulation time 1445764795 ps
CPU time 20.57 seconds
Started Jul 12 05:59:02 PM PDT 24
Finished Jul 12 05:59:44 PM PDT 24
Peak memory 244792 kb
Host smart-c2f7ba40-d55f-4b18-b111-f45f31766bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1394045079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1394045079
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.138947732
Short name T138
Test name
Test status
Simulation time 9703207170 ps
CPU time 167.5 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 06:02:05 PM PDT 24
Peak memory 265396 kb
Host smart-55cba091-ea07-47fa-8e52-2f858899eac8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138947732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.138947732
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3731248864
Short name T115
Test name
Test status
Simulation time 2135689205 ps
CPU time 311.72 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 06:04:29 PM PDT 24
Peak memory 268972 kb
Host smart-fdbb31f9-af6b-4fa1-b63a-9b5ca3fd41dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731248864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3731248864
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2841373677
Short name T741
Test name
Test status
Simulation time 64346435 ps
CPU time 8.34 seconds
Started Jul 12 05:58:53 PM PDT 24
Finished Jul 12 05:59:25 PM PDT 24
Peak memory 248728 kb
Host smart-c6e63d9c-f1cd-49b2-ad89-6e69b7589feb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2841373677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2841373677
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3806136967
Short name T342
Test name
Test status
Simulation time 162321653 ps
CPU time 10.92 seconds
Started Jul 12 05:59:02 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 252680 kb
Host smart-56d303a5-4c23-4510-8a1e-0f3c9059fcd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806136967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3806136967
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3932054081
Short name T726
Test name
Test status
Simulation time 436923976 ps
CPU time 9.39 seconds
Started Jul 12 05:58:59 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 236548 kb
Host smart-41c0d190-4dca-4252-ba09-432a44659eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3932054081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3932054081
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1452378652
Short name T788
Test name
Test status
Simulation time 14043277 ps
CPU time 1.42 seconds
Started Jul 12 05:58:59 PM PDT 24
Finished Jul 12 05:59:25 PM PDT 24
Peak memory 237556 kb
Host smart-ec786b91-d419-49d2-acd5-2ba22db0f6c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1452378652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1452378652
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1035447900
Short name T746
Test name
Test status
Simulation time 654303112 ps
CPU time 21 seconds
Started Jul 12 05:59:02 PM PDT 24
Finished Jul 12 05:59:45 PM PDT 24
Peak memory 245776 kb
Host smart-1bd825da-3981-463c-92ab-ca9c1f220f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1035447900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1035447900
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4157598017
Short name T720
Test name
Test status
Simulation time 1446909013 ps
CPU time 8.9 seconds
Started Jul 12 05:58:59 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 252892 kb
Host smart-16ce924e-24f6-4687-b154-945453483f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4157598017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4157598017
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1787132321
Short name T719
Test name
Test status
Simulation time 112970840 ps
CPU time 8 seconds
Started Jul 12 05:59:04 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 240504 kb
Host smart-ab0a8137-390d-4c13-ab99-7d13cf7c647d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787132321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1787132321
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2671606102
Short name T814
Test name
Test status
Simulation time 33620146 ps
CPU time 4.75 seconds
Started Jul 12 05:58:59 PM PDT 24
Finished Jul 12 05:59:28 PM PDT 24
Peak memory 236600 kb
Host smart-96ef7aba-5cf2-4734-998e-09f9300c4b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2671606102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2671606102
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1358056745
Short name T820
Test name
Test status
Simulation time 171357808 ps
CPU time 25.78 seconds
Started Jul 12 05:59:02 PM PDT 24
Finished Jul 12 05:59:50 PM PDT 24
Peak memory 248688 kb
Host smart-c5087b47-1525-4ba0-b6fc-39024f3e362b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1358056745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1358056745
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1905350843
Short name T143
Test name
Test status
Simulation time 2219856291 ps
CPU time 140.05 seconds
Started Jul 12 05:59:00 PM PDT 24
Finished Jul 12 06:01:43 PM PDT 24
Peak memory 265412 kb
Host smart-57cfe9ef-3fa8-40f1-a269-57592eac1284
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1905350843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1905350843
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1873010849
Short name T782
Test name
Test status
Simulation time 319388424 ps
CPU time 7.79 seconds
Started Jul 12 05:58:59 PM PDT 24
Finished Jul 12 05:59:31 PM PDT 24
Peak memory 254592 kb
Host smart-53452956-3eaa-40f6-a35a-bab206657aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1873010849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1873010849
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.622803916
Short name T800
Test name
Test status
Simulation time 350646591 ps
CPU time 6.68 seconds
Started Jul 12 05:59:04 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 254152 kb
Host smart-72ffb62a-c733-40bb-a004-9757ecc8ab1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622803916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.622803916
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3046135833
Short name T813
Test name
Test status
Simulation time 138177053 ps
CPU time 5.66 seconds
Started Jul 12 05:59:03 PM PDT 24
Finished Jul 12 05:59:31 PM PDT 24
Peak memory 237560 kb
Host smart-0c8759ad-156f-43d9-bd61-1510739c7f49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3046135833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3046135833
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1922137777
Short name T772
Test name
Test status
Simulation time 176637237 ps
CPU time 11.48 seconds
Started Jul 12 05:59:05 PM PDT 24
Finished Jul 12 05:59:38 PM PDT 24
Peak memory 244800 kb
Host smart-ef2c6d79-0216-437d-a8ce-b227c6cfa8a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1922137777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1922137777
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1743546635
Short name T144
Test name
Test status
Simulation time 1709402559 ps
CPU time 110.88 seconds
Started Jul 12 05:59:06 PM PDT 24
Finished Jul 12 06:01:17 PM PDT 24
Peak memory 265272 kb
Host smart-25dc9f4e-ad0c-4a8e-b304-95d4ae92a034
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1743546635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1743546635
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2521415039
Short name T123
Test name
Test status
Simulation time 24960109853 ps
CPU time 989.7 seconds
Started Jul 12 05:59:07 PM PDT 24
Finished Jul 12 06:15:57 PM PDT 24
Peak memory 272640 kb
Host smart-bc0e49b3-2d13-488f-904c-1e1865db8239
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521415039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2521415039
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3011756052
Short name T714
Test name
Test status
Simulation time 66380110 ps
CPU time 6.37 seconds
Started Jul 12 05:59:06 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 250968 kb
Host smart-395b00c1-012d-4b15-bd0e-28e41ec726b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3011756052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3011756052
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.860984019
Short name T758
Test name
Test status
Simulation time 955098172 ps
CPU time 38.3 seconds
Started Jul 12 05:59:06 PM PDT 24
Finished Jul 12 06:00:05 PM PDT 24
Peak memory 240512 kb
Host smart-b88d9789-b4e3-4cae-a506-909471d6c3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=860984019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.860984019
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.529970565
Short name T818
Test name
Test status
Simulation time 108128474 ps
CPU time 9.65 seconds
Started Jul 12 05:59:07 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 240644 kb
Host smart-a61572a2-903c-41fd-82d9-e9063798bffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529970565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.529970565
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2575663149
Short name T184
Test name
Test status
Simulation time 100228113 ps
CPU time 4.64 seconds
Started Jul 12 05:59:04 PM PDT 24
Finished Jul 12 05:59:30 PM PDT 24
Peak memory 240476 kb
Host smart-66bf98a0-7c33-4629-a153-c6366d3a0c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2575663149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2575663149
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.469368014
Short name T819
Test name
Test status
Simulation time 11768896 ps
CPU time 1.46 seconds
Started Jul 12 05:59:06 PM PDT 24
Finished Jul 12 05:59:28 PM PDT 24
Peak memory 237456 kb
Host smart-873892d8-dade-4b0c-afae-d2d5ba36f208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469368014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.469368014
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2536577056
Short name T188
Test name
Test status
Simulation time 166978560 ps
CPU time 22.26 seconds
Started Jul 12 05:59:04 PM PDT 24
Finished Jul 12 05:59:48 PM PDT 24
Peak memory 248708 kb
Host smart-96b4bab5-75c1-4099-be33-ee04004b72e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2536577056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2536577056
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3241856283
Short name T139
Test name
Test status
Simulation time 4892397705 ps
CPU time 324.07 seconds
Started Jul 12 05:59:04 PM PDT 24
Finished Jul 12 06:04:50 PM PDT 24
Peak memory 265404 kb
Host smart-cd735940-2b77-4cb9-9a84-a6e1f7de859b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3241856283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3241856283
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3268775296
Short name T128
Test name
Test status
Simulation time 16510678008 ps
CPU time 555.31 seconds
Started Jul 12 05:59:05 PM PDT 24
Finished Jul 12 06:08:42 PM PDT 24
Peak memory 265608 kb
Host smart-745c98b2-27db-4d2c-b8b3-77c29964660a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268775296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3268775296
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2815293880
Short name T827
Test name
Test status
Simulation time 48576202 ps
CPU time 5.74 seconds
Started Jul 12 05:59:07 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 254760 kb
Host smart-6896f632-a25e-485e-bcae-38fdb13fb7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2815293880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2815293880
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3325035640
Short name T148
Test name
Test status
Simulation time 23265477 ps
CPU time 2.36 seconds
Started Jul 12 05:59:04 PM PDT 24
Finished Jul 12 05:59:28 PM PDT 24
Peak memory 237772 kb
Host smart-7eb662c5-db6c-4291-a50b-1e7b6702434a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3325035640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3325035640
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.766862506
Short name T722
Test name
Test status
Simulation time 156004837 ps
CPU time 7.05 seconds
Started Jul 12 05:59:11 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 240972 kb
Host smart-7d5183c1-1e40-46b5-ad2b-6d0ba8ffd4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766862506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.766862506
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1602695003
Short name T829
Test name
Test status
Simulation time 187572950 ps
CPU time 4.76 seconds
Started Jul 12 05:59:11 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 240432 kb
Host smart-3b210a49-ff8b-4b81-96e9-54d53542a523
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1602695003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1602695003
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.851408040
Short name T738
Test name
Test status
Simulation time 17920465 ps
CPU time 1.9 seconds
Started Jul 12 05:59:11 PM PDT 24
Finished Jul 12 05:59:31 PM PDT 24
Peak memory 237556 kb
Host smart-0e0dc666-ac30-4609-b23e-67494df3776a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=851408040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.851408040
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2367890844
Short name T785
Test name
Test status
Simulation time 346761051 ps
CPU time 26.08 seconds
Started Jul 12 05:59:11 PM PDT 24
Finished Jul 12 05:59:55 PM PDT 24
Peak memory 245728 kb
Host smart-8668fe06-7037-4de7-a0ea-f0722fe81146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2367890844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2367890844
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4164203375
Short name T133
Test name
Test status
Simulation time 6687410515 ps
CPU time 386.73 seconds
Started Jul 12 05:59:10 PM PDT 24
Finished Jul 12 06:05:55 PM PDT 24
Peak memory 265436 kb
Host smart-6fcf74c2-3fe7-4cc1-8437-1d17b6fae4d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4164203375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4164203375
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1654884354
Short name T117
Test name
Test status
Simulation time 30124892663 ps
CPU time 321.22 seconds
Started Jul 12 05:59:10 PM PDT 24
Finished Jul 12 06:04:50 PM PDT 24
Peak memory 268196 kb
Host smart-fc730341-883c-4746-ae9d-ddd6b053b292
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654884354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1654884354
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3443145890
Short name T711
Test name
Test status
Simulation time 1298322864 ps
CPU time 19.67 seconds
Started Jul 12 05:59:08 PM PDT 24
Finished Jul 12 05:59:47 PM PDT 24
Peak memory 248676 kb
Host smart-0fab9e03-7849-4ee7-b8db-59ecee6a8289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443145890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3443145890
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2439389054
Short name T156
Test name
Test status
Simulation time 1209520106 ps
CPU time 44.29 seconds
Started Jul 12 05:59:08 PM PDT 24
Finished Jul 12 06:00:12 PM PDT 24
Peak memory 240504 kb
Host smart-5cefb049-89c2-48a4-b14d-ba8513437db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2439389054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2439389054
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2027442160
Short name T341
Test name
Test status
Simulation time 387566618 ps
CPU time 9.9 seconds
Started Jul 12 05:59:16 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 251956 kb
Host smart-3b481477-2c0e-42fe-ab85-ab3f1f9df785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027442160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2027442160
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3936963444
Short name T716
Test name
Test status
Simulation time 359263529 ps
CPU time 5.55 seconds
Started Jul 12 05:59:15 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 237552 kb
Host smart-7caa3d59-ea82-46a8-bcf5-afe05879d24d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3936963444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3936963444
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2836961333
Short name T332
Test name
Test status
Simulation time 26240624 ps
CPU time 1.59 seconds
Started Jul 12 05:59:14 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 237428 kb
Host smart-0df758fc-b554-468b-8d15-82df3d1995ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2836961333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2836961333
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.249444086
Short name T189
Test name
Test status
Simulation time 718054814 ps
CPU time 24.24 seconds
Started Jul 12 05:59:15 PM PDT 24
Finished Jul 12 05:59:55 PM PDT 24
Peak memory 245748 kb
Host smart-38b386bc-c8e2-4a06-936a-0d4d8a5d1ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=249444086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.249444086
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3996712573
Short name T146
Test name
Test status
Simulation time 5674459761 ps
CPU time 305.01 seconds
Started Jul 12 05:59:10 PM PDT 24
Finished Jul 12 06:04:33 PM PDT 24
Peak memory 269992 kb
Host smart-f71cdd91-b781-4b81-877a-a22d0e4ab73d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996712573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3996712573
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.427975252
Short name T710
Test name
Test status
Simulation time 77325819 ps
CPU time 5.51 seconds
Started Jul 12 05:59:11 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 248892 kb
Host smart-0c662c5a-4f24-4d4f-bc0b-10d2a90e9f12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=427975252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.427975252
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1716689051
Short name T795
Test name
Test status
Simulation time 6350552607 ps
CPU time 266.66 seconds
Started Jul 12 05:58:33 PM PDT 24
Finished Jul 12 06:03:29 PM PDT 24
Peak memory 240808 kb
Host smart-08624229-884e-48b3-9611-d28b78c66bf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1716689051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1716689051
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4159179921
Short name T743
Test name
Test status
Simulation time 3406690222 ps
CPU time 130.37 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 06:01:14 PM PDT 24
Peak memory 237604 kb
Host smart-c24b5e21-ecc4-4d03-b75c-4e7da0bc1897
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4159179921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4159179921
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3872893274
Short name T183
Test name
Test status
Simulation time 341678395 ps
CPU time 5.54 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 05:59:09 PM PDT 24
Peak memory 248940 kb
Host smart-e339320c-7256-4816-8eb7-ad3a075ecefc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3872893274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3872893274
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3054228571
Short name T747
Test name
Test status
Simulation time 134910516 ps
CPU time 5.58 seconds
Started Jul 12 05:58:32 PM PDT 24
Finished Jul 12 05:59:07 PM PDT 24
Peak memory 248756 kb
Host smart-65780584-3cf8-4ee6-8d7d-88c64963cf95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054228571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3054228571
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.304226051
Short name T187
Test name
Test status
Simulation time 91180075 ps
CPU time 5.3 seconds
Started Jul 12 05:58:31 PM PDT 24
Finished Jul 12 05:59:07 PM PDT 24
Peak memory 237552 kb
Host smart-2bac62f0-545c-486e-9b81-d761bc7222f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=304226051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.304226051
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.191831224
Short name T754
Test name
Test status
Simulation time 24276438 ps
CPU time 1.55 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:05 PM PDT 24
Peak memory 237548 kb
Host smart-8b399bde-03f8-4537-9b12-c08aca3d986e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=191831224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.191831224
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4060259873
Short name T742
Test name
Test status
Simulation time 327903243 ps
CPU time 22.49 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 05:59:26 PM PDT 24
Peak memory 248660 kb
Host smart-50215e09-af79-4d02-b037-e64a35df781d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4060259873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4060259873
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1974598617
Short name T113
Test name
Test status
Simulation time 2208770451 ps
CPU time 147.28 seconds
Started Jul 12 05:58:30 PM PDT 24
Finished Jul 12 06:01:27 PM PDT 24
Peak memory 266512 kb
Host smart-ffb4c70d-46a4-47ed-bd21-1948b07ea7f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1974598617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1974598617
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3085581328
Short name T744
Test name
Test status
Simulation time 213886750 ps
CPU time 7.53 seconds
Started Jul 12 05:58:28 PM PDT 24
Finished Jul 12 05:59:05 PM PDT 24
Peak memory 247056 kb
Host smart-76dd43a1-53f5-4d4f-a2b6-6124e22a0b76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3085581328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3085581328
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1490109322
Short name T808
Test name
Test status
Simulation time 8801543 ps
CPU time 1.51 seconds
Started Jul 12 05:59:16 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 237548 kb
Host smart-c53ed527-8f07-4f8f-bfd0-5185e33d5091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1490109322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1490109322
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2675048556
Short name T757
Test name
Test status
Simulation time 14728214 ps
CPU time 1.32 seconds
Started Jul 12 05:59:16 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 235764 kb
Host smart-a2847042-be51-4c28-bb83-4d9673bccb8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2675048556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2675048556
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4006073092
Short name T151
Test name
Test status
Simulation time 15380301 ps
CPU time 1.49 seconds
Started Jul 12 05:59:15 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 237512 kb
Host smart-a3f369d3-72e7-4bb8-aeab-ddfa8bc14e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4006073092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4006073092
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.638111317
Short name T828
Test name
Test status
Simulation time 16624920 ps
CPU time 1.36 seconds
Started Jul 12 05:59:18 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 237544 kb
Host smart-5177e74c-b0a8-43a7-b0d1-7f0576a5343d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=638111317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.638111317
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1590896200
Short name T807
Test name
Test status
Simulation time 13691977 ps
CPU time 1.5 seconds
Started Jul 12 05:59:15 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 236600 kb
Host smart-d1dd75ed-0fa0-42b6-bf24-8348d8a12f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1590896200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1590896200
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3010127062
Short name T787
Test name
Test status
Simulation time 11076786 ps
CPU time 1.27 seconds
Started Jul 12 05:59:17 PM PDT 24
Finished Jul 12 05:59:33 PM PDT 24
Peak memory 236620 kb
Host smart-12660c7c-9de2-414c-84f1-49e3b4d8aa3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010127062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3010127062
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.550030041
Short name T763
Test name
Test status
Simulation time 8718027 ps
CPU time 1.66 seconds
Started Jul 12 05:59:21 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 237576 kb
Host smart-f5749198-3ca8-47bf-a86e-d17d209ef878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=550030041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.550030041
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1092199673
Short name T728
Test name
Test status
Simulation time 21123082 ps
CPU time 1.4 seconds
Started Jul 12 05:59:22 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 237576 kb
Host smart-eed352c0-3054-4d73-814f-4742bdcbf40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1092199673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1092199673
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2773269987
Short name T831
Test name
Test status
Simulation time 18235858 ps
CPU time 1.35 seconds
Started Jul 12 05:59:22 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 237564 kb
Host smart-305d529c-0cf2-4d9f-b9a1-9f6f7eed470e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2773269987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2773269987
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1804825724
Short name T168
Test name
Test status
Simulation time 2221175578 ps
CPU time 153.6 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 06:01:37 PM PDT 24
Peak memory 237604 kb
Host smart-eaa51374-c773-48b4-bc10-c83f378f90b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1804825724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1804825724
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4175332846
Short name T717
Test name
Test status
Simulation time 15464421434 ps
CPU time 347.19 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 06:04:50 PM PDT 24
Peak memory 240588 kb
Host smart-24376d4f-86b6-4386-af9d-faaaa2157b30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4175332846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4175332846
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4052093354
Short name T182
Test name
Test status
Simulation time 376489009 ps
CPU time 9.22 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 05:59:13 PM PDT 24
Peak memory 249084 kb
Host smart-91e983bb-9104-463e-9deb-78b5251abb99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4052093354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4052093354
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3966603304
Short name T225
Test name
Test status
Simulation time 77525826 ps
CPU time 6.18 seconds
Started Jul 12 05:58:32 PM PDT 24
Finished Jul 12 05:59:07 PM PDT 24
Peak memory 240532 kb
Host smart-1f88dcac-a29b-4119-a33b-479ac5769d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966603304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3966603304
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.190790236
Short name T796
Test name
Test status
Simulation time 364134725 ps
CPU time 7.41 seconds
Started Jul 12 05:58:33 PM PDT 24
Finished Jul 12 05:59:10 PM PDT 24
Peak memory 240452 kb
Host smart-752d0ec9-6c9e-435a-b6e1-94a37784dd25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=190790236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.190790236
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3046000239
Short name T775
Test name
Test status
Simulation time 6477919 ps
CPU time 1.43 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:05 PM PDT 24
Peak memory 236696 kb
Host smart-ccbfb81d-b9aa-4233-9cb1-9afa900c58c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3046000239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3046000239
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1579954276
Short name T806
Test name
Test status
Simulation time 942521400 ps
CPU time 21.55 seconds
Started Jul 12 05:58:34 PM PDT 24
Finished Jul 12 05:59:24 PM PDT 24
Peak memory 245772 kb
Host smart-cd4440eb-d832-4e39-a61d-a5f5b85915bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1579954276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1579954276
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2584661942
Short name T343
Test name
Test status
Simulation time 4294008771 ps
CPU time 343.05 seconds
Started Jul 12 05:58:32 PM PDT 24
Finished Jul 12 06:04:45 PM PDT 24
Peak memory 265500 kb
Host smart-198514e4-9145-4130-9541-6b50986d215d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584661942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2584661942
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4148167123
Short name T768
Test name
Test status
Simulation time 251277395 ps
CPU time 15.87 seconds
Started Jul 12 05:58:33 PM PDT 24
Finished Jul 12 05:59:19 PM PDT 24
Peak memory 248528 kb
Host smart-999d8b1e-4c8a-4a7d-af79-9dd4b8bc41f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4148167123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4148167123
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3401190079
Short name T339
Test name
Test status
Simulation time 6684171 ps
CPU time 1.49 seconds
Started Jul 12 05:59:20 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 237544 kb
Host smart-cdb7e6f1-f9a7-4a94-92f2-d5e577f31cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3401190079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3401190079
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.506027704
Short name T801
Test name
Test status
Simulation time 15758715 ps
CPU time 1.32 seconds
Started Jul 12 05:59:21 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 235612 kb
Host smart-64184dc7-93be-4814-9f9a-ff731f1014ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=506027704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.506027704
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.58184897
Short name T762
Test name
Test status
Simulation time 11233823 ps
CPU time 1.39 seconds
Started Jul 12 05:59:21 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 237564 kb
Host smart-96815ada-3a59-41dd-9c45-b3a2df2ec018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58184897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.58184897
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.386290717
Short name T733
Test name
Test status
Simulation time 11939787 ps
CPU time 1.43 seconds
Started Jul 12 05:59:21 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 236612 kb
Host smart-f1985455-6e8c-40f8-8954-94fcfd968f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=386290717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.386290717
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.923898841
Short name T812
Test name
Test status
Simulation time 18490636 ps
CPU time 1.44 seconds
Started Jul 12 05:59:23 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 237544 kb
Host smart-de3db480-d961-4550-a618-979f6d700190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=923898841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.923898841
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4283574288
Short name T736
Test name
Test status
Simulation time 11212488 ps
CPU time 1.25 seconds
Started Jul 12 05:59:22 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 236708 kb
Host smart-c21b92f2-ad4a-40e2-abc0-831f929e0ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4283574288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4283574288
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1225880008
Short name T805
Test name
Test status
Simulation time 8404051 ps
CPU time 1.43 seconds
Started Jul 12 05:59:22 PM PDT 24
Finished Jul 12 05:59:35 PM PDT 24
Peak memory 236612 kb
Host smart-1247e683-c81a-41c2-8401-b655283c978e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225880008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1225880008
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2847081645
Short name T784
Test name
Test status
Simulation time 9670556 ps
CPU time 1.32 seconds
Started Jul 12 05:59:20 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 235596 kb
Host smart-829cab90-8b2c-451b-b4e5-e51a86525731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2847081645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2847081645
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.574395417
Short name T756
Test name
Test status
Simulation time 10968367 ps
CPU time 1.39 seconds
Started Jul 12 05:59:19 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 237564 kb
Host smart-6928deca-0d6b-4323-ba9c-d0e9a6a3fe0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=574395417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.574395417
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2542075501
Short name T817
Test name
Test status
Simulation time 8276571 ps
CPU time 1.48 seconds
Started Jul 12 05:59:27 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 235608 kb
Host smart-a27ffcc4-2825-41e2-81c8-1807d03169a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2542075501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2542075501
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.956358787
Short name T803
Test name
Test status
Simulation time 6739420659 ps
CPU time 108.56 seconds
Started Jul 12 05:58:38 PM PDT 24
Finished Jul 12 06:00:54 PM PDT 24
Peak memory 240568 kb
Host smart-819e5fa4-f62a-4409-83e3-fef0531ac8d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=956358787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.956358787
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3352778254
Short name T198
Test name
Test status
Simulation time 6803311692 ps
CPU time 170.7 seconds
Started Jul 12 05:58:36 PM PDT 24
Finished Jul 12 06:01:55 PM PDT 24
Peak memory 236676 kb
Host smart-9d69ff0d-06f4-4f23-b43d-c26307879301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3352778254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3352778254
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2066862566
Short name T773
Test name
Test status
Simulation time 140696881 ps
CPU time 6.05 seconds
Started Jul 12 05:58:33 PM PDT 24
Finished Jul 12 05:59:08 PM PDT 24
Peak memory 240572 kb
Host smart-f1ddaac8-7b53-41c4-89a2-e63a3a90490b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2066862566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2066862566
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.386918826
Short name T340
Test name
Test status
Simulation time 63543440 ps
CPU time 9.24 seconds
Started Jul 12 05:58:40 PM PDT 24
Finished Jul 12 05:59:16 PM PDT 24
Peak memory 254652 kb
Host smart-8c2cb513-1492-4c0b-8c53-54c223a23b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386918826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.386918826
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4056483534
Short name T169
Test name
Test status
Simulation time 20575276 ps
CPU time 3.7 seconds
Started Jul 12 05:58:39 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 240456 kb
Host smart-5f631718-bbb9-44e9-a165-bd27c303d3d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4056483534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4056483534
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4095279315
Short name T826
Test name
Test status
Simulation time 18762375 ps
CPU time 1.31 seconds
Started Jul 12 05:58:35 PM PDT 24
Finished Jul 12 05:59:05 PM PDT 24
Peak memory 236596 kb
Host smart-0f24a617-72cb-4c3b-a29e-42585fc12535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4095279315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4095279315
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3393266654
Short name T737
Test name
Test status
Simulation time 2451674466 ps
CPU time 43.19 seconds
Started Jul 12 05:58:39 PM PDT 24
Finished Jul 12 05:59:50 PM PDT 24
Peak memory 248724 kb
Host smart-5c255a7c-0a41-4b94-b6db-9f2f906e79cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3393266654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3393266654
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1719702900
Short name T825
Test name
Test status
Simulation time 9451797183 ps
CPU time 101.27 seconds
Started Jul 12 05:58:31 PM PDT 24
Finished Jul 12 06:00:42 PM PDT 24
Peak memory 265376 kb
Host smart-36efabfe-1d9e-4448-94ad-18152d9a328f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1719702900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1719702900
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2180621303
Short name T718
Test name
Test status
Simulation time 298989669 ps
CPU time 10.01 seconds
Started Jul 12 05:58:33 PM PDT 24
Finished Jul 12 05:59:12 PM PDT 24
Peak memory 248700 kb
Host smart-9fb03c12-f287-40f6-b7b5-c9a17afa5345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180621303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2180621303
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3429584227
Short name T765
Test name
Test status
Simulation time 10238037 ps
CPU time 1.34 seconds
Started Jul 12 05:59:26 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 235672 kb
Host smart-0edce83f-f4d7-40e5-b691-9b5f2810bf6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3429584227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3429584227
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.611426723
Short name T776
Test name
Test status
Simulation time 12273868 ps
CPU time 1.26 seconds
Started Jul 12 05:59:26 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 236592 kb
Host smart-b807ece7-c17f-4c52-8382-1dfe8a7216fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=611426723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.611426723
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3327956315
Short name T804
Test name
Test status
Simulation time 10503816 ps
CPU time 1.25 seconds
Started Jul 12 05:59:28 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 237576 kb
Host smart-b9f04189-738d-4277-8349-3ad4e22c5a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3327956315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3327956315
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3866584755
Short name T764
Test name
Test status
Simulation time 17299718 ps
CPU time 1.39 seconds
Started Jul 12 05:59:28 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 236572 kb
Host smart-25a1ad0b-7cb1-4c87-9016-f3beb7c3f12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3866584755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3866584755
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2709917293
Short name T745
Test name
Test status
Simulation time 17843376 ps
CPU time 1.37 seconds
Started Jul 12 05:59:28 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 236620 kb
Host smart-23185046-4916-4ac4-a693-e53048354628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2709917293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2709917293
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3675246705
Short name T739
Test name
Test status
Simulation time 11088861 ps
CPU time 1.31 seconds
Started Jul 12 05:59:27 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 237544 kb
Host smart-e0fc13e5-637d-4c82-9805-cf9c2c0c1c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3675246705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3675246705
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3122541991
Short name T749
Test name
Test status
Simulation time 27397574 ps
CPU time 1.52 seconds
Started Jul 12 05:59:26 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 237568 kb
Host smart-618d666e-f49a-441f-a88b-084381f78f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3122541991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3122541991
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2523323826
Short name T769
Test name
Test status
Simulation time 7705570 ps
CPU time 1.34 seconds
Started Jul 12 05:59:28 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 237576 kb
Host smart-d1f72601-78ee-4733-8075-a89ef2af94bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2523323826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2523323826
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2233345861
Short name T337
Test name
Test status
Simulation time 56223267 ps
CPU time 1.28 seconds
Started Jul 12 05:59:27 PM PDT 24
Finished Jul 12 05:59:37 PM PDT 24
Peak memory 235456 kb
Host smart-e5a8b7a7-6081-4016-8cdc-97f7155c6636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233345861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2233345861
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2523219163
Short name T809
Test name
Test status
Simulation time 7271454 ps
CPU time 1.44 seconds
Started Jul 12 05:59:26 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 235672 kb
Host smart-9e7aa3f5-f9bb-4c50-9206-4e4be0336b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2523219163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2523219163
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2529098418
Short name T755
Test name
Test status
Simulation time 56019906 ps
CPU time 7.21 seconds
Started Jul 12 05:58:37 PM PDT 24
Finished Jul 12 05:59:12 PM PDT 24
Peak memory 242616 kb
Host smart-c04a1e1c-20a6-48a4-b7ef-19a80b72f6ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529098418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2529098418
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.543654191
Short name T810
Test name
Test status
Simulation time 120965927 ps
CPU time 6.01 seconds
Started Jul 12 05:58:37 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 237572 kb
Host smart-a1167eef-3c67-40bb-81aa-0a1ee09d8513
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=543654191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.543654191
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3319903770
Short name T802
Test name
Test status
Simulation time 8756937 ps
CPU time 1.58 seconds
Started Jul 12 05:58:39 PM PDT 24
Finished Jul 12 05:59:09 PM PDT 24
Peak memory 237680 kb
Host smart-5fb7e2f1-cafb-47b6-a448-d39a21522a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3319903770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3319903770
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3813439201
Short name T727
Test name
Test status
Simulation time 1041528561 ps
CPU time 41.46 seconds
Started Jul 12 05:58:37 PM PDT 24
Finished Jul 12 05:59:46 PM PDT 24
Peak memory 248724 kb
Host smart-3b9c6e80-06d5-409a-a492-9183e8fbab14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813439201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3813439201
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2531296612
Short name T731
Test name
Test status
Simulation time 1311796589 ps
CPU time 21.78 seconds
Started Jul 12 05:58:41 PM PDT 24
Finished Jul 12 05:59:29 PM PDT 24
Peak memory 248200 kb
Host smart-698175c5-f055-4079-918e-990c7c1fa324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2531296612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2531296612
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1593119437
Short name T780
Test name
Test status
Simulation time 275121616 ps
CPU time 7.2 seconds
Started Jul 12 05:58:43 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 240532 kb
Host smart-61c6c0ee-a451-41b1-bc24-ac13df5f46e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593119437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1593119437
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3483943321
Short name T185
Test name
Test status
Simulation time 514291591 ps
CPU time 9.24 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:19 PM PDT 24
Peak memory 237516 kb
Host smart-02464cf4-1c8f-467a-bcc6-61fd8ac246b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3483943321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3483943321
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3568057592
Short name T789
Test name
Test status
Simulation time 6449478 ps
CPU time 1.36 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 237576 kb
Host smart-11e0a6e8-2e62-45ad-9ba0-314efa79bb86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3568057592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3568057592
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3769552546
Short name T799
Test name
Test status
Simulation time 699376680 ps
CPU time 47.24 seconds
Started Jul 12 05:58:48 PM PDT 24
Finished Jul 12 06:00:00 PM PDT 24
Peak memory 245776 kb
Host smart-129bba94-7307-418e-8c58-f32e0e931ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3769552546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3769552546
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2983836897
Short name T140
Test name
Test status
Simulation time 8237055970 ps
CPU time 620.97 seconds
Started Jul 12 05:58:38 PM PDT 24
Finished Jul 12 06:09:26 PM PDT 24
Peak memory 265408 kb
Host smart-41930d2a-ef9a-4826-ac39-e950b9bc5c2d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983836897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2983836897
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3003288162
Short name T724
Test name
Test status
Simulation time 1005942802 ps
CPU time 16.42 seconds
Started Jul 12 05:58:38 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 253868 kb
Host smart-fea220e1-ca35-4a6b-878a-4bf5bdd96fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3003288162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3003288162
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3780049396
Short name T811
Test name
Test status
Simulation time 567020701 ps
CPU time 9.09 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:20 PM PDT 24
Peak memory 256500 kb
Host smart-dbc0a405-3508-4de6-9735-63b9f0cf4257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780049396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3780049396
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1026404153
Short name T167
Test name
Test status
Simulation time 120322082 ps
CPU time 6.01 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:15 PM PDT 24
Peak memory 237560 kb
Host smart-a9ee7294-ff68-43f4-9cd2-cfeafa4fdea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1026404153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1026404153
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2651818366
Short name T790
Test name
Test status
Simulation time 10786990 ps
CPU time 1.36 seconds
Started Jul 12 05:58:46 PM PDT 24
Finished Jul 12 05:59:12 PM PDT 24
Peak memory 236472 kb
Host smart-cc599b94-5845-4988-a070-047e0d72f124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2651818366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2651818366
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1656743374
Short name T732
Test name
Test status
Simulation time 675338011 ps
CPU time 44.92 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:55 PM PDT 24
Peak memory 248664 kb
Host smart-73beb453-16b0-4e02-910f-ae02fb1da324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1656743374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1656743374
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1807669219
Short name T116
Test name
Test status
Simulation time 2898874769 ps
CPU time 154.54 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 06:01:45 PM PDT 24
Peak memory 268244 kb
Host smart-eda51231-f978-4a61-9577-ebe8e7b6aa6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1807669219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1807669219
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3665821288
Short name T734
Test name
Test status
Simulation time 94893461 ps
CPU time 6.2 seconds
Started Jul 12 05:58:46 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 248880 kb
Host smart-d5089abe-8a4c-43e6-b360-13f0acb36695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3665821288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3665821288
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3752743316
Short name T760
Test name
Test status
Simulation time 684494578 ps
CPU time 12.63 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:23 PM PDT 24
Peak memory 252072 kb
Host smart-d3e785df-93ae-4c2b-8d7b-95322f2d737f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752743316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3752743316
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.767417883
Short name T186
Test name
Test status
Simulation time 193868595 ps
CPU time 8.97 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 05:59:24 PM PDT 24
Peak memory 237564 kb
Host smart-fa0da005-21e3-4480-bc19-1d1a10ea5567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=767417883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.767417883
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3933939470
Short name T153
Test name
Test status
Simulation time 17460356 ps
CPU time 1.46 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:12 PM PDT 24
Peak memory 235592 kb
Host smart-c60f4ca6-5f33-4b62-82e1-534b82d5a886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933939470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3933939470
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1647304857
Short name T753
Test name
Test status
Simulation time 182321448 ps
CPU time 10.17 seconds
Started Jul 12 05:58:45 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 244840 kb
Host smart-6960d5a6-fa3e-4177-a75f-6887a5b13ac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1647304857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1647304857
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2112091065
Short name T121
Test name
Test status
Simulation time 3904891358 ps
CPU time 283.02 seconds
Started Jul 12 05:58:43 PM PDT 24
Finished Jul 12 06:03:52 PM PDT 24
Peak memory 272372 kb
Host smart-7f1bf57b-8a1a-4592-b5e7-cec37fb9aa5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2112091065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2112091065
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1643743161
Short name T147
Test name
Test status
Simulation time 31671260347 ps
CPU time 612.17 seconds
Started Jul 12 05:58:46 PM PDT 24
Finished Jul 12 06:09:23 PM PDT 24
Peak memory 268756 kb
Host smart-1d2a2a83-d266-4460-b870-b4bc7583eeb7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643743161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1643743161
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3415746881
Short name T761
Test name
Test status
Simulation time 38591366 ps
CPU time 5.74 seconds
Started Jul 12 05:58:44 PM PDT 24
Finished Jul 12 05:59:15 PM PDT 24
Peak memory 253744 kb
Host smart-d3e42ef6-a9b9-4f80-9092-d79b4806648f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3415746881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3415746881
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1131152326
Short name T730
Test name
Test status
Simulation time 35063185 ps
CPU time 3.14 seconds
Started Jul 12 05:58:46 PM PDT 24
Finished Jul 12 05:59:14 PM PDT 24
Peak memory 237732 kb
Host smart-6b0bbc5a-c5ac-4c3a-a530-35b513929e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1131152326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1131152326
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.408255263
Short name T771
Test name
Test status
Simulation time 132449503 ps
CPU time 9.42 seconds
Started Jul 12 05:58:49 PM PDT 24
Finished Jul 12 05:59:24 PM PDT 24
Peak memory 240568 kb
Host smart-8826eeba-f502-4b87-a1f1-ffd6f03c6fd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408255263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.408255263
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2567327370
Short name T740
Test name
Test status
Simulation time 85291352 ps
CPU time 6.11 seconds
Started Jul 12 05:58:51 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 237532 kb
Host smart-12a3ee49-9c00-46b3-b1dd-dd10c193b35f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2567327370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2567327370
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3494524490
Short name T333
Test name
Test status
Simulation time 8135350 ps
CPU time 1.54 seconds
Started Jul 12 05:58:51 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 235604 kb
Host smart-e0291a8c-78f6-4137-8be0-20674c32e516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3494524490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3494524490
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1940914538
Short name T766
Test name
Test status
Simulation time 2579412362 ps
CPU time 22 seconds
Started Jul 12 05:58:52 PM PDT 24
Finished Jul 12 05:59:39 PM PDT 24
Peak memory 245812 kb
Host smart-66a68b52-3fd3-4203-9934-d4f273737b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1940914538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1940914538
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3097854712
Short name T792
Test name
Test status
Simulation time 128913285 ps
CPU time 13.85 seconds
Started Jul 12 05:58:48 PM PDT 24
Finished Jul 12 05:59:27 PM PDT 24
Peak memory 248076 kb
Host smart-6b308595-3704-4b8e-83fd-bbe04b5a59c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3097854712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3097854712
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4076553953
Short name T713
Test name
Test status
Simulation time 85982526 ps
CPU time 2.15 seconds
Started Jul 12 05:58:51 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 237536 kb
Host smart-997ba29d-5c2f-47a6-8bdc-390e7bf315ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4076553953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4076553953
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2520693377
Short name T46
Test name
Test status
Simulation time 37528747057 ps
CPU time 1066.97 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 05:02:55 PM PDT 24
Peak memory 273388 kb
Host smart-df757571-17d7-42f6-ad81-d178e4b40e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520693377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2520693377
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1757664433
Short name T518
Test name
Test status
Simulation time 167975065 ps
CPU time 10.38 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 04:45:18 PM PDT 24
Peak memory 249280 kb
Host smart-32a14089-bb18-4a42-a6f0-8c636d82ccbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1757664433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1757664433
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3316541391
Short name T642
Test name
Test status
Simulation time 4143639338 ps
CPU time 114.38 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 04:47:02 PM PDT 24
Peak memory 250368 kb
Host smart-3ed5181f-2829-42a2-9765-d5275531cb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
41391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3316541391
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2770654003
Short name T493
Test name
Test status
Simulation time 375946755 ps
CPU time 15.87 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 04:45:23 PM PDT 24
Peak memory 249300 kb
Host smart-1e7a6cbc-126d-4466-8efd-3ef3d51469fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
54003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2770654003
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3304775175
Short name T325
Test name
Test status
Simulation time 86126448523 ps
CPU time 1364 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 05:07:50 PM PDT 24
Peak memory 273488 kb
Host smart-dc55626d-cd95-4228-a8b0-a67c8ace3386
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304775175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3304775175
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2158965417
Short name T624
Test name
Test status
Simulation time 8250222256 ps
CPU time 879.62 seconds
Started Jul 12 04:45:05 PM PDT 24
Finished Jul 12 04:59:48 PM PDT 24
Peak memory 266760 kb
Host smart-4a8bea87-2541-4d16-b68f-a9974e6c964f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158965417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2158965417
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3010583405
Short name T311
Test name
Test status
Simulation time 10276664055 ps
CPU time 230.39 seconds
Started Jul 12 04:45:06 PM PDT 24
Finished Jul 12 04:48:59 PM PDT 24
Peak memory 256200 kb
Host smart-297dd90c-8c75-4785-a781-64caa5abd84e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010583405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3010583405
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.68035785
Short name T547
Test name
Test status
Simulation time 1868140542 ps
CPU time 22.24 seconds
Started Jul 12 04:45:06 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 249164 kb
Host smart-830777ff-1d20-41b4-96d3-21b5edc7d80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68035
785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.68035785
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.818386848
Short name T597
Test name
Test status
Simulation time 210205759 ps
CPU time 15.15 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:23 PM PDT 24
Peak memory 248704 kb
Host smart-4383f933-436d-4716-bc3f-04fdf73473f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81838
6848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.818386848
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1427965582
Short name T679
Test name
Test status
Simulation time 614167122 ps
CPU time 21.62 seconds
Started Jul 12 04:45:06 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 257452 kb
Host smart-4492c1a6-c996-4da7-b585-05055915f3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14279
65582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1427965582
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1773024180
Short name T344
Test name
Test status
Simulation time 128035644 ps
CPU time 16.53 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:23 PM PDT 24
Peak memory 257268 kb
Host smart-294a5c15-aa3a-42c2-9df3-ce6d55e33ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17730
24180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1773024180
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3351059671
Short name T76
Test name
Test status
Simulation time 700921229 ps
CPU time 21.96 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:26 PM PDT 24
Peak memory 257336 kb
Host smart-0e1e1277-4b72-4e18-b68e-fe498e497fe2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351059671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3351059671
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2516623364
Short name T228
Test name
Test status
Simulation time 27330607581 ps
CPU time 2814.16 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 298564 kb
Host smart-deb891ad-36a5-430b-8205-26bd2fec4dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516623364 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2516623364
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3922821481
Short name T505
Test name
Test status
Simulation time 27058460608 ps
CPU time 1741.84 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 05:14:10 PM PDT 24
Peak memory 273864 kb
Host smart-6702f528-f529-4328-8029-628f6970cc36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922821481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3922821481
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.427662528
Short name T371
Test name
Test status
Simulation time 1309636366 ps
CPU time 54.53 seconds
Started Jul 12 04:45:09 PM PDT 24
Finished Jul 12 04:46:05 PM PDT 24
Peak memory 249168 kb
Host smart-9977f784-ee9b-47ed-ba84-4a5382eb4590
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427662528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.427662528
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3406397552
Short name T695
Test name
Test status
Simulation time 8225487519 ps
CPU time 148.33 seconds
Started Jul 12 04:45:05 PM PDT 24
Finished Jul 12 04:47:36 PM PDT 24
Peak memory 256892 kb
Host smart-02c2e39b-4325-43f5-bb5c-5124b88b428b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
97552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3406397552
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.780953664
Short name T71
Test name
Test status
Simulation time 162774185 ps
CPU time 3.96 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 249252 kb
Host smart-62fba433-89fe-4a5d-8381-b95f8a648770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78095
3664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.780953664
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3955380569
Short name T64
Test name
Test status
Simulation time 45952438319 ps
CPU time 2566.37 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 282156 kb
Host smart-8a878f6a-c0a4-4514-8e23-27f75b0021e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955380569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3955380569
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1862126311
Short name T379
Test name
Test status
Simulation time 984965970 ps
CPU time 15.83 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:45:22 PM PDT 24
Peak memory 249288 kb
Host smart-2255e900-9121-449e-b406-93f60e1ff08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18621
26311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1862126311
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.458626103
Short name T369
Test name
Test status
Simulation time 70362604 ps
CPU time 5.21 seconds
Started Jul 12 04:45:17 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 240420 kb
Host smart-3090863a-d6e3-4442-9a53-50b9f77551da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45862
6103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.458626103
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3357797004
Short name T32
Test name
Test status
Simulation time 708399115 ps
CPU time 12.11 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:19 PM PDT 24
Peak memory 270520 kb
Host smart-e3f334c1-a2bd-4652-a278-b3bad05d489e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3357797004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3357797004
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.927254904
Short name T242
Test name
Test status
Simulation time 368189212 ps
CPU time 19.57 seconds
Started Jul 12 04:45:05 PM PDT 24
Finished Jul 12 04:45:28 PM PDT 24
Peak memory 248496 kb
Host smart-90aae95a-3428-4dd6-ae14-6ab5c63ecd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92725
4904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.927254904
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3169722563
Short name T538
Test name
Test status
Simulation time 4631700998 ps
CPU time 44.36 seconds
Started Jul 12 04:45:05 PM PDT 24
Finished Jul 12 04:45:52 PM PDT 24
Peak memory 257488 kb
Host smart-c2c6df55-ec0c-4541-b3f0-9aac5d3fe261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
22563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3169722563
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3279803132
Short name T56
Test name
Test status
Simulation time 28731822974 ps
CPU time 1984.43 seconds
Started Jul 12 04:45:07 PM PDT 24
Finished Jul 12 05:18:14 PM PDT 24
Peak memory 289724 kb
Host smart-b97d7895-7ce4-4173-bb15-0b8daae647fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279803132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3279803132
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4064960265
Short name T542
Test name
Test status
Simulation time 78273487138 ps
CPU time 2648.99 seconds
Started Jul 12 04:45:36 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 289928 kb
Host smart-5fd5a76b-323c-433d-b36d-70431d6f8f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064960265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4064960265
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1840052954
Short name T591
Test name
Test status
Simulation time 207934105 ps
CPU time 10.93 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:45:45 PM PDT 24
Peak memory 249268 kb
Host smart-01655e17-9e0e-4f28-a684-8fdd0145b96e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1840052954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1840052954
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2804572065
Short name T584
Test name
Test status
Simulation time 1522561779 ps
CPU time 121.3 seconds
Started Jul 12 04:45:22 PM PDT 24
Finished Jul 12 04:47:24 PM PDT 24
Peak memory 257448 kb
Host smart-a6b7f3e3-c813-4e33-810e-45ed89d2d27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045
72065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2804572065
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2020478116
Short name T194
Test name
Test status
Simulation time 470015434 ps
CPU time 27.44 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 04:45:54 PM PDT 24
Peak memory 249220 kb
Host smart-de9a2bb2-ee3d-4f17-b5ec-6fbc8c61722c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20204
78116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2020478116
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.617142010
Short name T697
Test name
Test status
Simulation time 24296693713 ps
CPU time 1445.32 seconds
Started Jul 12 04:45:28 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 273680 kb
Host smart-4f7f132b-1d18-4292-9133-041b5fd1496e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617142010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.617142010
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1204074614
Short name T432
Test name
Test status
Simulation time 19580713473 ps
CPU time 195.18 seconds
Started Jul 12 04:45:26 PM PDT 24
Finished Jul 12 04:48:43 PM PDT 24
Peak memory 249388 kb
Host smart-f5c762fd-1c48-415a-b0cf-c1cd6e23319f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204074614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1204074614
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3793261561
Short name T574
Test name
Test status
Simulation time 246015722 ps
CPU time 25.63 seconds
Started Jul 12 04:45:35 PM PDT 24
Finished Jul 12 04:46:03 PM PDT 24
Peak memory 249296 kb
Host smart-8011f1b3-b7ab-4a9e-838e-16c8c1bc2c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932
61561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3793261561
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1075869872
Short name T660
Test name
Test status
Simulation time 4377232090 ps
CPU time 61.14 seconds
Started Jul 12 04:45:20 PM PDT 24
Finished Jul 12 04:46:22 PM PDT 24
Peak memory 249140 kb
Host smart-c74c7c02-669d-4b50-855e-cc22be50b392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10758
69872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1075869872
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2610272674
Short name T270
Test name
Test status
Simulation time 165733113 ps
CPU time 18.59 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:45:47 PM PDT 24
Peak memory 256592 kb
Host smart-634d70b3-5063-4284-be9e-0ac8dea4a7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
72674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2610272674
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1981287715
Short name T358
Test name
Test status
Simulation time 1026969213 ps
CPU time 21.4 seconds
Started Jul 12 04:45:25 PM PDT 24
Finished Jul 12 04:45:48 PM PDT 24
Peak memory 256416 kb
Host smart-e27926ec-6126-4bf1-92e9-e8990f1d350d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812
87715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1981287715
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2687194344
Short name T54
Test name
Test status
Simulation time 65007864784 ps
CPU time 3369.83 seconds
Started Jul 12 04:45:36 PM PDT 24
Finished Jul 12 05:41:48 PM PDT 24
Peak memory 290324 kb
Host smart-953fddf4-0e8e-483c-8ef6-c28e470127b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687194344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2687194344
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2716346142
Short name T251
Test name
Test status
Simulation time 33840592130 ps
CPU time 3253.17 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 306672 kb
Host smart-06617431-92df-4de6-b702-ab4bbde17ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716346142 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2716346142
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1942405073
Short name T215
Test name
Test status
Simulation time 13491579 ps
CPU time 2.25 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 249592 kb
Host smart-3495834a-fb42-4bde-b52c-2d8c85b56b5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1942405073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1942405073
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.690246290
Short name T480
Test name
Test status
Simulation time 29456783377 ps
CPU time 1969.95 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 05:18:25 PM PDT 24
Peak memory 290320 kb
Host smart-22c46e06-6c82-4ba4-b442-0c5dab35b208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690246290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.690246290
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1427174755
Short name T568
Test name
Test status
Simulation time 1172378722 ps
CPU time 15.43 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:45:50 PM PDT 24
Peak memory 249188 kb
Host smart-2d564dcf-7490-45a2-9eeb-8798d07c5a90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1427174755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1427174755
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3855377705
Short name T637
Test name
Test status
Simulation time 8477369765 ps
CPU time 166.06 seconds
Started Jul 12 04:45:22 PM PDT 24
Finished Jul 12 04:48:09 PM PDT 24
Peak memory 252424 kb
Host smart-3cd63158-4745-4edd-a9dd-57555ee104ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
77705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3855377705
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1246038900
Short name T367
Test name
Test status
Simulation time 1705667885 ps
CPU time 41.27 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:46:17 PM PDT 24
Peak memory 249176 kb
Host smart-dc86bdaf-c648-484d-b9d4-b1dc9ec7a8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12460
38900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1246038900
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2103147124
Short name T636
Test name
Test status
Simulation time 84192086705 ps
CPU time 1377.89 seconds
Started Jul 12 04:45:23 PM PDT 24
Finished Jul 12 05:08:21 PM PDT 24
Peak memory 289976 kb
Host smart-3ea139e2-b83a-4eba-a9ce-7b8568704215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103147124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2103147124
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1543098677
Short name T289
Test name
Test status
Simulation time 40539976903 ps
CPU time 269.88 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 04:50:07 PM PDT 24
Peak memory 249240 kb
Host smart-2f5315e4-ea5e-4aee-bd13-d34212fce247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543098677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1543098677
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.813374542
Short name T685
Test name
Test status
Simulation time 784488684 ps
CPU time 47.17 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 04:46:13 PM PDT 24
Peak memory 256496 kb
Host smart-29d7e55e-17eb-4d65-84f0-3052a0fb1ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81337
4542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.813374542
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2677000076
Short name T40
Test name
Test status
Simulation time 983739242 ps
CPU time 19.58 seconds
Started Jul 12 04:45:21 PM PDT 24
Finished Jul 12 04:45:41 PM PDT 24
Peak memory 249268 kb
Host smart-bb9747bf-77e6-4e77-ae63-3bc35124409f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26770
00076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2677000076
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3967908621
Short name T514
Test name
Test status
Simulation time 1212183754 ps
CPU time 40.5 seconds
Started Jul 12 04:45:35 PM PDT 24
Finished Jul 12 04:46:18 PM PDT 24
Peak memory 249296 kb
Host smart-88ff41a3-b1cb-449b-b8fb-576133c0c16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
08621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3967908621
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1776712682
Short name T468
Test name
Test status
Simulation time 392671102 ps
CPU time 24.85 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 04:45:59 PM PDT 24
Peak memory 257036 kb
Host smart-fc2953a3-e2e6-4b22-a1d1-87a2cf95727c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17767
12682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1776712682
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1580010692
Short name T172
Test name
Test status
Simulation time 128938625887 ps
CPU time 4373.08 seconds
Started Jul 12 04:45:21 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 298660 kb
Host smart-75550ffe-5bf8-4823-9889-f10de921eada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580010692 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1580010692
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1665887341
Short name T208
Test name
Test status
Simulation time 33288288 ps
CPU time 3.24 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 04:45:38 PM PDT 24
Peak memory 249568 kb
Host smart-afd40098-7890-4d54-92bb-1d4737b09b04
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1665887341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1665887341
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.396502666
Short name T88
Test name
Test status
Simulation time 200916375947 ps
CPU time 3110.89 seconds
Started Jul 12 04:45:39 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 289996 kb
Host smart-7dda8ed1-3109-4d4d-be91-3ca5b5fdb87f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396502666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.396502666
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4216509740
Short name T522
Test name
Test status
Simulation time 1016447215 ps
CPU time 19.22 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:45:52 PM PDT 24
Peak memory 249176 kb
Host smart-5686d522-9cfa-45ec-bf5f-6fd988deee1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4216509740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4216509740
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2995156168
Short name T230
Test name
Test status
Simulation time 10763270948 ps
CPU time 141.72 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:47:56 PM PDT 24
Peak memory 257404 kb
Host smart-c634cf5b-a6bb-4707-be34-1430041bfe34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
56168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2995156168
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3233106365
Short name T579
Test name
Test status
Simulation time 448279032 ps
CPU time 27.91 seconds
Started Jul 12 04:45:20 PM PDT 24
Finished Jul 12 04:45:49 PM PDT 24
Peak memory 256488 kb
Host smart-4fb91b5d-08de-4fd6-b7be-1055067aeee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
06365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3233106365
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.560316805
Short name T15
Test name
Test status
Simulation time 24858447615 ps
CPU time 1294.62 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 05:07:06 PM PDT 24
Peak memory 289612 kb
Host smart-3425e7c5-5281-48cf-b4b8-6648d8168179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560316805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.560316805
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.4278526644
Short name T457
Test name
Test status
Simulation time 10472287254 ps
CPU time 1172.81 seconds
Started Jul 12 04:45:36 PM PDT 24
Finished Jul 12 05:05:11 PM PDT 24
Peak memory 286092 kb
Host smart-33c5b9e9-3891-418b-b4d4-a24d832a1810
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278526644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4278526644
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2376862710
Short name T313
Test name
Test status
Simulation time 31396600509 ps
CPU time 326.87 seconds
Started Jul 12 04:45:23 PM PDT 24
Finished Jul 12 04:50:51 PM PDT 24
Peak memory 249344 kb
Host smart-c09306b4-863b-4af4-b353-7ef3001187d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376862710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2376862710
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2194340615
Short name T446
Test name
Test status
Simulation time 962547271 ps
CPU time 23.63 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 04:45:48 PM PDT 24
Peak memory 256640 kb
Host smart-6f784843-b6a3-4ff9-84f6-45b76c7d6956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943
40615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2194340615
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.681720705
Short name T439
Test name
Test status
Simulation time 645680139 ps
CPU time 35.33 seconds
Started Jul 12 04:45:23 PM PDT 24
Finished Jul 12 04:46:00 PM PDT 24
Peak memory 248740 kb
Host smart-5ef70c01-f5ea-4ad7-aead-9646df0ff255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68172
0705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.681720705
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.330792306
Short name T107
Test name
Test status
Simulation time 401734870 ps
CPU time 25.33 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 04:45:58 PM PDT 24
Peak memory 257364 kb
Host smart-b1b14f29-36c4-4b00-94de-b454c607f1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33079
2306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.330792306
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3696178489
Short name T532
Test name
Test status
Simulation time 1371263575 ps
CPU time 15.77 seconds
Started Jul 12 04:45:23 PM PDT 24
Finished Jul 12 04:45:40 PM PDT 24
Peak memory 249596 kb
Host smart-d89f6bf7-5221-4c8e-8aaa-7f25c9de2642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
78489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3696178489
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2855736608
Short name T684
Test name
Test status
Simulation time 135985655718 ps
CPU time 2487.6 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 05:27:05 PM PDT 24
Peak memory 289772 kb
Host smart-195dab02-008b-4bd7-827f-2e61d9fab635
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855736608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2855736608
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3300576742
Short name T49
Test name
Test status
Simulation time 90386959086 ps
CPU time 1471.35 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 05:10:09 PM PDT 24
Peak memory 289556 kb
Host smart-cf059f8e-2fce-4f40-a79f-7bdf6a225d8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300576742 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3300576742
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3120329785
Short name T583
Test name
Test status
Simulation time 934658949 ps
CPU time 12.44 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 04:45:55 PM PDT 24
Peak memory 249232 kb
Host smart-2a7a43b2-a066-4fc1-9e74-2b43ef7a8696
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3120329785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3120329785
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3852829378
Short name T569
Test name
Test status
Simulation time 7636766350 ps
CPU time 43.85 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:46:19 PM PDT 24
Peak memory 257456 kb
Host smart-ed7ef515-b3ae-40cf-be91-6808c61645d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38528
29378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3852829378
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.344736029
Short name T504
Test name
Test status
Simulation time 102251799 ps
CPU time 12.14 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:45:46 PM PDT 24
Peak memory 248796 kb
Host smart-3775a1b6-9f0e-45ce-9ece-19fd8e52b11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34473
6029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.344736029
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3596439129
Short name T330
Test name
Test status
Simulation time 70720382376 ps
CPU time 2029.71 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 05:19:24 PM PDT 24
Peak memory 282108 kb
Host smart-c8b59a24-6f5d-410e-aad9-47e0ebb9c715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596439129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3596439129
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2171600096
Short name T52
Test name
Test status
Simulation time 3127210540 ps
CPU time 36.73 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:46:09 PM PDT 24
Peak memory 249528 kb
Host smart-56d98d1d-b14f-47d3-badc-26b2aca94e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21716
00096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2171600096
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2379812801
Short name T426
Test name
Test status
Simulation time 710745813 ps
CPU time 40.74 seconds
Started Jul 12 04:45:33 PM PDT 24
Finished Jul 12 04:46:17 PM PDT 24
Peak memory 256180 kb
Host smart-52a2cc79-5ddf-42ac-8fb1-cc9d090ade50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23798
12801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2379812801
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1128105503
Short name T528
Test name
Test status
Simulation time 200109280 ps
CPU time 16.45 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 04:45:48 PM PDT 24
Peak memory 255984 kb
Host smart-13499e6f-e62d-4998-bdc2-909997ffad7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11281
05503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1128105503
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1085057812
Short name T108
Test name
Test status
Simulation time 65136627899 ps
CPU time 1547.42 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 05:11:29 PM PDT 24
Peak memory 290132 kb
Host smart-f040dd29-e708-42d8-9af1-84f4d443dd8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085057812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1085057812
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1007351461
Short name T209
Test name
Test status
Simulation time 42941423 ps
CPU time 4.06 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 04:45:46 PM PDT 24
Peak memory 249568 kb
Host smart-af509526-5748-4814-86b4-d5752b2070d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1007351461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1007351461
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.616996489
Short name T377
Test name
Test status
Simulation time 57728137176 ps
CPU time 3281.36 seconds
Started Jul 12 04:45:28 PM PDT 24
Finished Jul 12 05:40:12 PM PDT 24
Peak memory 290260 kb
Host smart-6c21901b-aa6b-47a5-8791-78d2b8047d8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616996489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.616996489
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2351973083
Short name T683
Test name
Test status
Simulation time 323022229 ps
CPU time 5.68 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:45:53 PM PDT 24
Peak memory 249268 kb
Host smart-b544c068-873b-46d0-b1d4-f28d2406030d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2351973083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2351973083
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.865960609
Short name T14
Test name
Test status
Simulation time 4425605358 ps
CPU time 237.18 seconds
Started Jul 12 04:45:33 PM PDT 24
Finished Jul 12 04:49:34 PM PDT 24
Peak memory 257456 kb
Host smart-27e438a2-31a4-4e66-88f0-062f72c0b4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86596
0609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.865960609
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.507408596
Short name T632
Test name
Test status
Simulation time 38284297 ps
CPU time 2.85 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 04:45:35 PM PDT 24
Peak memory 240576 kb
Host smart-3fd70217-1a4f-4d6f-b2e7-847ed7376890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50740
8596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.507408596
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4164319222
Short name T470
Test name
Test status
Simulation time 200407116888 ps
CPU time 1364.58 seconds
Started Jul 12 04:45:38 PM PDT 24
Finished Jul 12 05:08:24 PM PDT 24
Peak memory 265744 kb
Host smart-35f306c1-700b-4bc5-9a23-0e51d4599727
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164319222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4164319222
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3192845763
Short name T100
Test name
Test status
Simulation time 13582297305 ps
CPU time 274.84 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:50:08 PM PDT 24
Peak memory 256092 kb
Host smart-2508aa69-3d8a-4a70-913c-35bf7d484db0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192845763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3192845763
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1754472904
Short name T671
Test name
Test status
Simulation time 328150273 ps
CPU time 9.61 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:45:45 PM PDT 24
Peak memory 253804 kb
Host smart-2782ed78-0814-4ef4-95fb-a805e770eb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
72904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1754472904
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1209539158
Short name T386
Test name
Test status
Simulation time 1431834523 ps
CPU time 32.44 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 04:46:09 PM PDT 24
Peak memory 249240 kb
Host smart-ff818ce9-cfe6-4a08-a5db-b49c6561e671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12095
39158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1209539158
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1200932868
Short name T605
Test name
Test status
Simulation time 358213562 ps
CPU time 12.1 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:45:56 PM PDT 24
Peak memory 248792 kb
Host smart-b16c6845-7d21-4061-853e-5f9528b0d5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12009
32868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1200932868
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2733929107
Short name T521
Test name
Test status
Simulation time 195974349 ps
CPU time 12.59 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 04:45:46 PM PDT 24
Peak memory 249208 kb
Host smart-8c7ca77c-4266-465c-9a75-084cf587c75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27339
29107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2733929107
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2192527802
Short name T243
Test name
Test status
Simulation time 193903039487 ps
CPU time 2824.96 seconds
Started Jul 12 04:45:28 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 290160 kb
Host smart-6aab9916-d377-4e18-9b3c-5afd854c18a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192527802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2192527802
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.152837814
Short name T250
Test name
Test status
Simulation time 64303752701 ps
CPU time 6887.31 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 371584 kb
Host smart-a9eccd77-daff-446e-8557-8395f6c0bb60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152837814 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.152837814
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2382389643
Short name T202
Test name
Test status
Simulation time 47968462 ps
CPU time 3.81 seconds
Started Jul 12 04:45:35 PM PDT 24
Finished Jul 12 04:45:42 PM PDT 24
Peak memory 249440 kb
Host smart-6311ea22-80a1-477c-9fd2-86c98b59ed03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2382389643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2382389643
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.276492746
Short name T50
Test name
Test status
Simulation time 10121449549 ps
CPU time 1073.93 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 05:03:26 PM PDT 24
Peak memory 282904 kb
Host smart-3cce1ede-24a9-40f8-b38b-0c01976558a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276492746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.276492746
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.802591298
Short name T221
Test name
Test status
Simulation time 160884662 ps
CPU time 9.2 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 04:46:02 PM PDT 24
Peak memory 249132 kb
Host smart-f7a97dd9-6d22-44fb-96f4-b93d9e7340a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=802591298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.802591298
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2150457643
Short name T557
Test name
Test status
Simulation time 1915141215 ps
CPU time 72.63 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:46:46 PM PDT 24
Peak memory 250196 kb
Host smart-93aece3a-701e-4c42-86f6-25d3926877a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504
57643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2150457643
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3650969540
Short name T456
Test name
Test status
Simulation time 2527403273 ps
CPU time 39.49 seconds
Started Jul 12 04:45:48 PM PDT 24
Finished Jul 12 04:46:28 PM PDT 24
Peak memory 249176 kb
Host smart-23a3cc52-bcaf-49c6-8979-eacc58a92c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
69540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3650969540
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1984685278
Short name T327
Test name
Test status
Simulation time 51097169156 ps
CPU time 2832.37 seconds
Started Jul 12 04:45:40 PM PDT 24
Finished Jul 12 05:32:53 PM PDT 24
Peak memory 285660 kb
Host smart-8c4c0234-3e5b-4121-9fc5-d550a160d66b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984685278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1984685278
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3345007755
Short name T594
Test name
Test status
Simulation time 33329608026 ps
CPU time 1334.07 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 05:07:46 PM PDT 24
Peak memory 289644 kb
Host smart-40d4f87d-7a0c-498b-8f6e-9736e0374229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345007755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3345007755
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.7646365
Short name T607
Test name
Test status
Simulation time 360752781 ps
CPU time 11.73 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:45:44 PM PDT 24
Peak memory 249264 kb
Host smart-2543f88c-196a-4782-9fa6-a2c96e3f482b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76463
65 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.7646365
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.4248330907
Short name T492
Test name
Test status
Simulation time 133564826 ps
CPU time 13.43 seconds
Started Jul 12 04:45:30 PM PDT 24
Finished Jul 12 04:45:46 PM PDT 24
Peak memory 248484 kb
Host smart-89915a2f-beb5-4db9-98ae-28454d3d2a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42483
30907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.4248330907
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3176477886
Short name T625
Test name
Test status
Simulation time 378346487 ps
CPU time 8.36 seconds
Started Jul 12 04:45:42 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 253408 kb
Host smart-7ff3cac5-2ea9-4b74-878e-37e199006d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
77886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3176477886
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2559533004
Short name T475
Test name
Test status
Simulation time 2082703256 ps
CPU time 58.03 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:46:34 PM PDT 24
Peak memory 257260 kb
Host smart-ade3ff17-8263-46b7-be38-04d0c7c8f51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25595
33004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2559533004
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3496696256
Short name T179
Test name
Test status
Simulation time 2443487802 ps
CPU time 118.15 seconds
Started Jul 12 04:45:39 PM PDT 24
Finished Jul 12 04:47:38 PM PDT 24
Peak memory 252648 kb
Host smart-9d4ce95a-1145-4dbd-9e79-c556f4ad62b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496696256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3496696256
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.380293452
Short name T692
Test name
Test status
Simulation time 1466160670544 ps
CPU time 6081.44 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 06:27:20 PM PDT 24
Peak memory 322772 kb
Host smart-2cc69cce-c2ad-439c-8644-4935f7149f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380293452 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.380293452
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2348172132
Short name T206
Test name
Test status
Simulation time 63164578 ps
CPU time 3.35 seconds
Started Jul 12 04:45:37 PM PDT 24
Finished Jul 12 04:45:42 PM PDT 24
Peak memory 249484 kb
Host smart-27d06428-8825-469c-b368-bfb3dfdfe7ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2348172132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2348172132
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3728214329
Short name T97
Test name
Test status
Simulation time 15343833833 ps
CPU time 1452.44 seconds
Started Jul 12 04:45:33 PM PDT 24
Finished Jul 12 05:09:49 PM PDT 24
Peak memory 290248 kb
Host smart-a97cb88c-b47d-46b0-bad9-712524ff0937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728214329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3728214329
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2479850596
Short name T567
Test name
Test status
Simulation time 139032299 ps
CPU time 7.98 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:02 PM PDT 24
Peak memory 249260 kb
Host smart-8d81458d-c282-4a0f-9bdf-dc2d49a67c1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2479850596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2479850596
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.721271320
Short name T566
Test name
Test status
Simulation time 51117811572 ps
CPU time 171.59 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 04:49:49 PM PDT 24
Peak memory 257084 kb
Host smart-6087afcf-f86a-4854-8618-1503a4d36692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72127
1320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.721271320
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1938418289
Short name T663
Test name
Test status
Simulation time 4246083225 ps
CPU time 61.31 seconds
Started Jul 12 04:46:44 PM PDT 24
Finished Jul 12 04:47:47 PM PDT 24
Peak memory 247572 kb
Host smart-080ae177-b50b-4001-bde9-b28d3873a9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19384
18289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1938418289
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.386426165
Short name T477
Test name
Test status
Simulation time 82995429159 ps
CPU time 1036.88 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 05:02:59 PM PDT 24
Peak memory 273300 kb
Host smart-8912c546-63ee-46ba-8578-84a32d75d9d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386426165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.386426165
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.484772899
Short name T361
Test name
Test status
Simulation time 44657395147 ps
CPU time 1464.6 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 05:10:07 PM PDT 24
Peak memory 290152 kb
Host smart-10ad6158-c83f-493f-9201-198294e57f10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484772899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.484772899
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3350153600
Short name T293
Test name
Test status
Simulation time 4427574924 ps
CPU time 179.08 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 04:48:37 PM PDT 24
Peak memory 249344 kb
Host smart-aad4f8cc-9485-49db-8c83-3d49b35b2557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350153600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3350153600
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1448037992
Short name T535
Test name
Test status
Simulation time 397663821 ps
CPU time 23.27 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:46:10 PM PDT 24
Peak memory 257344 kb
Host smart-f6d738f2-3dac-4242-a1db-91bfde0cf6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14480
37992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1448037992
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1262105999
Short name T441
Test name
Test status
Simulation time 222931320 ps
CPU time 12.51 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 04:46:11 PM PDT 24
Peak memory 248800 kb
Host smart-2de8e415-93a9-436a-9bc4-8f8b6976c7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
05999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1262105999
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4082663757
Short name T559
Test name
Test status
Simulation time 368693794 ps
CPU time 19.78 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:46:04 PM PDT 24
Peak memory 256900 kb
Host smart-d5798ccc-8676-4af7-9243-5768bfe5d22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40826
63757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4082663757
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2926186859
Short name T609
Test name
Test status
Simulation time 817533394 ps
CPU time 13 seconds
Started Jul 12 04:46:44 PM PDT 24
Finished Jul 12 04:46:58 PM PDT 24
Peak memory 254324 kb
Host smart-ee43da70-ac25-47b8-b53b-0f7888ef8f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29261
86859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2926186859
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2251983827
Short name T600
Test name
Test status
Simulation time 1289934636 ps
CPU time 70.56 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 04:48:08 PM PDT 24
Peak memory 256968 kb
Host smart-2cac68fa-c27d-474d-80f6-71f06dfc2b99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251983827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2251983827
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1378550051
Short name T479
Test name
Test status
Simulation time 145405184833 ps
CPU time 3276.25 seconds
Started Jul 12 04:45:56 PM PDT 24
Finished Jul 12 05:40:34 PM PDT 24
Peak memory 331472 kb
Host smart-04da2f42-4bfa-4b82-b637-2ab29f1e1693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378550051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1378550051
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1242618006
Short name T41
Test name
Test status
Simulation time 48401353 ps
CPU time 4.34 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 04:45:50 PM PDT 24
Peak memory 249476 kb
Host smart-8e34e9c6-ffc4-447f-b090-fb7f2e5e34a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1242618006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1242618006
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3904709857
Short name T404
Test name
Test status
Simulation time 56457034403 ps
CPU time 1176.88 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 05:05:14 PM PDT 24
Peak memory 289524 kb
Host smart-a0ce74f6-01f4-42e1-ae4d-36d64c9916a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904709857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3904709857
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2442212090
Short name T472
Test name
Test status
Simulation time 1088504211 ps
CPU time 46.04 seconds
Started Jul 12 04:45:49 PM PDT 24
Finished Jul 12 04:46:36 PM PDT 24
Peak memory 249432 kb
Host smart-bce1b3f8-0098-44a5-b37d-344579a4952e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2442212090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2442212090
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.545594904
Short name T393
Test name
Test status
Simulation time 3894733011 ps
CPU time 241.15 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 04:49:38 PM PDT 24
Peak memory 257476 kb
Host smart-fe92abbe-1b04-469a-84f0-ac16aa1fb853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54559
4904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.545594904
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1347005599
Short name T409
Test name
Test status
Simulation time 1573157910 ps
CPU time 22.88 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 04:47:21 PM PDT 24
Peak memory 248376 kb
Host smart-2e3c0852-4dda-4d20-8760-7583450f48e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
05599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1347005599
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1132761756
Short name T483
Test name
Test status
Simulation time 16156369385 ps
CPU time 1542.52 seconds
Started Jul 12 04:45:35 PM PDT 24
Finished Jul 12 05:11:21 PM PDT 24
Peak memory 290112 kb
Host smart-3c6ed268-4e69-4f8b-9510-4efd50089969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132761756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1132761756
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2815724477
Short name T394
Test name
Test status
Simulation time 202992183981 ps
CPU time 2825.59 seconds
Started Jul 12 04:45:35 PM PDT 24
Finished Jul 12 05:32:44 PM PDT 24
Peak memory 282156 kb
Host smart-1be18a22-5bc0-4918-a2ba-b4a5583b6fa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815724477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2815724477
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.904677670
Short name T509
Test name
Test status
Simulation time 1311395422 ps
CPU time 69.91 seconds
Started Jul 12 04:45:33 PM PDT 24
Finished Jul 12 04:46:47 PM PDT 24
Peak memory 249284 kb
Host smart-01aee79b-78d9-4bff-89c8-f4c8ab635536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90467
7670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.904677670
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.245353601
Short name T709
Test name
Test status
Simulation time 1529310355 ps
CPU time 48.59 seconds
Started Jul 12 04:45:35 PM PDT 24
Finished Jul 12 04:46:26 PM PDT 24
Peak memory 248796 kb
Host smart-bae8861c-44ae-437c-883f-61c9e5275f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24535
3601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.245353601
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.178467105
Short name T232
Test name
Test status
Simulation time 1471626990 ps
CPU time 33.22 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:46:17 PM PDT 24
Peak memory 249120 kb
Host smart-0336fffa-66c3-4f76-882d-1f7ac9138074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17846
7105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.178467105
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3245392560
Short name T37
Test name
Test status
Simulation time 144845562 ps
CPU time 14.16 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 04:45:52 PM PDT 24
Peak memory 256104 kb
Host smart-aad229af-d2c0-4395-9911-a4e6dd15e626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32453
92560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3245392560
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.851253211
Short name T411
Test name
Test status
Simulation time 53903978371 ps
CPU time 3119.77 seconds
Started Jul 12 04:45:34 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 298448 kb
Host smart-575dafed-9c81-4f91-9b0d-ecbe2310f256
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851253211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.851253211
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2398064652
Short name T418
Test name
Test status
Simulation time 165112913987 ps
CPU time 4361.9 seconds
Started Jul 12 04:45:40 PM PDT 24
Finished Jul 12 05:58:24 PM PDT 24
Peak memory 347812 kb
Host smart-5e0ed57b-0590-423f-9d3b-3dac1b7f5105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398064652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2398064652
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.226240442
Short name T34
Test name
Test status
Simulation time 103673760 ps
CPU time 4.04 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:45:48 PM PDT 24
Peak memory 249500 kb
Host smart-8650729c-a2d1-45e8-a6a4-186a2e030186
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=226240442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.226240442
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1578951936
Short name T519
Test name
Test status
Simulation time 21387210797 ps
CPU time 1413.66 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 05:09:18 PM PDT 24
Peak memory 289656 kb
Host smart-030a4a88-bcac-47b9-a5c5-944f7d393303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578951936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1578951936
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.121135890
Short name T363
Test name
Test status
Simulation time 136474398 ps
CPU time 8.61 seconds
Started Jul 12 04:45:54 PM PDT 24
Finished Jul 12 04:46:04 PM PDT 24
Peak memory 249200 kb
Host smart-198f026b-146e-4073-aafe-4e491c5bac11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=121135890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.121135890
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4113442679
Short name T434
Test name
Test status
Simulation time 211878122 ps
CPU time 13.93 seconds
Started Jul 12 04:45:40 PM PDT 24
Finished Jul 12 04:45:55 PM PDT 24
Peak memory 255004 kb
Host smart-4d891cb7-3c28-4ae5-b7f1-fa1f9b734318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
42679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4113442679
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3427834519
Short name T523
Test name
Test status
Simulation time 215409752 ps
CPU time 23.39 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:46:07 PM PDT 24
Peak memory 249152 kb
Host smart-5d8ca12b-3bd3-4c45-8054-99611bb93ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
34519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3427834519
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1739001398
Short name T664
Test name
Test status
Simulation time 29090560404 ps
CPU time 1537.27 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 05:12:35 PM PDT 24
Peak memory 267332 kb
Host smart-839824b5-b842-4773-b6e0-a9a13759d879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739001398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1739001398
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2824190505
Short name T298
Test name
Test status
Simulation time 14933346347 ps
CPU time 576.38 seconds
Started Jul 12 04:46:53 PM PDT 24
Finished Jul 12 04:56:30 PM PDT 24
Peak memory 248876 kb
Host smart-aecc3c4b-56b7-4199-a2c6-7bb44c0886d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824190505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2824190505
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2949679105
Short name T48
Test name
Test status
Simulation time 5193086942 ps
CPU time 82.07 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 04:47:09 PM PDT 24
Peak memory 249300 kb
Host smart-6610cdc6-caa9-49b0-957c-b1811221d6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
79105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2949679105
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3487337210
Short name T93
Test name
Test status
Simulation time 2731516992 ps
CPU time 42.31 seconds
Started Jul 12 04:45:42 PM PDT 24
Finished Jul 12 04:46:25 PM PDT 24
Peak memory 249328 kb
Host smart-69fa3d32-c240-46a1-9058-8dacd418aa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34873
37210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3487337210
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.4289969799
Short name T47
Test name
Test status
Simulation time 1419906238 ps
CPU time 18.32 seconds
Started Jul 12 04:46:53 PM PDT 24
Finished Jul 12 04:47:13 PM PDT 24
Peak memory 256152 kb
Host smart-d0789869-9331-4acd-8253-5f8a666eb33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
69799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4289969799
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2368047726
Short name T501
Test name
Test status
Simulation time 3970230204 ps
CPU time 39.55 seconds
Started Jul 12 04:45:37 PM PDT 24
Finished Jul 12 04:46:18 PM PDT 24
Peak memory 257524 kb
Host smart-5a92f271-8dab-46ca-9723-0a9e3b1d9a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23680
47726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2368047726
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.122831586
Short name T706
Test name
Test status
Simulation time 12047748410 ps
CPU time 514.43 seconds
Started Jul 12 04:45:40 PM PDT 24
Finished Jul 12 04:54:16 PM PDT 24
Peak memory 265696 kb
Host smart-53115cbb-cda0-46a0-bea8-c8f5de362cba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122831586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.122831586
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2119955598
Short name T214
Test name
Test status
Simulation time 17523431 ps
CPU time 2.73 seconds
Started Jul 12 04:45:48 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 249548 kb
Host smart-e529d196-1f54-4274-a30c-a83082db3e6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2119955598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2119955598
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1328412069
Short name T489
Test name
Test status
Simulation time 1119790511 ps
CPU time 14.59 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 04:46:01 PM PDT 24
Peak memory 249092 kb
Host smart-6550b6a9-2332-4b5d-ba72-c468e413d10e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1328412069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1328412069
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2420001894
Short name T436
Test name
Test status
Simulation time 5882999718 ps
CPU time 114.91 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:47:42 PM PDT 24
Peak memory 257360 kb
Host smart-c61bc9e8-8e74-4bc4-8291-eb1efbbdc65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
01894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2420001894
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3074693944
Short name T488
Test name
Test status
Simulation time 474919364 ps
CPU time 9.78 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:04 PM PDT 24
Peak memory 254708 kb
Host smart-b0a5ea65-27f1-4e20-bfd7-cbfbb1884de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
93944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3074693944
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.751090209
Short name T673
Test name
Test status
Simulation time 23623311560 ps
CPU time 1556.56 seconds
Started Jul 12 04:45:40 PM PDT 24
Finished Jul 12 05:11:37 PM PDT 24
Peak memory 273252 kb
Host smart-8b71eec1-cc32-4add-80cc-04ac3135994a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751090209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.751090209
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.676084808
Short name T395
Test name
Test status
Simulation time 75644099050 ps
CPU time 2192.07 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 05:22:19 PM PDT 24
Peak memory 289260 kb
Host smart-51d95c5e-1d32-4b0a-99c9-e9db6f2b0c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676084808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.676084808
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.803983843
Short name T290
Test name
Test status
Simulation time 16545932055 ps
CPU time 169.7 seconds
Started Jul 12 04:45:56 PM PDT 24
Finished Jul 12 04:48:47 PM PDT 24
Peak memory 249060 kb
Host smart-f6d32d73-c191-429c-af33-b43ca4b8d6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803983843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.803983843
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.812557440
Short name T510
Test name
Test status
Simulation time 1123724512 ps
CPU time 68.07 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:46:55 PM PDT 24
Peak memory 256512 kb
Host smart-2770db2b-7e1e-4c57-83d5-8efc876f216f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81255
7440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.812557440
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2806031220
Short name T649
Test name
Test status
Simulation time 3103377660 ps
CPU time 52.8 seconds
Started Jul 12 04:45:41 PM PDT 24
Finished Jul 12 04:46:35 PM PDT 24
Peak memory 249428 kb
Host smart-0fbd7353-6e06-4662-a4d1-28fb67fabe2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28060
31220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2806031220
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3686875138
Short name T680
Test name
Test status
Simulation time 1367951334 ps
CPU time 43.05 seconds
Started Jul 12 04:45:42 PM PDT 24
Finished Jul 12 04:46:26 PM PDT 24
Peak memory 249260 kb
Host smart-febc88f5-e42d-499a-89ef-a7b452775c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36868
75138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3686875138
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.4288929612
Short name T91
Test name
Test status
Simulation time 152165367991 ps
CPU time 2510.47 seconds
Started Jul 12 04:46:52 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 298216 kb
Host smart-5ee37559-3a2a-4877-af61-a2423afa6c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288929612 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.4288929612
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1803971421
Short name T203
Test name
Test status
Simulation time 628115144 ps
CPU time 3.96 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:11 PM PDT 24
Peak memory 249460 kb
Host smart-a75289ea-0ca3-46e1-b063-de481d7a31b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1803971421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1803971421
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1480294218
Short name T484
Test name
Test status
Simulation time 49486984916 ps
CPU time 1480.95 seconds
Started Jul 12 04:45:06 PM PDT 24
Finished Jul 12 05:09:50 PM PDT 24
Peak memory 273896 kb
Host smart-e288b809-f7e3-48ec-8f24-22542e39a39a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480294218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1480294218
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.784156589
Short name T498
Test name
Test status
Simulation time 908998526 ps
CPU time 23.23 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:29 PM PDT 24
Peak memory 249284 kb
Host smart-0fa865d0-5ef1-4d05-b568-f5bd2ff21929
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=784156589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.784156589
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1173726056
Short name T549
Test name
Test status
Simulation time 4618120967 ps
CPU time 96.6 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:46:44 PM PDT 24
Peak memory 256968 kb
Host smart-d6fd51bc-fe92-401b-b101-973c93cfc8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11737
26056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1173726056
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2692749422
Short name T487
Test name
Test status
Simulation time 385966137 ps
CPU time 10.68 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:17 PM PDT 24
Peak memory 249200 kb
Host smart-d04d4831-2ffb-4894-aff9-98b5bf95978d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26927
49422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2692749422
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3170793301
Short name T558
Test name
Test status
Simulation time 10238565097 ps
CPU time 743.82 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 04:57:31 PM PDT 24
Peak memory 273932 kb
Host smart-f7e0d9cf-f6ba-4dec-a5e2-fb638a11aa76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170793301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3170793301
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1626002332
Short name T410
Test name
Test status
Simulation time 428259218 ps
CPU time 22.58 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:29 PM PDT 24
Peak memory 249096 kb
Host smart-366f53c7-20a0-4f67-80a6-878d27747658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16260
02332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1626002332
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4128403945
Short name T601
Test name
Test status
Simulation time 263700588 ps
CPU time 18.23 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 249276 kb
Host smart-29dbfadb-71c9-4692-ba2f-54a4ff930b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41284
03945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4128403945
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2158287866
Short name T33
Test name
Test status
Simulation time 1365769229 ps
CPU time 13.5 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 04:45:30 PM PDT 24
Peak memory 271268 kb
Host smart-80826c33-3b70-4896-b37d-026792d52f54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2158287866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2158287866
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2650262593
Short name T264
Test name
Test status
Simulation time 787396471 ps
CPU time 23.11 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:28 PM PDT 24
Peak memory 249120 kb
Host smart-8b2335c3-6849-4d08-a8f1-144577829d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
62593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2650262593
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1646457569
Short name T541
Test name
Test status
Simulation time 546458399 ps
CPU time 17.23 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 257416 kb
Host smart-5c183a2c-7052-4a9b-8438-b1673cd4a453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16464
57569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1646457569
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.875379481
Short name T499
Test name
Test status
Simulation time 76521632199 ps
CPU time 1948.99 seconds
Started Jul 12 04:47:18 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 287996 kb
Host smart-59418252-8d4f-4d16-bd63-b6718e7fee30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875379481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.875379481
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4273423994
Short name T582
Test name
Test status
Simulation time 1436577175 ps
CPU time 83.15 seconds
Started Jul 12 04:45:44 PM PDT 24
Finished Jul 12 04:47:08 PM PDT 24
Peak memory 256844 kb
Host smart-0e8536e0-16de-4e01-a1bc-64add37c8eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42734
23994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4273423994
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4156383221
Short name T667
Test name
Test status
Simulation time 2228767156 ps
CPU time 35.68 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:46:23 PM PDT 24
Peak memory 256548 kb
Host smart-bee86ad6-c8b7-48d5-a9ad-e839b5c3efd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41563
83221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4156383221
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1385774309
Short name T260
Test name
Test status
Simulation time 9022060025 ps
CPU time 1006.93 seconds
Started Jul 12 04:46:01 PM PDT 24
Finished Jul 12 05:02:49 PM PDT 24
Peak memory 274140 kb
Host smart-fde7ef13-27ec-4d83-b8c8-71dbefeff8c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385774309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1385774309
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3683534424
Short name T628
Test name
Test status
Simulation time 65544383320 ps
CPU time 1400.12 seconds
Started Jul 12 04:45:49 PM PDT 24
Finished Jul 12 05:09:10 PM PDT 24
Peak memory 273260 kb
Host smart-0452edb4-0f5e-4dc7-b4cb-3da75c5b5ba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683534424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3683534424
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.160361106
Short name T220
Test name
Test status
Simulation time 33258168262 ps
CPU time 341.1 seconds
Started Jul 12 04:45:43 PM PDT 24
Finished Jul 12 04:51:25 PM PDT 24
Peak memory 249000 kb
Host smart-37e9e9fb-49ef-443a-93aa-27aab42ff9bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160361106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.160361106
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1351564517
Short name T701
Test name
Test status
Simulation time 396748143 ps
CPU time 24.52 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 04:46:17 PM PDT 24
Peak memory 255700 kb
Host smart-6f79b9a6-cef2-4aa5-940f-db0501c76647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
64517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1351564517
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3747681468
Short name T57
Test name
Test status
Simulation time 2369579577 ps
CPU time 42.86 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:46:30 PM PDT 24
Peak memory 248992 kb
Host smart-3d74cd35-389d-494e-8341-b15f504caa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37476
81468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3747681468
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3908197031
Short name T272
Test name
Test status
Simulation time 308708323 ps
CPU time 22.91 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 04:46:10 PM PDT 24
Peak memory 256964 kb
Host smart-68dc3143-27eb-4d44-a7f0-bc6c2e388bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
97031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3908197031
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2666976538
Short name T392
Test name
Test status
Simulation time 3806322951 ps
CPU time 55.12 seconds
Started Jul 12 04:45:40 PM PDT 24
Finished Jul 12 04:46:35 PM PDT 24
Peak memory 257552 kb
Host smart-3090057e-e88e-430b-aedc-5ca2423a468a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26669
76538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2666976538
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.4224104803
Short name T171
Test name
Test status
Simulation time 25452975242 ps
CPU time 1357.26 seconds
Started Jul 12 04:45:48 PM PDT 24
Finished Jul 12 05:08:26 PM PDT 24
Peak memory 290340 kb
Host smart-19e6648f-fe15-413f-9160-7955ad917329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224104803 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.4224104803
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3165382055
Short name T705
Test name
Test status
Simulation time 5732195052 ps
CPU time 566.45 seconds
Started Jul 12 04:45:55 PM PDT 24
Finished Jul 12 04:55:23 PM PDT 24
Peak memory 266716 kb
Host smart-3749068b-1c79-4b3e-a3e0-d936699690d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165382055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3165382055
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1370478875
Short name T469
Test name
Test status
Simulation time 5726853686 ps
CPU time 91.03 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:47:26 PM PDT 24
Peak memory 257600 kb
Host smart-de525614-84bc-4d84-b903-e01ccb4b0dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
78875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1370478875
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3391559798
Short name T77
Test name
Test status
Simulation time 612339153 ps
CPU time 16.93 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:46:04 PM PDT 24
Peak memory 249276 kb
Host smart-a5c51a16-576c-45e8-ba53-da2678d03b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
59798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3391559798
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1084658697
Short name T323
Test name
Test status
Simulation time 9818678873 ps
CPU time 772.83 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:58:40 PM PDT 24
Peak memory 273856 kb
Host smart-d55bf0c9-bf53-49c3-a68d-5029d6ffe8ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084658697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1084658697
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3026249392
Short name T539
Test name
Test status
Simulation time 18761653916 ps
CPU time 496.7 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 04:55:44 PM PDT 24
Peak memory 273000 kb
Host smart-710f5fca-ae1c-49a2-a0e5-da5441e99652
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026249392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3026249392
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2002650752
Short name T294
Test name
Test status
Simulation time 7782693452 ps
CPU time 326.51 seconds
Started Jul 12 04:45:44 PM PDT 24
Finished Jul 12 04:51:12 PM PDT 24
Peak memory 256084 kb
Host smart-0aca6d24-4d9b-4465-b9b5-8214911791e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002650752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2002650752
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3360594863
Short name T652
Test name
Test status
Simulation time 119767675 ps
CPU time 8.33 seconds
Started Jul 12 04:45:55 PM PDT 24
Finished Jul 12 04:46:05 PM PDT 24
Peak memory 249220 kb
Host smart-7e820b61-a3dc-4377-8665-11c41e97fc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33605
94863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3360594863
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.734445931
Short name T562
Test name
Test status
Simulation time 637761993 ps
CPU time 27.56 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 04:47:55 PM PDT 24
Peak memory 248752 kb
Host smart-9293101c-52ed-4262-a787-8954d3acd49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73444
5931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.734445931
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4015102455
Short name T630
Test name
Test status
Simulation time 698347752 ps
CPU time 45.37 seconds
Started Jul 12 04:45:49 PM PDT 24
Finished Jul 12 04:46:35 PM PDT 24
Peak memory 257456 kb
Host smart-10323cf8-93e7-47d7-a4ca-9a213b85bbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
02455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4015102455
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.45415577
Short name T670
Test name
Test status
Simulation time 3260749732 ps
CPU time 45.45 seconds
Started Jul 12 04:45:46 PM PDT 24
Finished Jul 12 04:46:33 PM PDT 24
Peak memory 256760 kb
Host smart-cb04cdc9-dcc4-40b9-9307-97057b67647b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45415
577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.45415577
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1024535795
Short name T661
Test name
Test status
Simulation time 51949477752 ps
CPU time 1231.49 seconds
Started Jul 12 04:45:54 PM PDT 24
Finished Jul 12 05:06:27 PM PDT 24
Peak memory 289504 kb
Host smart-0596123d-55d8-43e1-bbee-623beb5a8c63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024535795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1024535795
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3306014834
Short name T195
Test name
Test status
Simulation time 74673761269 ps
CPU time 2400.65 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 05:25:47 PM PDT 24
Peak memory 283880 kb
Host smart-f8d3c543-3ddb-4cfe-97bc-2a3c272d3250
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306014834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3306014834
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1350574011
Short name T257
Test name
Test status
Simulation time 3649527267 ps
CPU time 109.75 seconds
Started Jul 12 04:45:44 PM PDT 24
Finished Jul 12 04:47:35 PM PDT 24
Peak memory 257560 kb
Host smart-7bde1ffa-1991-4ed1-bb8d-f4969e12a254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
74011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1350574011
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1416634122
Short name T623
Test name
Test status
Simulation time 942302556 ps
CPU time 28.91 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:47:25 PM PDT 24
Peak memory 248708 kb
Host smart-4a621ab0-4ae4-4209-83a5-821244715a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14166
34122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1416634122
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3481569668
Short name T699
Test name
Test status
Simulation time 48424088556 ps
CPU time 1020.82 seconds
Started Jul 12 04:47:18 PM PDT 24
Finished Jul 12 05:04:20 PM PDT 24
Peak memory 284756 kb
Host smart-23059bf3-893e-4623-bcd6-60cbb586a899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481569668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3481569668
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2248234955
Short name T26
Test name
Test status
Simulation time 6158407535 ps
CPU time 915.46 seconds
Started Jul 12 04:45:45 PM PDT 24
Finished Jul 12 05:01:02 PM PDT 24
Peak memory 273864 kb
Host smart-be36a278-4a8a-40bd-9630-9d0dd76c72ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248234955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2248234955
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2352884804
Short name T345
Test name
Test status
Simulation time 1423154449 ps
CPU time 31.36 seconds
Started Jul 12 04:45:49 PM PDT 24
Finished Jul 12 04:46:21 PM PDT 24
Peak memory 256788 kb
Host smart-859c80f4-9503-4090-a0a8-9b64d543c9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23528
84804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2352884804
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2785858276
Short name T384
Test name
Test status
Simulation time 690579684 ps
CPU time 14.16 seconds
Started Jul 12 04:45:49 PM PDT 24
Finished Jul 12 04:46:04 PM PDT 24
Peak memory 256312 kb
Host smart-357540f3-7104-43d1-a676-35f1c97af363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858
58276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2785858276
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1512387092
Short name T520
Test name
Test status
Simulation time 159154703 ps
CPU time 19.63 seconds
Started Jul 12 04:45:44 PM PDT 24
Finished Jul 12 04:46:05 PM PDT 24
Peak memory 256448 kb
Host smart-db26a4e7-d452-4da9-8070-c949e3cf1816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
87092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1512387092
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1679789566
Short name T444
Test name
Test status
Simulation time 372084848 ps
CPU time 5.7 seconds
Started Jul 12 04:45:55 PM PDT 24
Finished Jul 12 04:46:02 PM PDT 24
Peak memory 240868 kb
Host smart-4a8f4953-8e52-453a-8f97-212be1fff980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16797
89566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1679789566
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3663466140
Short name T443
Test name
Test status
Simulation time 1806715887 ps
CPU time 62.96 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:58 PM PDT 24
Peak memory 257316 kb
Host smart-b30ffe97-eabe-4124-8a1d-e5622397bf72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663466140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3663466140
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2348553155
Short name T398
Test name
Test status
Simulation time 14461839403 ps
CPU time 875.6 seconds
Started Jul 12 04:46:01 PM PDT 24
Finished Jul 12 05:00:38 PM PDT 24
Peak memory 273040 kb
Host smart-eaeb4a03-662f-4652-a78b-f9c78ed86f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348553155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2348553155
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2006600147
Short name T555
Test name
Test status
Simulation time 2694272326 ps
CPU time 45.32 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 04:46:39 PM PDT 24
Peak memory 257580 kb
Host smart-008eaf25-3862-4554-a385-593d3ba7ca9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20066
00147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2006600147
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4076452956
Short name T387
Test name
Test status
Simulation time 1126408685 ps
CPU time 35.89 seconds
Started Jul 12 04:45:51 PM PDT 24
Finished Jul 12 04:46:27 PM PDT 24
Peak memory 257440 kb
Host smart-2635e143-223d-4233-b15d-026eadbbb1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40764
52956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4076452956
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.860337673
Short name T192
Test name
Test status
Simulation time 39577188347 ps
CPU time 2498.73 seconds
Started Jul 12 04:45:56 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 289532 kb
Host smart-e5ed91a9-adf0-496b-b3dc-564a87753d31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860337673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.860337673
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4017930073
Short name T548
Test name
Test status
Simulation time 20799835293 ps
CPU time 1406.66 seconds
Started Jul 12 04:46:00 PM PDT 24
Finished Jul 12 05:09:28 PM PDT 24
Peak memory 272804 kb
Host smart-75a67878-f5fd-4384-a685-6ab11a054f31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017930073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4017930073
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.743909239
Short name T267
Test name
Test status
Simulation time 14613587105 ps
CPU time 592.24 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 04:55:46 PM PDT 24
Peak memory 248164 kb
Host smart-97c72eeb-1a67-4e8f-90a4-5694ac454fb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743909239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.743909239
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3472899203
Short name T352
Test name
Test status
Simulation time 2931212377 ps
CPU time 48.27 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:42 PM PDT 24
Peak memory 257052 kb
Host smart-dc35f46e-6c38-4943-99c7-bb94c60bfbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34728
99203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3472899203
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.180050258
Short name T268
Test name
Test status
Simulation time 402103588 ps
CPU time 33.97 seconds
Started Jul 12 04:45:51 PM PDT 24
Finished Jul 12 04:46:25 PM PDT 24
Peak memory 256968 kb
Host smart-5c7ee254-067f-448c-9874-77196c7b554c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
0258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.180050258
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.829050348
Short name T616
Test name
Test status
Simulation time 1321372084 ps
CPU time 24.27 seconds
Started Jul 12 04:46:01 PM PDT 24
Finished Jul 12 04:46:27 PM PDT 24
Peak memory 256944 kb
Host smart-f14c0e23-804e-480c-a06e-bebf1fe06d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82905
0348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.829050348
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.429873695
Short name T62
Test name
Test status
Simulation time 200494484 ps
CPU time 17.53 seconds
Started Jul 12 04:46:03 PM PDT 24
Finished Jul 12 04:46:21 PM PDT 24
Peak memory 249088 kb
Host smart-2b8a4be4-01e9-42a0-a43e-94271bbd8897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42987
3695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.429873695
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2812562537
Short name T524
Test name
Test status
Simulation time 41558325552 ps
CPU time 1626.8 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 05:13:06 PM PDT 24
Peak memory 289692 kb
Host smart-aff37a04-6056-4cf4-aebe-874d5ae04e3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812562537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2812562537
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2439799850
Short name T654
Test name
Test status
Simulation time 6400538205 ps
CPU time 857.29 seconds
Started Jul 12 04:45:56 PM PDT 24
Finished Jul 12 05:00:15 PM PDT 24
Peak memory 273452 kb
Host smart-5d2431b3-6db3-4e6c-90da-f20f4be25794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439799850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2439799850
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2553242080
Short name T448
Test name
Test status
Simulation time 2198133838 ps
CPU time 66.2 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 04:47:05 PM PDT 24
Peak memory 257088 kb
Host smart-f20159a8-32f0-4ea5-88d3-b410e08c2935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
42080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2553242080
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2701462940
Short name T496
Test name
Test status
Simulation time 921750872 ps
CPU time 51.66 seconds
Started Jul 12 04:45:50 PM PDT 24
Finished Jul 12 04:46:43 PM PDT 24
Peak memory 249104 kb
Host smart-c87f4cd6-a1ca-4480-98e6-38b702dd646c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27014
62940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2701462940
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3063764011
Short name T282
Test name
Test status
Simulation time 31313230956 ps
CPU time 1773.82 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 05:15:29 PM PDT 24
Peak memory 284104 kb
Host smart-7b372cac-d384-48c8-8f4c-bc9846c56c18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063764011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3063764011
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3573225737
Short name T563
Test name
Test status
Simulation time 22392632044 ps
CPU time 236.63 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 04:49:50 PM PDT 24
Peak memory 249352 kb
Host smart-de92e9b8-cf40-49d7-90f2-65a670a90f0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573225737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3573225737
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1586616628
Short name T370
Test name
Test status
Simulation time 175937672 ps
CPU time 18.21 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:13 PM PDT 24
Peak memory 256680 kb
Host smart-ed9c73bf-d3be-488d-a46f-6efcbf724758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
16628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1586616628
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.886766473
Short name T447
Test name
Test status
Simulation time 92379437 ps
CPU time 7.26 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:02 PM PDT 24
Peak memory 249300 kb
Host smart-99054db4-40db-4787-ac3d-fdb00cdf0459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88676
6473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.886766473
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1471563326
Short name T442
Test name
Test status
Simulation time 141841339 ps
CPU time 8.07 seconds
Started Jul 12 04:45:53 PM PDT 24
Finished Jul 12 04:46:02 PM PDT 24
Peak memory 249260 kb
Host smart-43084306-c34d-4fe9-9666-51502cef13dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
63326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1471563326
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.446872269
Short name T190
Test name
Test status
Simulation time 1785701820 ps
CPU time 18.99 seconds
Started Jul 12 04:45:54 PM PDT 24
Finished Jul 12 04:46:14 PM PDT 24
Peak memory 256788 kb
Host smart-4631ef6b-f530-4986-8ce6-c716fe7995d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44687
2269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.446872269
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.181674932
Short name T95
Test name
Test status
Simulation time 611816501077 ps
CPU time 3056.37 seconds
Started Jul 12 04:45:54 PM PDT 24
Finished Jul 12 05:36:52 PM PDT 24
Peak memory 290256 kb
Host smart-eb1638c3-37d8-4a72-90f1-24f56b774e45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181674932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.181674932
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1631579881
Short name T222
Test name
Test status
Simulation time 42531345822 ps
CPU time 2793.16 seconds
Started Jul 12 04:45:52 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 289888 kb
Host smart-cb0e3d8f-4ff5-45b3-bddf-d5c81a08a889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631579881 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1631579881
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3106044250
Short name T517
Test name
Test status
Simulation time 40493838109 ps
CPU time 1104.71 seconds
Started Jul 12 04:45:55 PM PDT 24
Finished Jul 12 05:04:21 PM PDT 24
Peak memory 273808 kb
Host smart-871eff97-9066-4d30-b82b-3ee70705b328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106044250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3106044250
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1676270042
Short name T592
Test name
Test status
Simulation time 530533182 ps
CPU time 25.75 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 04:46:25 PM PDT 24
Peak memory 256464 kb
Host smart-26862f3e-03df-4ea7-84fe-316c9464c0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
70042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1676270042
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.799698080
Short name T239
Test name
Test status
Simulation time 5676319400 ps
CPU time 55.1 seconds
Started Jul 12 04:46:01 PM PDT 24
Finished Jul 12 04:46:57 PM PDT 24
Peak memory 257524 kb
Host smart-23042c17-9e72-4ba2-944c-cb87fbc7e24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79969
8080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.799698080
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3381560132
Short name T589
Test name
Test status
Simulation time 43827811955 ps
CPU time 2202.46 seconds
Started Jul 12 04:46:05 PM PDT 24
Finished Jul 12 05:22:49 PM PDT 24
Peak memory 273380 kb
Host smart-165e58c6-cd65-4b6f-b0b7-75ef21defdd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381560132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3381560132
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2661040236
Short name T416
Test name
Test status
Simulation time 27809233023 ps
CPU time 1571.56 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 05:12:21 PM PDT 24
Peak memory 273844 kb
Host smart-b72855f8-9107-4796-b078-010dd4edbc9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661040236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2661040236
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.473149418
Short name T598
Test name
Test status
Simulation time 6070219857 ps
CPU time 130.38 seconds
Started Jul 12 04:46:03 PM PDT 24
Finished Jul 12 04:48:14 PM PDT 24
Peak memory 255132 kb
Host smart-58cb278a-70b8-4e87-b85b-7d26a529a550
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473149418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.473149418
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2983155586
Short name T61
Test name
Test status
Simulation time 539937501 ps
CPU time 29.5 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 04:46:27 PM PDT 24
Peak memory 256832 kb
Host smart-7f054cba-ecb5-4688-9408-2602328e2281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29831
55586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2983155586
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.708336877
Short name T681
Test name
Test status
Simulation time 681481269 ps
CPU time 20.54 seconds
Started Jul 12 04:45:59 PM PDT 24
Finished Jul 12 04:46:21 PM PDT 24
Peak memory 255860 kb
Host smart-d20616e9-54ee-47fc-af61-2a3dbd121752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70833
6877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.708336877
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.906217985
Short name T373
Test name
Test status
Simulation time 522787159 ps
CPU time 21.31 seconds
Started Jul 12 04:45:58 PM PDT 24
Finished Jul 12 04:46:21 PM PDT 24
Peak memory 256912 kb
Host smart-1250d24e-8668-4b53-923e-7d11626c5a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90621
7985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.906217985
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2183107378
Short name T36
Test name
Test status
Simulation time 746511011 ps
CPU time 26.69 seconds
Started Jul 12 04:46:00 PM PDT 24
Finished Jul 12 04:46:27 PM PDT 24
Peak memory 257436 kb
Host smart-23d03fe0-99ea-4762-ae38-2cae95c4b5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21831
07378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2183107378
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.289697726
Short name T554
Test name
Test status
Simulation time 206552507770 ps
CPU time 3307.6 seconds
Started Jul 12 04:46:05 PM PDT 24
Finished Jul 12 05:41:15 PM PDT 24
Peak memory 302408 kb
Host smart-76eddd93-2c96-4161-a8f3-5f902d4f7cd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289697726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.289697726
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.228304924
Short name T643
Test name
Test status
Simulation time 16636383857 ps
CPU time 1018.18 seconds
Started Jul 12 04:46:03 PM PDT 24
Finished Jul 12 05:03:02 PM PDT 24
Peak memory 265692 kb
Host smart-35d37003-9b95-43a7-bfb4-4696f9a90f7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228304924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.228304924
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2466510643
Short name T611
Test name
Test status
Simulation time 1510474157 ps
CPU time 76.26 seconds
Started Jul 12 04:45:55 PM PDT 24
Finished Jul 12 04:47:12 PM PDT 24
Peak memory 256984 kb
Host smart-a04cf942-c9eb-421c-98c4-c8f29a7e1fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24665
10643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2466510643
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.994089318
Short name T390
Test name
Test status
Simulation time 342539532 ps
CPU time 22.88 seconds
Started Jul 12 04:46:00 PM PDT 24
Finished Jul 12 04:46:24 PM PDT 24
Peak memory 248632 kb
Host smart-840a4a0c-1de1-4fab-b103-8af12ffc314a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99408
9318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.994089318
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1199404378
Short name T553
Test name
Test status
Simulation time 44352995647 ps
CPU time 1049.76 seconds
Started Jul 12 04:46:04 PM PDT 24
Finished Jul 12 05:03:35 PM PDT 24
Peak memory 273176 kb
Host smart-4d893dd6-5882-4685-aa3f-6d656d65ddb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199404378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1199404378
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1254944462
Short name T4
Test name
Test status
Simulation time 107130097598 ps
CPU time 1432.36 seconds
Started Jul 12 04:46:03 PM PDT 24
Finished Jul 12 05:09:56 PM PDT 24
Peak memory 273480 kb
Host smart-67d69f69-1555-4291-9d36-1fd8f53ea0bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254944462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1254944462
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.946696388
Short name T2
Test name
Test status
Simulation time 21635671849 ps
CPU time 524.98 seconds
Started Jul 12 04:46:04 PM PDT 24
Finished Jul 12 04:54:51 PM PDT 24
Peak memory 256232 kb
Host smart-ab22827e-29ea-4a8b-9c69-64cb0b79e20a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946696388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.946696388
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2213459569
Short name T406
Test name
Test status
Simulation time 1064841502 ps
CPU time 15.71 seconds
Started Jul 12 04:45:57 PM PDT 24
Finished Jul 12 04:46:15 PM PDT 24
Peak memory 249272 kb
Host smart-bd0264f6-81a3-44c9-b082-ac9e3724caed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22134
59569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2213459569
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3799690238
Short name T639
Test name
Test status
Simulation time 1722201317 ps
CPU time 60.8 seconds
Started Jul 12 04:45:58 PM PDT 24
Finished Jul 12 04:47:01 PM PDT 24
Peak memory 249268 kb
Host smart-f694a008-f7f5-4695-b278-5fc3167952b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
90238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3799690238
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3169840395
Short name T111
Test name
Test status
Simulation time 1801532083 ps
CPU time 28.09 seconds
Started Jul 12 04:45:58 PM PDT 24
Finished Jul 12 04:46:28 PM PDT 24
Peak memory 256848 kb
Host smart-536e34f4-6ca8-4bf4-a20c-1db873218581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31698
40395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3169840395
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2819419566
Short name T658
Test name
Test status
Simulation time 219849715 ps
CPU time 7.08 seconds
Started Jul 12 04:46:05 PM PDT 24
Finished Jul 12 04:46:13 PM PDT 24
Peak memory 255432 kb
Host smart-75938374-b31c-4d1c-84ab-8763d722045c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28194
19566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2819419566
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4257597035
Short name T703
Test name
Test status
Simulation time 80180716451 ps
CPU time 2141.69 seconds
Started Jul 12 04:46:06 PM PDT 24
Finished Jul 12 05:21:50 PM PDT 24
Peak memory 273108 kb
Host smart-97c4d9f6-5dc9-49f9-841b-0fa5692ae5de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257597035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4257597035
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1956572967
Short name T238
Test name
Test status
Simulation time 49729421794 ps
CPU time 1460.62 seconds
Started Jul 12 04:46:05 PM PDT 24
Finished Jul 12 05:10:28 PM PDT 24
Peak memory 273480 kb
Host smart-bc4f7a7b-8726-403e-a39a-5e4b11aa7eff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956572967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1956572967
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1973997887
Short name T200
Test name
Test status
Simulation time 3425757270 ps
CPU time 80.38 seconds
Started Jul 12 04:46:02 PM PDT 24
Finished Jul 12 04:47:23 PM PDT 24
Peak memory 257492 kb
Host smart-1335c2f0-96c2-4596-9e06-aa566f265378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19739
97887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1973997887
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2211368536
Short name T698
Test name
Test status
Simulation time 1112972452 ps
CPU time 43.63 seconds
Started Jul 12 04:46:05 PM PDT 24
Finished Jul 12 04:46:50 PM PDT 24
Peak memory 257408 kb
Host smart-fd37968b-c6b8-4cf7-a0e6-e3e3308ccd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22113
68536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2211368536
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3502200366
Short name T283
Test name
Test status
Simulation time 7118927192 ps
CPU time 632.09 seconds
Started Jul 12 04:46:04 PM PDT 24
Finished Jul 12 04:56:38 PM PDT 24
Peak memory 272048 kb
Host smart-b67513f2-c25f-4ff9-b6b5-560b107bdcba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502200366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3502200366
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2866374238
Short name T380
Test name
Test status
Simulation time 8323582907 ps
CPU time 818.63 seconds
Started Jul 12 04:46:02 PM PDT 24
Finished Jul 12 04:59:42 PM PDT 24
Peak memory 268804 kb
Host smart-a41880a9-c039-4313-bd30-326caede2fa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866374238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2866374238
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3128522297
Short name T629
Test name
Test status
Simulation time 1283805935 ps
CPU time 56.14 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 04:47:05 PM PDT 24
Peak memory 248196 kb
Host smart-4f7d3b95-46f6-469b-b9f1-219586e10343
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128522297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3128522297
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1710711326
Short name T383
Test name
Test status
Simulation time 23163986 ps
CPU time 4.04 seconds
Started Jul 12 04:46:02 PM PDT 24
Finished Jul 12 04:46:06 PM PDT 24
Peak memory 249272 kb
Host smart-eee0c341-c133-46e9-81ae-68091fb2549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17107
11326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1710711326
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2444710300
Short name T621
Test name
Test status
Simulation time 3993521929 ps
CPU time 55.18 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:47:06 PM PDT 24
Peak memory 257508 kb
Host smart-234b6b7d-adcb-4835-b6d4-470d475a788d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24447
10300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2444710300
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2702053069
Short name T604
Test name
Test status
Simulation time 546858954 ps
CPU time 36.69 seconds
Started Jul 12 04:46:04 PM PDT 24
Finished Jul 12 04:46:42 PM PDT 24
Peak memory 256584 kb
Host smart-2fff7763-2922-4121-8c96-b32099b6f889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
53069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2702053069
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1006832345
Short name T17
Test name
Test status
Simulation time 262905193 ps
CPU time 16.54 seconds
Started Jul 12 04:46:03 PM PDT 24
Finished Jul 12 04:46:20 PM PDT 24
Peak memory 249292 kb
Host smart-c259e655-6b1f-4fd4-9b63-4105b2b2cbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10068
32345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1006832345
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3735188891
Short name T511
Test name
Test status
Simulation time 21545382213 ps
CPU time 654.66 seconds
Started Jul 12 04:46:05 PM PDT 24
Finished Jul 12 04:57:02 PM PDT 24
Peak memory 265708 kb
Host smart-212d5813-0f8d-4e81-b0fa-6776c655b98e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735188891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3735188891
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3125889565
Short name T596
Test name
Test status
Simulation time 5150928915 ps
CPU time 650.76 seconds
Started Jul 12 04:46:12 PM PDT 24
Finished Jul 12 04:57:03 PM PDT 24
Peak memory 273892 kb
Host smart-1080af42-c747-4f4e-98e3-009b0b484906
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125889565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3125889565
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3404224643
Short name T595
Test name
Test status
Simulation time 5197197702 ps
CPU time 290.92 seconds
Started Jul 12 04:46:03 PM PDT 24
Finished Jul 12 04:50:54 PM PDT 24
Peak memory 257588 kb
Host smart-c473d2f0-6cca-4f78-b51d-d05ded020c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34042
24643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3404224643
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.151758096
Short name T634
Test name
Test status
Simulation time 1102022214 ps
CPU time 29.85 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 04:46:39 PM PDT 24
Peak memory 249148 kb
Host smart-4123ea29-dd4c-48d4-aa29-1a9862a9492c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15175
8096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.151758096
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.722425583
Short name T593
Test name
Test status
Simulation time 117042913482 ps
CPU time 1520.19 seconds
Started Jul 12 04:46:10 PM PDT 24
Finished Jul 12 05:11:32 PM PDT 24
Peak memory 273276 kb
Host smart-dad43296-6813-4e94-9479-0c65e54d909e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722425583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.722425583
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2306996524
Short name T7
Test name
Test status
Simulation time 15457751445 ps
CPU time 1400.39 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 05:09:36 PM PDT 24
Peak memory 288244 kb
Host smart-1564795b-9a1b-48ee-84fc-2c356ddb74d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306996524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2306996524
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.4091592229
Short name T376
Test name
Test status
Simulation time 212984606 ps
CPU time 20.13 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 04:46:29 PM PDT 24
Peak memory 256520 kb
Host smart-452bd8e6-a2a2-461a-8a66-752bd7e8f1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915
92229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.4091592229
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3512274485
Short name T6
Test name
Test status
Simulation time 133796798 ps
CPU time 8.38 seconds
Started Jul 12 04:46:04 PM PDT 24
Finished Jul 12 04:46:14 PM PDT 24
Peak memory 251360 kb
Host smart-a5fb6b0d-4f9c-41e8-b7b4-83e34cec95af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122
74485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3512274485
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2726817819
Short name T35
Test name
Test status
Simulation time 101817677 ps
CPU time 5.17 seconds
Started Jul 12 04:46:09 PM PDT 24
Finished Jul 12 04:46:16 PM PDT 24
Peak memory 253128 kb
Host smart-5045b79f-bd27-4acc-8d43-4fb018b11b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268
17819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2726817819
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.124122379
Short name T490
Test name
Test status
Simulation time 280052873 ps
CPU time 26.16 seconds
Started Jul 12 04:46:02 PM PDT 24
Finished Jul 12 04:46:29 PM PDT 24
Peak memory 256056 kb
Host smart-1ac49388-0529-4948-980e-482d8fbc23da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12412
2379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.124122379
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1607546291
Short name T75
Test name
Test status
Simulation time 15991397376 ps
CPU time 1516.89 seconds
Started Jul 12 04:46:11 PM PDT 24
Finished Jul 12 05:11:29 PM PDT 24
Peak memory 298584 kb
Host smart-2951c1fd-191d-4134-b42d-f229f13c5dac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607546291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1607546291
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2945660002
Short name T482
Test name
Test status
Simulation time 133559396311 ps
CPU time 2387.29 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 290064 kb
Host smart-916b4be0-c205-48c2-a6e5-60de51a5580a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945660002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2945660002
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2806871435
Short name T572
Test name
Test status
Simulation time 4629890582 ps
CPU time 76.33 seconds
Started Jul 12 04:46:15 PM PDT 24
Finished Jul 12 04:47:32 PM PDT 24
Peak memory 257412 kb
Host smart-6be2d207-a019-4da8-979a-e5c80bd5c9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28068
71435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2806871435
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1151138761
Short name T109
Test name
Test status
Simulation time 727007451 ps
CPU time 48.44 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:46:58 PM PDT 24
Peak memory 249120 kb
Host smart-26cb4d0e-174a-4bf0-8f1b-c59d4bea0f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11511
38761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1151138761
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3209272749
Short name T319
Test name
Test status
Simulation time 31263262090 ps
CPU time 1792.6 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 05:16:02 PM PDT 24
Peak memory 273744 kb
Host smart-9fd1f5e0-9b2c-4143-8922-a7ef9790951d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209272749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3209272749
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3885337180
Short name T359
Test name
Test status
Simulation time 29676715714 ps
CPU time 1633.2 seconds
Started Jul 12 04:46:12 PM PDT 24
Finished Jul 12 05:13:26 PM PDT 24
Peak memory 273956 kb
Host smart-e78eac99-0a9d-4e39-808e-af51249e141b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885337180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3885337180
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1930774246
Short name T537
Test name
Test status
Simulation time 305420223 ps
CPU time 7.29 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 04:46:16 PM PDT 24
Peak memory 253000 kb
Host smart-942c3b8f-4773-48fe-b33e-087fd2bf47b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19307
74246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1930774246
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2553990001
Short name T471
Test name
Test status
Simulation time 1060431833 ps
CPU time 31.99 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 04:46:41 PM PDT 24
Peak memory 249052 kb
Host smart-148079f6-f348-44ce-846f-4835ef05699f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25539
90001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2553990001
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1474404892
Short name T454
Test name
Test status
Simulation time 1547792081 ps
CPU time 14.87 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:46:25 PM PDT 24
Peak memory 255736 kb
Host smart-2f7d8c9e-f448-4b7c-abb7-ad6c460931bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
04892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1474404892
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3604455182
Short name T425
Test name
Test status
Simulation time 1843850644 ps
CPU time 21.82 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:46:32 PM PDT 24
Peak memory 257308 kb
Host smart-d87eff02-7324-4be9-97f1-adfd3ec8d95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36044
55182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3604455182
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.504284229
Short name T45
Test name
Test status
Simulation time 17882363669 ps
CPU time 1492.08 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 05:11:08 PM PDT 24
Peak memory 290276 kb
Host smart-1c66cdc8-359b-40fb-84ad-372863080f0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504284229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.504284229
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4167622880
Short name T223
Test name
Test status
Simulation time 85837011537 ps
CPU time 4856.28 seconds
Started Jul 12 04:46:07 PM PDT 24
Finished Jul 12 06:07:06 PM PDT 24
Peak memory 317040 kb
Host smart-af1fe623-511d-4e93-ab2a-4b9cf7415990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167622880 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4167622880
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.925596237
Short name T207
Test name
Test status
Simulation time 87069607 ps
CPU time 3.48 seconds
Started Jul 12 04:45:10 PM PDT 24
Finished Jul 12 04:45:15 PM PDT 24
Peak memory 249540 kb
Host smart-2f0c2ff9-1e66-4711-b630-b8d03d251419
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=925596237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.925596237
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2426315349
Short name T55
Test name
Test status
Simulation time 29125424668 ps
CPU time 1315.65 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 05:07:15 PM PDT 24
Peak memory 290248 kb
Host smart-93fc8381-64d6-4594-979b-963f886abcde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426315349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2426315349
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4273968864
Short name T63
Test name
Test status
Simulation time 1938485886 ps
CPU time 34.4 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 249256 kb
Host smart-2398da61-1cf7-45e0-adcd-ca3470cffdbb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4273968864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4273968864
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.299141028
Short name T486
Test name
Test status
Simulation time 482752847 ps
CPU time 39.66 seconds
Started Jul 12 04:45:10 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 256924 kb
Host smart-d72bae78-04f6-477f-9150-a0741b631ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29914
1028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.299141028
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2002384316
Short name T543
Test name
Test status
Simulation time 1399718100 ps
CPU time 8.04 seconds
Started Jul 12 04:45:09 PM PDT 24
Finished Jul 12 04:45:18 PM PDT 24
Peak memory 252068 kb
Host smart-3041b60d-d2e9-40d1-a668-2399b0e3e665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20023
84316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2002384316
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1729804917
Short name T300
Test name
Test status
Simulation time 169175816370 ps
CPU time 2575.9 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 284400 kb
Host smart-8b13e537-4189-4696-9f59-3473fd111b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729804917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1729804917
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3519426978
Short name T346
Test name
Test status
Simulation time 132710209292 ps
CPU time 1399.1 seconds
Started Jul 12 04:45:09 PM PDT 24
Finished Jul 12 05:08:30 PM PDT 24
Peak memory 290288 kb
Host smart-824c1f75-536a-4c41-b0ab-1942f60aa25c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519426978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3519426978
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.748265200
Short name T285
Test name
Test status
Simulation time 17875816417 ps
CPU time 186.26 seconds
Started Jul 12 04:45:08 PM PDT 24
Finished Jul 12 04:48:16 PM PDT 24
Peak memory 249416 kb
Host smart-a6a3682f-655d-462e-9969-967acb9c96d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748265200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.748265200
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4136959058
Short name T570
Test name
Test status
Simulation time 171874444 ps
CPU time 16.47 seconds
Started Jul 12 04:45:13 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 249292 kb
Host smart-33cb756d-deaa-46ca-b72d-fe53f4745c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41369
59058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4136959058
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3942685376
Short name T21
Test name
Test status
Simulation time 924328502 ps
CPU time 14.56 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:32 PM PDT 24
Peak memory 253684 kb
Host smart-94c34cec-d41a-454e-9a2b-f6f900110532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39426
85376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3942685376
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.565851679
Short name T12
Test name
Test status
Simulation time 607599017 ps
CPU time 28.32 seconds
Started Jul 12 04:45:09 PM PDT 24
Finished Jul 12 04:45:39 PM PDT 24
Peak memory 266516 kb
Host smart-40c724c4-16be-4301-8e71-d882d1ebcf17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=565851679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.565851679
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1528244547
Short name T500
Test name
Test status
Simulation time 544915287 ps
CPU time 8.84 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:26 PM PDT 24
Peak memory 248780 kb
Host smart-e74e07e2-31ed-42da-bf7a-77d227ec496c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15282
44547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1528244547
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.837165383
Short name T453
Test name
Test status
Simulation time 340618956 ps
CPU time 11.57 seconds
Started Jul 12 04:45:08 PM PDT 24
Finished Jul 12 04:45:21 PM PDT 24
Peak memory 249664 kb
Host smart-229c3fb5-c349-49da-85ce-cd9598bf5dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83716
5383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.837165383
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1030689718
Short name T571
Test name
Test status
Simulation time 13762556508 ps
CPU time 862.34 seconds
Started Jul 12 04:45:07 PM PDT 24
Finished Jul 12 04:59:32 PM PDT 24
Peak memory 265796 kb
Host smart-ed77b783-3ec7-40a8-9581-294284d374f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030689718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1030689718
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1756270022
Short name T531
Test name
Test status
Simulation time 168862059999 ps
CPU time 2608.15 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 270404 kb
Host smart-2b1b51e0-dd2e-4384-9779-65849e43a888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756270022 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1756270022
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.489921218
Short name T550
Test name
Test status
Simulation time 170976095711 ps
CPU time 1446.61 seconds
Started Jul 12 04:46:13 PM PDT 24
Finished Jul 12 05:10:21 PM PDT 24
Peak memory 273472 kb
Host smart-e78ae63b-7e1c-46ce-aff8-a8b859a8b0d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489921218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.489921218
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1810725376
Short name T427
Test name
Test status
Simulation time 4303749779 ps
CPU time 49.57 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:47:00 PM PDT 24
Peak memory 250348 kb
Host smart-47f06243-5685-4a51-9c62-8151de653c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
25376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1810725376
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2594999274
Short name T674
Test name
Test status
Simulation time 604774979 ps
CPU time 41.21 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:46:51 PM PDT 24
Peak memory 249076 kb
Host smart-d2564c52-2d24-47ac-8773-b187cfcb7d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25949
99274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2594999274
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2006355635
Short name T580
Test name
Test status
Simulation time 24699356917 ps
CPU time 1734.53 seconds
Started Jul 12 04:46:16 PM PDT 24
Finished Jul 12 05:15:12 PM PDT 24
Peak memory 283468 kb
Host smart-5a724886-90d5-43b3-8d1d-ac8a5a316991
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006355635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2006355635
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.117401411
Short name T415
Test name
Test status
Simulation time 4834651603 ps
CPU time 74.9 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:47:25 PM PDT 24
Peak memory 256796 kb
Host smart-c5639bf4-6a3f-48b0-99fa-186800a5a6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11740
1411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.117401411
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1736994842
Short name T421
Test name
Test status
Simulation time 938146962 ps
CPU time 16.64 seconds
Started Jul 12 04:46:19 PM PDT 24
Finished Jul 12 04:46:37 PM PDT 24
Peak memory 254324 kb
Host smart-4297ff47-ada9-4a12-9821-0cc0889aea7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17369
94842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1736994842
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.746547673
Short name T626
Test name
Test status
Simulation time 2164890341 ps
CPU time 38.41 seconds
Started Jul 12 04:46:08 PM PDT 24
Finished Jul 12 04:46:48 PM PDT 24
Peak memory 256864 kb
Host smart-7483821c-835e-4176-a8bd-2934d1c1daff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74654
7673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.746547673
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1543376235
Short name T176
Test name
Test status
Simulation time 1552176182 ps
CPU time 43.43 seconds
Started Jul 12 04:46:15 PM PDT 24
Finished Jul 12 04:46:59 PM PDT 24
Peak memory 257252 kb
Host smart-d6c5deee-9433-40df-8181-8dbeaa7f182d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15433
76235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1543376235
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3972341167
Short name T573
Test name
Test status
Simulation time 168966190508 ps
CPU time 2734.23 seconds
Started Jul 12 04:46:24 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 298372 kb
Host smart-9637aa12-a553-48ff-8db9-f3ff795aa16e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972341167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3972341167
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.478190431
Short name T397
Test name
Test status
Simulation time 16566045004 ps
CPU time 1902.48 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 05:17:57 PM PDT 24
Peak memory 290000 kb
Host smart-23ed7bb7-1363-448b-b45e-3811c22e2db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478190431 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.478190431
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1198977705
Short name T515
Test name
Test status
Simulation time 8368595433 ps
CPU time 248.37 seconds
Started Jul 12 04:46:13 PM PDT 24
Finished Jul 12 04:50:22 PM PDT 24
Peak memory 257448 kb
Host smart-db276fd2-e25b-45c6-8b68-a34c528192a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11989
77705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1198977705
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3375376729
Short name T18
Test name
Test status
Simulation time 500418206 ps
CPU time 32.9 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 04:46:48 PM PDT 24
Peak memory 249136 kb
Host smart-147b9e5b-02c7-4489-84a5-e0cc2c152eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33753
76729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3375376729
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2000564313
Short name T273
Test name
Test status
Simulation time 16429836641 ps
CPU time 1044.17 seconds
Started Jul 12 04:46:13 PM PDT 24
Finished Jul 12 05:03:38 PM PDT 24
Peak memory 273608 kb
Host smart-b40b26f7-06cb-4144-963d-a340b608568a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000564313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2000564313
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1556210228
Short name T399
Test name
Test status
Simulation time 113404342 ps
CPU time 10.37 seconds
Started Jul 12 04:46:24 PM PDT 24
Finished Jul 12 04:46:36 PM PDT 24
Peak memory 256832 kb
Host smart-0ccbfa2f-2284-4b60-93aa-a976c2fde0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15562
10228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1556210228
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1418557757
Short name T536
Test name
Test status
Simulation time 324122897 ps
CPU time 28.05 seconds
Started Jul 12 04:46:13 PM PDT 24
Finished Jul 12 04:46:42 PM PDT 24
Peak memory 257344 kb
Host smart-13f6344a-e5a3-4219-bccd-ab29c56d180f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
57757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1418557757
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4221102275
Short name T495
Test name
Test status
Simulation time 305744561 ps
CPU time 18.35 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 04:46:34 PM PDT 24
Peak memory 256088 kb
Host smart-7b568006-0303-4e42-aac0-df5f4d95183f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42211
02275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4221102275
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.425305511
Short name T378
Test name
Test status
Simulation time 1374937815 ps
CPU time 51.15 seconds
Started Jul 12 04:46:13 PM PDT 24
Finished Jul 12 04:47:05 PM PDT 24
Peak memory 257288 kb
Host smart-f6da2635-9b2d-46ac-a651-6aa6e74110ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42530
5511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.425305511
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2518883092
Short name T460
Test name
Test status
Simulation time 788459112 ps
CPU time 78.37 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 04:47:33 PM PDT 24
Peak memory 257332 kb
Host smart-0cebf1ee-3d16-4a54-beec-d27cbd724c07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518883092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2518883092
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2705219422
Short name T610
Test name
Test status
Simulation time 163347060550 ps
CPU time 2735.73 seconds
Started Jul 12 04:46:23 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 289320 kb
Host smart-e3e031ba-fead-46c1-8222-96be21e4961d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705219422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2705219422
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3068908589
Short name T39
Test name
Test status
Simulation time 3820007338 ps
CPU time 101.78 seconds
Started Jul 12 04:46:23 PM PDT 24
Finished Jul 12 04:48:06 PM PDT 24
Peak memory 257568 kb
Host smart-fa1ada8a-0df4-4fbc-ab92-1fdad9954bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30689
08589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3068908589
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2939841831
Short name T576
Test name
Test status
Simulation time 2535956878 ps
CPU time 21.47 seconds
Started Jul 12 04:46:19 PM PDT 24
Finished Jul 12 04:46:41 PM PDT 24
Peak memory 249864 kb
Host smart-1781ea21-b960-484d-8714-2968d9f19c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29398
41831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2939841831
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4079997256
Short name T331
Test name
Test status
Simulation time 35053583501 ps
CPU time 2155.25 seconds
Started Jul 12 04:46:21 PM PDT 24
Finished Jul 12 05:22:17 PM PDT 24
Peak memory 286500 kb
Host smart-11daf984-62e2-4660-b74b-7ee5637301c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079997256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4079997256
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.874211746
Short name T83
Test name
Test status
Simulation time 192001447175 ps
CPU time 2791.99 seconds
Started Jul 12 04:46:18 PM PDT 24
Finished Jul 12 05:32:51 PM PDT 24
Peak memory 289584 kb
Host smart-10347521-2851-42d2-8321-9acdd1b63b4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874211746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.874211746
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3347062807
Short name T306
Test name
Test status
Simulation time 6935824206 ps
CPU time 294.66 seconds
Started Jul 12 04:46:19 PM PDT 24
Finished Jul 12 04:51:14 PM PDT 24
Peak memory 249564 kb
Host smart-e3a9b386-8087-4a00-b797-0de0ec6548f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347062807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3347062807
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3958553904
Short name T491
Test name
Test status
Simulation time 388915012 ps
CPU time 12.88 seconds
Started Jul 12 04:46:14 PM PDT 24
Finished Jul 12 04:46:28 PM PDT 24
Peak memory 256592 kb
Host smart-b7168841-1942-45da-8d53-35f05fba46ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
53904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3958553904
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2107546460
Short name T348
Test name
Test status
Simulation time 3282320729 ps
CPU time 15.81 seconds
Started Jul 12 04:46:11 PM PDT 24
Finished Jul 12 04:46:28 PM PDT 24
Peak memory 249412 kb
Host smart-d4f3397b-cd8b-4efd-8356-4d49bbdab868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
46460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2107546460
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1554114348
Short name T586
Test name
Test status
Simulation time 900692603 ps
CPU time 29.94 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 04:46:56 PM PDT 24
Peak memory 256484 kb
Host smart-0938950c-fcbb-4d37-be21-64a6b3e6f33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
14348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1554114348
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3691177131
Short name T494
Test name
Test status
Simulation time 5838398318 ps
CPU time 488.99 seconds
Started Jul 12 04:46:23 PM PDT 24
Finished Jul 12 04:54:33 PM PDT 24
Peak memory 265680 kb
Host smart-42880c71-0362-498e-89da-d37fbcec3938
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691177131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3691177131
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1812012268
Short name T105
Test name
Test status
Simulation time 34150367076 ps
CPU time 729.5 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 04:58:37 PM PDT 24
Peak memory 273364 kb
Host smart-389de1e1-dd2a-441f-b634-d1543d3760c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812012268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1812012268
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3869131641
Short name T69
Test name
Test status
Simulation time 4985936795 ps
CPU time 172.74 seconds
Started Jul 12 04:46:22 PM PDT 24
Finished Jul 12 04:49:15 PM PDT 24
Peak memory 257468 kb
Host smart-24fe747a-c547-406f-95e6-1e20caca2f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38691
31641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3869131641
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3063962544
Short name T241
Test name
Test status
Simulation time 3510209874 ps
CPU time 49.7 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 04:47:16 PM PDT 24
Peak memory 249336 kb
Host smart-09345bce-bcdd-4b27-a052-70923feabb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30639
62544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3063962544
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2197418418
Short name T263
Test name
Test status
Simulation time 27393562457 ps
CPU time 1161.47 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 05:05:48 PM PDT 24
Peak memory 273940 kb
Host smart-4b2f62f2-6d6f-4381-b492-28e5ba140ae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197418418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2197418418
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1992738425
Short name T258
Test name
Test status
Simulation time 43225030983 ps
CPU time 1144.41 seconds
Started Jul 12 04:46:26 PM PDT 24
Finished Jul 12 05:05:32 PM PDT 24
Peak memory 289364 kb
Host smart-1274bc4a-26e6-4f67-aae7-a07ce8835940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992738425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1992738425
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.746180277
Short name T296
Test name
Test status
Simulation time 2820467022 ps
CPU time 121.09 seconds
Started Jul 12 04:46:28 PM PDT 24
Finished Jul 12 04:48:31 PM PDT 24
Peak memory 256456 kb
Host smart-654c0f79-2161-4ca6-bf2c-92d2f1af9bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746180277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.746180277
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.96980307
Short name T385
Test name
Test status
Simulation time 544330647 ps
CPU time 30.35 seconds
Started Jul 12 04:46:20 PM PDT 24
Finished Jul 12 04:46:51 PM PDT 24
Peak memory 249196 kb
Host smart-98a22d20-e29a-4da7-9452-11cf1f9b48cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96980
307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.96980307
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.8937362
Short name T551
Test name
Test status
Simulation time 1069271859 ps
CPU time 61.04 seconds
Started Jul 12 04:46:20 PM PDT 24
Finished Jul 12 04:47:21 PM PDT 24
Peak memory 249088 kb
Host smart-b38b3e3c-2032-41e6-9542-e7263d7e75db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89373
62 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.8937362
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3296504420
Short name T365
Test name
Test status
Simulation time 123894465 ps
CPU time 9.42 seconds
Started Jul 12 04:46:28 PM PDT 24
Finished Jul 12 04:46:39 PM PDT 24
Peak memory 253284 kb
Host smart-6dd7ddf1-6eaf-447f-b166-ffda3bc989f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32965
04420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3296504420
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2820906813
Short name T19
Test name
Test status
Simulation time 782752868 ps
CPU time 53.56 seconds
Started Jul 12 04:46:20 PM PDT 24
Finished Jul 12 04:47:14 PM PDT 24
Peak memory 249256 kb
Host smart-1f26da3d-89cb-48b2-9e31-2fa6eb9a7c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28209
06813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2820906813
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.300344877
Short name T675
Test name
Test status
Simulation time 21807511049 ps
CPU time 1779.61 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 05:16:06 PM PDT 24
Peak memory 305236 kb
Host smart-c15a7e9c-1d39-42b1-8ecd-1dcc57215b94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300344877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.300344877
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2438861964
Short name T217
Test name
Test status
Simulation time 193860478881 ps
CPU time 2776.47 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 05:32:44 PM PDT 24
Peak memory 289576 kb
Host smart-9b2a5253-6461-4fc8-977d-2b5ab519a6e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438861964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2438861964
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1387887260
Short name T349
Test name
Test status
Simulation time 23491842486 ps
CPU time 85.09 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 04:47:51 PM PDT 24
Peak memory 256824 kb
Host smart-8f0dac05-2754-4fea-8e75-426fe2a277cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878
87260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1387887260
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2006002288
Short name T402
Test name
Test status
Simulation time 191595262 ps
CPU time 4.46 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 04:46:33 PM PDT 24
Peak memory 249272 kb
Host smart-65ce7b89-5aac-4fbe-8252-db915bf8eb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20060
02288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2006002288
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2046636993
Short name T467
Test name
Test status
Simulation time 116777603193 ps
CPU time 1916.7 seconds
Started Jul 12 04:46:28 PM PDT 24
Finished Jul 12 05:18:27 PM PDT 24
Peak memory 284660 kb
Host smart-ef7e7530-5611-422b-9a51-26242a848473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046636993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2046636993
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2104557222
Short name T364
Test name
Test status
Simulation time 982408692 ps
CPU time 22.14 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 04:46:50 PM PDT 24
Peak memory 256524 kb
Host smart-9e24626e-1a2c-49fd-a71d-9dae738f4b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
57222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2104557222
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1633942028
Short name T414
Test name
Test status
Simulation time 4621350049 ps
CPU time 63.74 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 04:47:30 PM PDT 24
Peak memory 249216 kb
Host smart-dde481fe-d63e-488c-898b-a77bdae51c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16339
42028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1633942028
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.571974113
Short name T627
Test name
Test status
Simulation time 407599515 ps
CPU time 31.29 seconds
Started Jul 12 04:46:32 PM PDT 24
Finished Jul 12 04:47:04 PM PDT 24
Peak memory 256340 kb
Host smart-c756a767-1b0e-4032-a6a5-87d6275f9f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57197
4113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.571974113
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2583916381
Short name T481
Test name
Test status
Simulation time 184200272 ps
CPU time 4.13 seconds
Started Jul 12 04:46:24 PM PDT 24
Finished Jul 12 04:46:29 PM PDT 24
Peak memory 251424 kb
Host smart-749d0436-00cb-42ce-b994-1ea4a8ae40e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25839
16381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2583916381
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2229613121
Short name T615
Test name
Test status
Simulation time 750007257 ps
CPU time 21.51 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 04:46:50 PM PDT 24
Peak memory 257420 kb
Host smart-33c23fe6-abdd-4f4e-9437-59f726472979
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229613121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2229613121
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4002687806
Short name T458
Test name
Test status
Simulation time 123310936782 ps
CPU time 1755.13 seconds
Started Jul 12 04:46:31 PM PDT 24
Finished Jul 12 05:15:47 PM PDT 24
Peak memory 283872 kb
Host smart-99e30dba-22b5-44da-9c75-8e3cd5915b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002687806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4002687806
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3717048517
Short name T575
Test name
Test status
Simulation time 738080637 ps
CPU time 68.02 seconds
Started Jul 12 04:46:35 PM PDT 24
Finished Jul 12 04:47:44 PM PDT 24
Peak memory 256176 kb
Host smart-a8084f3a-b216-466c-8f47-92d1e9a7baff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170
48517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3717048517
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3867830569
Short name T388
Test name
Test status
Simulation time 244691286 ps
CPU time 14.96 seconds
Started Jul 12 04:46:32 PM PDT 24
Finished Jul 12 04:46:47 PM PDT 24
Peak memory 248832 kb
Host smart-0b707fa2-b112-4c62-a375-8e848b6a6864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678
30569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3867830569
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1146692337
Short name T355
Test name
Test status
Simulation time 10899131917 ps
CPU time 1173.98 seconds
Started Jul 12 04:46:30 PM PDT 24
Finished Jul 12 05:06:06 PM PDT 24
Peak memory 290320 kb
Host smart-8c4b0460-3ade-40d4-97e1-0ce1b0573d0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146692337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1146692337
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1955223344
Short name T614
Test name
Test status
Simulation time 13867718690 ps
CPU time 278.81 seconds
Started Jul 12 04:46:33 PM PDT 24
Finished Jul 12 04:51:13 PM PDT 24
Peak memory 249392 kb
Host smart-3a44d60d-decc-4645-8b80-c31217e7fbaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955223344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1955223344
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.640031724
Short name T463
Test name
Test status
Simulation time 1568428889 ps
CPU time 34.74 seconds
Started Jul 12 04:46:27 PM PDT 24
Finished Jul 12 04:47:04 PM PDT 24
Peak memory 257204 kb
Host smart-a360b4c8-ff3f-4222-8bee-6f2362fb578d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64003
1724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.640031724
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1611484699
Short name T94
Test name
Test status
Simulation time 1465364602 ps
CPU time 50.34 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 04:47:17 PM PDT 24
Peak memory 256988 kb
Host smart-4fd237b6-81b8-4a7d-ac39-93979c62f069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114
84699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1611484699
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2774755629
Short name T405
Test name
Test status
Simulation time 677442922 ps
CPU time 36.63 seconds
Started Jul 12 04:46:25 PM PDT 24
Finished Jul 12 04:47:03 PM PDT 24
Peak memory 257392 kb
Host smart-469a81b7-6d78-4e2d-a35e-0aad1226e282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27747
55629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2774755629
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.4032373587
Short name T644
Test name
Test status
Simulation time 37736241757 ps
CPU time 2115.92 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 05:21:53 PM PDT 24
Peak memory 290100 kb
Host smart-04f4bdc5-72b1-4f89-9787-3b7b296e53b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032373587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.4032373587
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2580075215
Short name T231
Test name
Test status
Simulation time 211653595572 ps
CPU time 4833.35 seconds
Started Jul 12 04:46:35 PM PDT 24
Finished Jul 12 06:07:10 PM PDT 24
Peak memory 337848 kb
Host smart-197b3ec9-7aed-4289-8140-9ca531eb0513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580075215 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2580075215
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.869606237
Short name T618
Test name
Test status
Simulation time 29530143505 ps
CPU time 1994.44 seconds
Started Jul 12 04:46:33 PM PDT 24
Finished Jul 12 05:19:48 PM PDT 24
Peak memory 286932 kb
Host smart-7a7217f9-f6e3-4bd7-af76-2d1499ea9d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869606237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.869606237
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4101483586
Short name T357
Test name
Test status
Simulation time 2481171676 ps
CPU time 131.57 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 04:48:48 PM PDT 24
Peak memory 257444 kb
Host smart-1a73c48b-b82d-4010-a421-1b56dac62019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41014
83586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4101483586
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3089653764
Short name T422
Test name
Test status
Simulation time 1750600543 ps
CPU time 42.43 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 04:47:20 PM PDT 24
Peak memory 249152 kb
Host smart-0dbc7589-48a6-4573-8d65-b7cb6fcd9874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30896
53764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3089653764
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.890351471
Short name T27
Test name
Test status
Simulation time 30675244910 ps
CPU time 1662.05 seconds
Started Jul 12 04:46:31 PM PDT 24
Finished Jul 12 05:14:14 PM PDT 24
Peak memory 273688 kb
Host smart-64d86331-8e9d-41c9-aac1-c90ef99c0511
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890351471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.890351471
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.806355048
Short name T304
Test name
Test status
Simulation time 6398821292 ps
CPU time 265.26 seconds
Started Jul 12 04:46:30 PM PDT 24
Finished Jul 12 04:50:57 PM PDT 24
Peak memory 249276 kb
Host smart-f61f4a49-668e-4e9f-9d92-119f27c6ffdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806355048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.806355048
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1642211205
Short name T647
Test name
Test status
Simulation time 5184179479 ps
CPU time 45.69 seconds
Started Jul 12 04:46:31 PM PDT 24
Finished Jul 12 04:47:18 PM PDT 24
Peak memory 256976 kb
Host smart-a9e67784-7cfe-49bc-a218-644bf8b809d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
11205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1642211205
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2211824155
Short name T668
Test name
Test status
Simulation time 842934441 ps
CPU time 22.49 seconds
Started Jul 12 04:46:30 PM PDT 24
Finished Jul 12 04:46:54 PM PDT 24
Peak memory 248744 kb
Host smart-424303ee-5430-4575-bfa7-06b60a373440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22118
24155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2211824155
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3978180497
Short name T249
Test name
Test status
Simulation time 133530218 ps
CPU time 11.37 seconds
Started Jul 12 04:46:31 PM PDT 24
Finished Jul 12 04:46:44 PM PDT 24
Peak memory 254384 kb
Host smart-4b9604bb-b51c-42a8-90ee-89e6d767e0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781
80497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3978180497
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3851480133
Short name T577
Test name
Test status
Simulation time 909431914 ps
CPU time 56.01 seconds
Started Jul 12 04:46:32 PM PDT 24
Finished Jul 12 04:47:29 PM PDT 24
Peak memory 256468 kb
Host smart-d8c21857-fbe6-4cba-895d-8d4cbf5cc914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514
80133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3851480133
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1515267297
Short name T599
Test name
Test status
Simulation time 855979226 ps
CPU time 16.35 seconds
Started Jul 12 04:46:40 PM PDT 24
Finished Jul 12 04:46:57 PM PDT 24
Peak memory 255576 kb
Host smart-4e690f4e-82eb-4447-b129-dffca1df240c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515267297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1515267297
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1695548516
Short name T58
Test name
Test status
Simulation time 71733173184 ps
CPU time 4971.41 seconds
Started Jul 12 04:47:07 PM PDT 24
Finished Jul 12 06:09:59 PM PDT 24
Peak memory 316212 kb
Host smart-6d9b7ed9-caae-4f81-af30-c587f6dc1e17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695548516 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1695548516
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2616597223
Short name T617
Test name
Test status
Simulation time 30497832741 ps
CPU time 2238.07 seconds
Started Jul 12 04:46:38 PM PDT 24
Finished Jul 12 05:23:57 PM PDT 24
Peak memory 282020 kb
Host smart-cf960da8-39d6-419e-b8c3-d253f53f2603
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616597223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2616597223
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3875230189
Short name T455
Test name
Test status
Simulation time 1727233059 ps
CPU time 146.12 seconds
Started Jul 12 04:46:37 PM PDT 24
Finished Jul 12 04:49:04 PM PDT 24
Peak memory 256976 kb
Host smart-899cb8f6-85c7-4a94-8ffe-35a7a6634331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38752
30189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3875230189
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2997486181
Short name T360
Test name
Test status
Simulation time 10359696474 ps
CPU time 48.53 seconds
Started Jul 12 04:46:35 PM PDT 24
Finished Jul 12 04:47:24 PM PDT 24
Peak memory 257392 kb
Host smart-217c1f3f-5cdf-4ea4-8342-500e8bf26ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29974
86181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2997486181
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3302327471
Short name T317
Test name
Test status
Simulation time 132705976071 ps
CPU time 2156.5 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 05:22:34 PM PDT 24
Peak memory 290356 kb
Host smart-8cbfa033-6aa7-4a61-923b-1c6f30da68cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302327471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3302327471
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4122777932
Short name T219
Test name
Test status
Simulation time 353961348620 ps
CPU time 2222.04 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 05:23:39 PM PDT 24
Peak memory 282940 kb
Host smart-1df2c3d1-d2d1-427e-b22a-77fe7742df1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122777932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4122777932
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.690399573
Short name T299
Test name
Test status
Simulation time 9818647107 ps
CPU time 411.44 seconds
Started Jul 12 04:46:35 PM PDT 24
Finished Jul 12 04:53:28 PM PDT 24
Peak memory 249280 kb
Host smart-ad140503-0aa9-4fdc-8c0e-321c42b0dcaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690399573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.690399573
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4044507080
Short name T606
Test name
Test status
Simulation time 2048452349 ps
CPU time 33.93 seconds
Started Jul 12 04:46:33 PM PDT 24
Finished Jul 12 04:47:07 PM PDT 24
Peak memory 256632 kb
Host smart-d7e35344-f86e-4a88-8683-2eb57a816d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
07080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4044507080
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3155152977
Short name T707
Test name
Test status
Simulation time 3214659314 ps
CPU time 63.51 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 04:47:41 PM PDT 24
Peak memory 257424 kb
Host smart-77b4225b-4428-4c9d-bf18-909f48627aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31551
52977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3155152977
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.505492470
Short name T389
Test name
Test status
Simulation time 1625079140 ps
CPU time 23.22 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 04:47:00 PM PDT 24
Peak memory 248656 kb
Host smart-98b36fcd-77d4-4428-846c-a17aac681491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50549
2470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.505492470
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2974585312
Short name T700
Test name
Test status
Simulation time 370636864 ps
CPU time 31.12 seconds
Started Jul 12 04:46:30 PM PDT 24
Finished Jul 12 04:47:02 PM PDT 24
Peak memory 256404 kb
Host smart-cd615eea-956a-42af-89fe-22889cc6b19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
85312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2974585312
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.512549626
Short name T545
Test name
Test status
Simulation time 11374654681 ps
CPU time 1121.82 seconds
Started Jul 12 04:46:37 PM PDT 24
Finished Jul 12 05:05:20 PM PDT 24
Peak memory 289284 kb
Host smart-ec6f5fb4-1c29-45e2-aa8d-b3f44836ae76
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512549626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.512549626
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1004662886
Short name T450
Test name
Test status
Simulation time 101595100880 ps
CPU time 2724.02 seconds
Started Jul 12 04:46:36 PM PDT 24
Finished Jul 12 05:32:01 PM PDT 24
Peak memory 316412 kb
Host smart-6a3d5944-3153-4a7e-853b-ddf9fe26c211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004662886 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1004662886
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3743376857
Short name T101
Test name
Test status
Simulation time 30926519233 ps
CPU time 1564.35 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 05:12:51 PM PDT 24
Peak memory 290072 kb
Host smart-674c020d-a390-4291-88bb-e201e651932f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743376857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3743376857
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3195895031
Short name T613
Test name
Test status
Simulation time 686311164 ps
CPU time 39 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 04:47:23 PM PDT 24
Peak memory 256880 kb
Host smart-0b5f2f03-0d3b-497a-9b16-bb2549104a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31958
95031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3195895031
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3248314614
Short name T429
Test name
Test status
Simulation time 504627705 ps
CPU time 27.44 seconds
Started Jul 12 04:46:42 PM PDT 24
Finished Jul 12 04:47:11 PM PDT 24
Peak memory 248932 kb
Host smart-cc57211f-fc16-494e-96b0-5653383d2fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32483
14614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3248314614
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2751101602
Short name T322
Test name
Test status
Simulation time 17532076928 ps
CPU time 1397.85 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 05:10:01 PM PDT 24
Peak memory 289572 kb
Host smart-235a557d-5937-4b07-bd1a-66f1138daee0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751101602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2751101602
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2029334860
Short name T464
Test name
Test status
Simulation time 39683942841 ps
CPU time 2157.85 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 282028 kb
Host smart-082c2e2d-1728-4450-8eef-c9c458da2db6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029334860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2029334860
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3262774447
Short name T288
Test name
Test status
Simulation time 9946003148 ps
CPU time 370.65 seconds
Started Jul 12 04:46:47 PM PDT 24
Finished Jul 12 04:52:58 PM PDT 24
Peak memory 249368 kb
Host smart-3106e640-c16b-43f9-ae84-b5fb0daa733a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262774447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3262774447
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.791349047
Short name T451
Test name
Test status
Simulation time 239087193 ps
CPU time 9.12 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 04:46:54 PM PDT 24
Peak memory 249152 kb
Host smart-3ac412d5-eede-4756-a62d-e832a54b56a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79134
9047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.791349047
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.291354402
Short name T544
Test name
Test status
Simulation time 782001681 ps
CPU time 20.03 seconds
Started Jul 12 04:46:42 PM PDT 24
Finished Jul 12 04:47:03 PM PDT 24
Peak memory 256476 kb
Host smart-d997631f-1438-46b4-9f99-203d4817da54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29135
4402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.291354402
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3902571461
Short name T423
Test name
Test status
Simulation time 360848882 ps
CPU time 25.39 seconds
Started Jul 12 04:46:45 PM PDT 24
Finished Jul 12 04:47:11 PM PDT 24
Peak memory 256720 kb
Host smart-a9a2db04-b7c9-42cd-9231-18b87a9c3c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39025
71461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3902571461
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.64436141
Short name T401
Test name
Test status
Simulation time 264468303 ps
CPU time 17.2 seconds
Started Jul 12 04:46:42 PM PDT 24
Finished Jul 12 04:47:00 PM PDT 24
Peak memory 256320 kb
Host smart-af6939da-f121-4d49-8981-080fbfbe76ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64436
141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.64436141
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3449873029
Short name T686
Test name
Test status
Simulation time 30396101220 ps
CPU time 1794.59 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 05:16:39 PM PDT 24
Peak memory 290012 kb
Host smart-61a1af98-d93f-4ace-be55-746922d4be54
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449873029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3449873029
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2281988285
Short name T691
Test name
Test status
Simulation time 53711788068 ps
CPU time 785.38 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 04:59:52 PM PDT 24
Peak memory 273384 kb
Host smart-f25953d0-86b6-40f2-b516-0736e7186c1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281988285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2281988285
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2742848700
Short name T587
Test name
Test status
Simulation time 8814158918 ps
CPU time 133.12 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 04:48:57 PM PDT 24
Peak memory 257492 kb
Host smart-bb3806be-c371-4678-8286-9adb89b3834f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27428
48700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2742848700
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1252468746
Short name T79
Test name
Test status
Simulation time 3606591054 ps
CPU time 52.49 seconds
Started Jul 12 04:46:44 PM PDT 24
Finished Jul 12 04:47:37 PM PDT 24
Peak memory 257060 kb
Host smart-225b243a-9029-4515-aef8-6d471ee82e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12524
68746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1252468746
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3287732417
Short name T106
Test name
Test status
Simulation time 127849388864 ps
CPU time 1732.88 seconds
Started Jul 12 04:46:50 PM PDT 24
Finished Jul 12 05:15:44 PM PDT 24
Peak memory 273748 kb
Host smart-d0d18298-3499-45f5-b654-22258e64150e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287732417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3287732417
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.686309375
Short name T292
Test name
Test status
Simulation time 15785697712 ps
CPU time 330.76 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 04:52:17 PM PDT 24
Peak memory 249308 kb
Host smart-602e8de7-12ef-47ff-908b-b12392b9ce1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686309375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.686309375
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2115533397
Short name T650
Test name
Test status
Simulation time 779854329 ps
CPU time 42.8 seconds
Started Jul 12 04:46:44 PM PDT 24
Finished Jul 12 04:47:28 PM PDT 24
Peak memory 256808 kb
Host smart-7a83fd5a-24b4-40ae-ba36-dc3d041ff330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155
33397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2115533397
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1897194841
Short name T665
Test name
Test status
Simulation time 1351851302 ps
CPU time 22.36 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 04:47:07 PM PDT 24
Peak memory 255692 kb
Host smart-d115c784-603e-47be-a090-7d757d850c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18971
94841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1897194841
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1026904796
Short name T252
Test name
Test status
Simulation time 2024959936 ps
CPU time 24.53 seconds
Started Jul 12 04:46:46 PM PDT 24
Finished Jul 12 04:47:10 PM PDT 24
Peak memory 255136 kb
Host smart-8fba6de7-6f38-44ca-a689-d552cbe19fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10269
04796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1026904796
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3104921341
Short name T413
Test name
Test status
Simulation time 1137870504 ps
CPU time 17.5 seconds
Started Jul 12 04:46:43 PM PDT 24
Finished Jul 12 04:47:01 PM PDT 24
Peak memory 256812 kb
Host smart-047b05a6-304d-4557-97e1-1031aae1d864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31049
21341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3104921341
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4287320340
Short name T461
Test name
Test status
Simulation time 38805628529 ps
CPU time 970.96 seconds
Started Jul 12 04:46:50 PM PDT 24
Finished Jul 12 05:03:02 PM PDT 24
Peak memory 290376 kb
Host smart-49cd5841-f4d6-4ec6-84be-7af1eb7fdcdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287320340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4287320340
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3082244384
Short name T210
Test name
Test status
Simulation time 105221638 ps
CPU time 3.05 seconds
Started Jul 12 04:45:10 PM PDT 24
Finished Jul 12 04:45:15 PM PDT 24
Peak memory 249564 kb
Host smart-8d59ef5a-bee6-4810-8f9d-6ab2381ed739
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3082244384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3082244384
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.710267859
Short name T89
Test name
Test status
Simulation time 39761148114 ps
CPU time 2140.91 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 05:20:55 PM PDT 24
Peak memory 273372 kb
Host smart-4c9690d3-4980-46b7-bc55-24a01d4b20ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710267859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.710267859
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1119436498
Short name T534
Test name
Test status
Simulation time 295073350 ps
CPU time 14.99 seconds
Started Jul 12 04:45:10 PM PDT 24
Finished Jul 12 04:45:26 PM PDT 24
Peak memory 249260 kb
Host smart-47f9bad0-e790-4bb1-92e7-cefe368b7063
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1119436498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1119436498
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.152962478
Short name T646
Test name
Test status
Simulation time 5456378942 ps
CPU time 155.25 seconds
Started Jul 12 04:45:13 PM PDT 24
Finished Jul 12 04:47:50 PM PDT 24
Peak memory 257492 kb
Host smart-531fcda8-3265-4526-a7ec-14c4eb302966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
2478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.152962478
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3040682011
Short name T655
Test name
Test status
Simulation time 3207312286 ps
CPU time 52.12 seconds
Started Jul 12 04:45:14 PM PDT 24
Finished Jul 12 04:46:08 PM PDT 24
Peak memory 249256 kb
Host smart-a8b97a57-0f9c-4c56-a177-852ff5d07f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
82011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3040682011
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.112080830
Short name T269
Test name
Test status
Simulation time 123411153713 ps
CPU time 1818.78 seconds
Started Jul 12 04:45:13 PM PDT 24
Finished Jul 12 05:15:33 PM PDT 24
Peak memory 273216 kb
Host smart-d6e3b970-b684-499a-91f8-a57412675265
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112080830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.112080830
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3963180577
Short name T653
Test name
Test status
Simulation time 17928676567 ps
CPU time 1188.35 seconds
Started Jul 12 04:45:22 PM PDT 24
Finished Jul 12 05:05:11 PM PDT 24
Peak memory 273896 kb
Host smart-16319235-edfc-4dad-972e-b70fe4fb64ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963180577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3963180577
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3239445451
Short name T635
Test name
Test status
Simulation time 32269882440 ps
CPU time 306.44 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 04:50:18 PM PDT 24
Peak memory 257136 kb
Host smart-554aea4e-864a-4587-a8bb-3599ab282cb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239445451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3239445451
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2508478421
Short name T99
Test name
Test status
Simulation time 1131860888 ps
CPU time 22.69 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 04:45:37 PM PDT 24
Peak memory 256692 kb
Host smart-906c4e07-1c2c-4bad-a781-0ab7e4f36d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
78421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2508478421
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4167703892
Short name T581
Test name
Test status
Simulation time 507362244 ps
CPU time 16.9 seconds
Started Jul 12 04:45:14 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 248496 kb
Host smart-f65ea534-b9fa-4250-ba82-a911b21c27af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41677
03892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4167703892
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1091867378
Short name T253
Test name
Test status
Simulation time 653325538 ps
CPU time 39.84 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 04:45:53 PM PDT 24
Peak memory 249184 kb
Host smart-880dcb79-0b6d-42b5-b496-571972388832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918
67378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1091867378
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3890291883
Short name T356
Test name
Test status
Simulation time 54705456 ps
CPU time 6.72 seconds
Started Jul 12 04:45:17 PM PDT 24
Finished Jul 12 04:45:25 PM PDT 24
Peak memory 249436 kb
Host smart-3b98ef40-328d-471b-aafe-8ddd86d4f055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
91883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3890291883
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.530356123
Short name T246
Test name
Test status
Simulation time 65784439779 ps
CPU time 3468.06 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 05:43:01 PM PDT 24
Peak memory 298460 kb
Host smart-74613edd-96b5-4099-bee1-5453c749e1f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530356123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.530356123
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.938752549
Short name T174
Test name
Test status
Simulation time 738283245207 ps
CPU time 2597.9 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 05:28:30 PM PDT 24
Peak memory 286536 kb
Host smart-799c26c3-2147-486c-adc7-f3edb46b5cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938752549 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.938752549
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4235473178
Short name T682
Test name
Test status
Simulation time 233262649744 ps
CPU time 2300.82 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 05:25:17 PM PDT 24
Peak memory 287832 kb
Host smart-bb96f0c1-373d-4f82-a215-ddcc71f8fac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235473178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4235473178
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.270357519
Short name T525
Test name
Test status
Simulation time 1217569232 ps
CPU time 75.3 seconds
Started Jul 12 04:46:48 PM PDT 24
Finished Jul 12 04:48:04 PM PDT 24
Peak memory 256924 kb
Host smart-4ac99837-623b-488b-9189-9325b53009d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27035
7519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.270357519
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.235416553
Short name T527
Test name
Test status
Simulation time 111797513 ps
CPU time 14.28 seconds
Started Jul 12 04:46:49 PM PDT 24
Finished Jul 12 04:47:04 PM PDT 24
Peak memory 255596 kb
Host smart-0e7e1695-e4a2-447a-b93a-538dd563c306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
6553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.235416553
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.651614975
Short name T328
Test name
Test status
Simulation time 536165246202 ps
CPU time 2763.03 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 05:33:01 PM PDT 24
Peak memory 282088 kb
Host smart-3aee7142-89fb-4510-8cb6-83d73ce02261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651614975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.651614975
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3284107411
Short name T588
Test name
Test status
Simulation time 29307615893 ps
CPU time 1517.18 seconds
Started Jul 12 04:46:47 PM PDT 24
Finished Jul 12 05:12:05 PM PDT 24
Peak memory 273976 kb
Host smart-fe469830-2900-48b9-853b-197b765f3c9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284107411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3284107411
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3319673463
Short name T696
Test name
Test status
Simulation time 9028358833 ps
CPU time 333.92 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:52:31 PM PDT 24
Peak memory 255936 kb
Host smart-beaf4cca-6a53-4de7-89e2-7b15da0e6982
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319673463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3319673463
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1911703883
Short name T178
Test name
Test status
Simulation time 2175085887 ps
CPU time 31.81 seconds
Started Jul 12 04:46:50 PM PDT 24
Finished Jul 12 04:47:23 PM PDT 24
Peak memory 256660 kb
Host smart-5196d362-5e16-4faa-b28c-5aa447ffede1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
03883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1911703883
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1935898627
Short name T602
Test name
Test status
Simulation time 3229004186 ps
CPU time 50.63 seconds
Started Jul 12 04:46:48 PM PDT 24
Finished Jul 12 04:47:40 PM PDT 24
Peak memory 248900 kb
Host smart-ba863dcc-1a95-4bae-b858-160a25662379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19358
98627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1935898627
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.351651984
Short name T67
Test name
Test status
Simulation time 794693066 ps
CPU time 58.94 seconds
Started Jul 12 04:46:53 PM PDT 24
Finished Jul 12 04:47:53 PM PDT 24
Peak memory 257108 kb
Host smart-1cc44ccd-2e09-455b-acce-3888f7e810a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35165
1984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.351651984
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4167735308
Short name T465
Test name
Test status
Simulation time 359901564 ps
CPU time 29.49 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:47:26 PM PDT 24
Peak memory 257336 kb
Host smart-1e152cf1-ec4c-4657-87fa-0226cfb56a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41677
35308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4167735308
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2812320520
Short name T704
Test name
Test status
Simulation time 39683848473 ps
CPU time 2278.7 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 05:24:55 PM PDT 24
Peak memory 290132 kb
Host smart-e6b8dc0e-82c5-4a33-a89e-1d1f6e9c29b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812320520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2812320520
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1541684580
Short name T420
Test name
Test status
Simulation time 37440328792 ps
CPU time 1212.66 seconds
Started Jul 12 04:46:56 PM PDT 24
Finished Jul 12 05:07:12 PM PDT 24
Peak memory 285300 kb
Host smart-426e287a-b268-4aa7-bb2b-42d43af1c8cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541684580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1541684580
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2316358394
Short name T476
Test name
Test status
Simulation time 2486942540 ps
CPU time 139.33 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 04:49:18 PM PDT 24
Peak memory 257576 kb
Host smart-a3df9152-bd52-4765-9fd4-dba9d1e6fd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
58394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2316358394
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1646787
Short name T428
Test name
Test status
Simulation time 85116851 ps
CPU time 4.93 seconds
Started Jul 12 04:46:53 PM PDT 24
Finished Jul 12 04:47:00 PM PDT 24
Peak memory 249220 kb
Host smart-5674a4c6-862d-40bb-a48e-7a9f42a4f24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467
87 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1646787
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3680445431
Short name T666
Test name
Test status
Simulation time 42995078595 ps
CPU time 2311.69 seconds
Started Jul 12 04:46:58 PM PDT 24
Finished Jul 12 05:25:32 PM PDT 24
Peak memory 284552 kb
Host smart-88f1cc6f-6dfc-469d-b81a-58739e1ac931
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680445431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3680445431
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3994563858
Short name T102
Test name
Test status
Simulation time 166490072789 ps
CPU time 2579.76 seconds
Started Jul 12 04:47:02 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 290264 kb
Host smart-7ad38031-f47f-476d-b188-5e137853d438
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994563858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3994563858
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.693945063
Short name T287
Test name
Test status
Simulation time 10070060594 ps
CPU time 396.84 seconds
Started Jul 12 04:46:56 PM PDT 24
Finished Jul 12 04:53:35 PM PDT 24
Peak memory 249256 kb
Host smart-2f0cabc9-72cf-4b02-ab17-600b26430088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693945063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.693945063
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3147655370
Short name T669
Test name
Test status
Simulation time 1392997320 ps
CPU time 12.06 seconds
Started Jul 12 04:46:50 PM PDT 24
Finished Jul 12 04:47:03 PM PDT 24
Peak memory 249208 kb
Host smart-8d845efa-f36d-439b-9333-025248def126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31476
55370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3147655370
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2414829580
Short name T196
Test name
Test status
Simulation time 127502739 ps
CPU time 9.27 seconds
Started Jul 12 04:46:49 PM PDT 24
Finished Jul 12 04:47:00 PM PDT 24
Peak memory 248656 kb
Host smart-a97f3f12-079b-4da1-af67-c2ed735fda55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
29580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2414829580
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3469158921
Short name T248
Test name
Test status
Simulation time 2046800916 ps
CPU time 70.54 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:48:06 PM PDT 24
Peak memory 256476 kb
Host smart-a29fd017-18b2-4a00-8344-14ce1aa84570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34691
58921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3469158921
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4247760560
Short name T437
Test name
Test status
Simulation time 1778086990 ps
CPU time 30.43 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:47:27 PM PDT 24
Peak memory 256548 kb
Host smart-ac1ab378-1fa9-44a2-9d62-2951ea913f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
60560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4247760560
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.4048208760
Short name T110
Test name
Test status
Simulation time 205011653445 ps
CPU time 2880.67 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 05:34:59 PM PDT 24
Peak memory 290108 kb
Host smart-e0f4c3b4-f6c3-4030-b560-2cb9b00e975d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048208760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.4048208760
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1648575601
Short name T608
Test name
Test status
Simulation time 35076628697 ps
CPU time 1169.39 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 05:06:27 PM PDT 24
Peak memory 288940 kb
Host smart-ceb3e008-1943-4ff4-9b65-eec7b42a88f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648575601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1648575601
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2121251475
Short name T259
Test name
Test status
Simulation time 7260772878 ps
CPU time 148.1 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:49:25 PM PDT 24
Peak memory 257476 kb
Host smart-be029548-8f49-4aa2-9034-ffc3468914ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21212
51475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2121251475
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2203257059
Short name T412
Test name
Test status
Simulation time 1484831114 ps
CPU time 24.61 seconds
Started Jul 12 04:46:58 PM PDT 24
Finished Jul 12 04:47:25 PM PDT 24
Peak memory 249068 kb
Host smart-b8486be4-abf0-4151-8365-22aaf5477903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22032
57059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2203257059
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1403641992
Short name T314
Test name
Test status
Simulation time 61445986757 ps
CPU time 1405.21 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 05:10:23 PM PDT 24
Peak memory 288028 kb
Host smart-ff9f0855-57c9-4770-ab40-2ef131e64e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403641992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1403641992
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1650645861
Short name T417
Test name
Test status
Simulation time 85716027270 ps
CPU time 2020.47 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 05:20:38 PM PDT 24
Peak memory 282052 kb
Host smart-ee36a739-cae1-49ed-b4c8-9563e32d7952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650645861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1650645861
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1488324640
Short name T305
Test name
Test status
Simulation time 32535142410 ps
CPU time 349.84 seconds
Started Jul 12 04:46:54 PM PDT 24
Finished Jul 12 04:52:46 PM PDT 24
Peak memory 256248 kb
Host smart-9ef81483-f609-400f-80fa-4af399116f2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488324640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1488324640
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4011816710
Short name T408
Test name
Test status
Simulation time 402736992 ps
CPU time 18.84 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 04:47:17 PM PDT 24
Peak memory 256920 kb
Host smart-de9eaba7-0ab2-4dea-85d3-0f4b7bf7a271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
16710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4011816710
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4290745129
Short name T445
Test name
Test status
Simulation time 1830063659 ps
CPU time 21.66 seconds
Started Jul 12 04:46:55 PM PDT 24
Finished Jul 12 04:47:20 PM PDT 24
Peak memory 249164 kb
Host smart-18179054-ee04-490e-82bf-cff72ad03a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42907
45129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4290745129
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.278286817
Short name T466
Test name
Test status
Simulation time 632265361 ps
CPU time 42.98 seconds
Started Jul 12 04:46:58 PM PDT 24
Finished Jul 12 04:47:43 PM PDT 24
Peak memory 248672 kb
Host smart-a2b93c3f-369b-4a8c-95ef-7cd401a56ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828
6817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.278286817
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2915643390
Short name T66
Test name
Test status
Simulation time 346642573 ps
CPU time 11.56 seconds
Started Jul 12 04:46:58 PM PDT 24
Finished Jul 12 04:47:11 PM PDT 24
Peak memory 249204 kb
Host smart-8721700c-ac30-4787-affb-567e9bee666b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29156
43390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2915643390
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.389190086
Short name T98
Test name
Test status
Simulation time 2749883394 ps
CPU time 253.16 seconds
Started Jul 12 04:46:56 PM PDT 24
Finished Jul 12 04:51:12 PM PDT 24
Peak memory 257496 kb
Host smart-1aa9911f-9f16-49c9-bd4b-aaf691226850
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389190086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.389190086
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.449841323
Short name T564
Test name
Test status
Simulation time 146304565409 ps
CPU time 2506.15 seconds
Started Jul 12 04:46:59 PM PDT 24
Finished Jul 12 05:28:47 PM PDT 24
Peak memory 284092 kb
Host smart-d2c8e145-2782-4759-86cf-2e4e6b3ff97d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449841323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.449841323
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2626428923
Short name T508
Test name
Test status
Simulation time 3875168179 ps
CPU time 222.22 seconds
Started Jul 12 04:46:59 PM PDT 24
Finished Jul 12 04:50:43 PM PDT 24
Peak memory 251416 kb
Host smart-083eea7c-dc39-4e18-b730-d18b49b2cf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
28923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2626428923
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3749922348
Short name T560
Test name
Test status
Simulation time 711478223 ps
CPU time 18.89 seconds
Started Jul 12 04:47:00 PM PDT 24
Finished Jul 12 04:47:20 PM PDT 24
Peak memory 249216 kb
Host smart-e38e8d12-98bb-498b-aed6-5a86f452acb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499
22348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3749922348
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.609232986
Short name T430
Test name
Test status
Simulation time 43879481421 ps
CPU time 997.22 seconds
Started Jul 12 04:47:02 PM PDT 24
Finished Jul 12 05:03:40 PM PDT 24
Peak memory 282176 kb
Host smart-400aa933-b38b-4709-945b-d2af34f32dbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609232986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.609232986
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1387192117
Short name T307
Test name
Test status
Simulation time 3936802411 ps
CPU time 165.35 seconds
Started Jul 12 04:46:59 PM PDT 24
Finished Jul 12 04:49:46 PM PDT 24
Peak memory 248244 kb
Host smart-4e3ac0b3-0d69-4b41-80e8-29482928ff82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387192117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1387192117
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.502240502
Short name T689
Test name
Test status
Simulation time 789743970 ps
CPU time 19.56 seconds
Started Jul 12 04:47:00 PM PDT 24
Finished Jul 12 04:47:21 PM PDT 24
Peak memory 249280 kb
Host smart-af88ee09-51d7-4531-a0e8-be70e30a4035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50224
0502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.502240502
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1628241658
Short name T438
Test name
Test status
Simulation time 3074664527 ps
CPU time 38.1 seconds
Started Jul 12 04:47:03 PM PDT 24
Finished Jul 12 04:47:41 PM PDT 24
Peak memory 249420 kb
Host smart-f8923fbb-ae7b-47d3-818a-a446c3795ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16282
41658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1628241658
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.312155221
Short name T372
Test name
Test status
Simulation time 3365027066 ps
CPU time 54.23 seconds
Started Jul 12 04:47:00 PM PDT 24
Finished Jul 12 04:47:56 PM PDT 24
Peak memory 256968 kb
Host smart-5c60a7d3-a7dc-497c-b2fc-8e1fb9536465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31215
5221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.312155221
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1871695091
Short name T656
Test name
Test status
Simulation time 4735048371 ps
CPU time 48.97 seconds
Started Jul 12 04:47:05 PM PDT 24
Finished Jul 12 04:47:54 PM PDT 24
Peak memory 249724 kb
Host smart-8d061de9-c514-43a9-8fca-e2f52fe7de3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
95091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1871695091
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3177180117
Short name T275
Test name
Test status
Simulation time 32182467166 ps
CPU time 919.26 seconds
Started Jul 12 04:47:00 PM PDT 24
Finished Jul 12 05:02:21 PM PDT 24
Peak memory 286244 kb
Host smart-f014a2fa-33c7-45b3-aaa2-1a2f5ec6e430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177180117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3177180117
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2459629466
Short name T173
Test name
Test status
Simulation time 168291150050 ps
CPU time 3050.28 seconds
Started Jul 12 04:47:11 PM PDT 24
Finished Jul 12 05:38:02 PM PDT 24
Peak memory 305788 kb
Host smart-6476f4bc-b280-48a3-94ff-59725e0959e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459629466 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2459629466
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3653026796
Short name T375
Test name
Test status
Simulation time 29645246362 ps
CPU time 1043.27 seconds
Started Jul 12 04:47:05 PM PDT 24
Finished Jul 12 05:04:29 PM PDT 24
Peak memory 282080 kb
Host smart-5f822628-7d59-4756-b11e-eefcf318e44c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653026796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3653026796
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.4011895632
Short name T177
Test name
Test status
Simulation time 7724432659 ps
CPU time 172.04 seconds
Started Jul 12 04:47:06 PM PDT 24
Finished Jul 12 04:49:59 PM PDT 24
Peak memory 257560 kb
Host smart-4364c0b9-ee90-4b13-84c0-9895f8c2268a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
95632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4011895632
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1519187869
Short name T459
Test name
Test status
Simulation time 1439280972 ps
CPU time 68.15 seconds
Started Jul 12 04:47:06 PM PDT 24
Finished Jul 12 04:48:15 PM PDT 24
Peak memory 249204 kb
Host smart-a9de9dae-96e4-4a87-ae64-92a614a6e50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191
87869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1519187869
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1953246538
Short name T329
Test name
Test status
Simulation time 69235244140 ps
CPU time 1992.42 seconds
Started Jul 12 04:47:06 PM PDT 24
Finished Jul 12 05:20:19 PM PDT 24
Peak memory 273152 kb
Host smart-6967fd4a-c843-4c24-9820-5d85f8c396c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953246538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1953246538
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2712393872
Short name T310
Test name
Test status
Simulation time 19755103996 ps
CPU time 439.43 seconds
Started Jul 12 04:47:08 PM PDT 24
Finished Jul 12 04:54:28 PM PDT 24
Peak memory 255644 kb
Host smart-297eb9f2-a9ee-4712-bf9c-e5b6bb074fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712393872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2712393872
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2096734442
Short name T603
Test name
Test status
Simulation time 3599632215 ps
CPU time 54.84 seconds
Started Jul 12 04:47:01 PM PDT 24
Finished Jul 12 04:47:57 PM PDT 24
Peak memory 249320 kb
Host smart-8680f638-dd8a-4a30-9ec8-554d5b7932d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20967
34442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2096734442
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3566572427
Short name T96
Test name
Test status
Simulation time 1097409454 ps
CPU time 60.59 seconds
Started Jul 12 04:47:01 PM PDT 24
Finished Jul 12 04:48:02 PM PDT 24
Peak memory 256688 kb
Host smart-a84de96f-c02b-42a9-9624-aaa68f55fe2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35665
72427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3566572427
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2084817799
Short name T693
Test name
Test status
Simulation time 822457439 ps
CPU time 58.03 seconds
Started Jul 12 04:47:08 PM PDT 24
Finished Jul 12 04:48:07 PM PDT 24
Peak memory 257352 kb
Host smart-09b49a7a-3721-4a12-8739-9b9cf01d2023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20848
17799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2084817799
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.17990848
Short name T354
Test name
Test status
Simulation time 298904281 ps
CPU time 24.47 seconds
Started Jul 12 04:47:05 PM PDT 24
Finished Jul 12 04:47:30 PM PDT 24
Peak memory 256148 kb
Host smart-5645e994-f153-4bb6-87d6-a9322fffa248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17990
848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.17990848
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2016228894
Short name T43
Test name
Test status
Simulation time 239576137019 ps
CPU time 3436.96 seconds
Started Jul 12 04:47:09 PM PDT 24
Finished Jul 12 05:44:27 PM PDT 24
Peak memory 289536 kb
Host smart-d212ffb3-63ac-47ee-9e52-d9bf61a4b8fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016228894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2016228894
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3712345899
Short name T227
Test name
Test status
Simulation time 5261223975 ps
CPU time 98.25 seconds
Started Jul 12 04:47:07 PM PDT 24
Finished Jul 12 04:48:46 PM PDT 24
Peak memory 257108 kb
Host smart-e0c5dcc3-7df2-48c9-97af-07ac86cf51f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37123
45899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3712345899
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3077736282
Short name T403
Test name
Test status
Simulation time 1826871998 ps
CPU time 17.09 seconds
Started Jul 12 04:47:07 PM PDT 24
Finished Jul 12 04:47:25 PM PDT 24
Peak memory 253964 kb
Host smart-5f3f2147-8445-4f08-b344-a595f82807ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
36282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3077736282
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2442875765
Short name T318
Test name
Test status
Simulation time 12446093855 ps
CPU time 1173.86 seconds
Started Jul 12 04:47:08 PM PDT 24
Finished Jul 12 05:06:43 PM PDT 24
Peak memory 290240 kb
Host smart-e8abe1d1-2d14-414b-88fa-8bb9288772dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442875765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2442875765
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.901549018
Short name T688
Test name
Test status
Simulation time 170622681554 ps
CPU time 2678.57 seconds
Started Jul 12 04:47:10 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 287272 kb
Host smart-335fabc5-2115-4413-8dbe-fae93bc93cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901549018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.901549018
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.4224427850
Short name T474
Test name
Test status
Simulation time 22635688014 ps
CPU time 102.36 seconds
Started Jul 12 04:47:08 PM PDT 24
Finished Jul 12 04:48:51 PM PDT 24
Peak memory 253900 kb
Host smart-afe0e104-77b2-4296-87c4-2ed0023fe617
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224427850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4224427850
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1503033768
Short name T391
Test name
Test status
Simulation time 691625308 ps
CPU time 29.31 seconds
Started Jul 12 04:47:05 PM PDT 24
Finished Jul 12 04:47:35 PM PDT 24
Peak memory 257032 kb
Host smart-309f0cc3-9b66-4fd2-a25f-5e647f0d06f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
33768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1503033768
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1796462147
Short name T400
Test name
Test status
Simulation time 564041991 ps
CPU time 32.95 seconds
Started Jul 12 04:47:06 PM PDT 24
Finished Jul 12 04:47:40 PM PDT 24
Peak memory 249280 kb
Host smart-64a8325e-9809-441f-830f-098b7f132230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17964
62147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1796462147
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1703244227
Short name T193
Test name
Test status
Simulation time 1214889392 ps
CPU time 41.43 seconds
Started Jul 12 04:47:06 PM PDT 24
Finished Jul 12 04:47:48 PM PDT 24
Peak memory 248956 kb
Host smart-a46c69ce-b260-4387-95ac-1919f60b90cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17032
44227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1703244227
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1864995821
Short name T645
Test name
Test status
Simulation time 9795058621 ps
CPU time 40.31 seconds
Started Jul 12 04:47:05 PM PDT 24
Finished Jul 12 04:47:46 PM PDT 24
Peak memory 257220 kb
Host smart-e60e2bfa-7a21-4564-9b73-488646142d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
95821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1864995821
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1219055831
Short name T197
Test name
Test status
Simulation time 11002430614 ps
CPU time 1376.44 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 05:10:12 PM PDT 24
Peak memory 289972 kb
Host smart-e576035c-f9a9-49c2-adec-0100072dc95a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219055831 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1219055831
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.592885700
Short name T368
Test name
Test status
Simulation time 28700419272 ps
CPU time 1634.85 seconds
Started Jul 12 04:47:13 PM PDT 24
Finished Jul 12 05:14:29 PM PDT 24
Peak memory 273768 kb
Host smart-26b78891-f371-47f8-895b-59989d206ba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592885700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.592885700
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.584685430
Short name T419
Test name
Test status
Simulation time 2957676184 ps
CPU time 97.41 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 04:48:53 PM PDT 24
Peak memory 257576 kb
Host smart-b30c6bef-c156-40db-9dbe-64d21115631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58468
5430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.584685430
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1830576356
Short name T72
Test name
Test status
Simulation time 126696790 ps
CPU time 8.16 seconds
Started Jul 12 04:47:13 PM PDT 24
Finished Jul 12 04:47:22 PM PDT 24
Peak memory 249220 kb
Host smart-c921c3f0-c70e-438b-8abe-1505b555bb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18305
76356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1830576356
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1891481806
Short name T274
Test name
Test status
Simulation time 27746053082 ps
CPU time 1538.3 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 05:12:54 PM PDT 24
Peak memory 273304 kb
Host smart-8008c44f-ca5d-439f-bc14-014b2da8754b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891481806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1891481806
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.255635898
Short name T506
Test name
Test status
Simulation time 18345305846 ps
CPU time 1549.8 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 05:13:05 PM PDT 24
Peak memory 290340 kb
Host smart-ceb2197b-a12d-47c1-a260-3cca1f09ed7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255635898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.255635898
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.865561736
Short name T5
Test name
Test status
Simulation time 14178900508 ps
CPU time 477.41 seconds
Started Jul 12 04:47:16 PM PDT 24
Finished Jul 12 04:55:14 PM PDT 24
Peak memory 249120 kb
Host smart-3f12d362-4a48-4c77-98cb-53e762227e8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865561736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.865561736
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1536738269
Short name T516
Test name
Test status
Simulation time 1389982202 ps
CPU time 20.83 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 04:47:36 PM PDT 24
Peak memory 256640 kb
Host smart-aba2c44a-8edd-4e0a-aeb7-23a66ce020ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15367
38269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1536738269
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2616952462
Short name T556
Test name
Test status
Simulation time 2545361374 ps
CPU time 40.94 seconds
Started Jul 12 04:47:15 PM PDT 24
Finished Jul 12 04:47:57 PM PDT 24
Peak memory 248996 kb
Host smart-fc9e657e-2f9f-4389-986b-0c957d2a2c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26169
52462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2616952462
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1199749639
Short name T237
Test name
Test status
Simulation time 1933205910 ps
CPU time 55.59 seconds
Started Jul 12 04:47:15 PM PDT 24
Finished Jul 12 04:48:11 PM PDT 24
Peak memory 249168 kb
Host smart-ed90c9b4-14a5-45f0-8496-a1b5bf7d5c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997
49639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1199749639
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1104123926
Short name T540
Test name
Test status
Simulation time 82772829 ps
CPU time 10.18 seconds
Started Jul 12 04:47:14 PM PDT 24
Finished Jul 12 04:47:25 PM PDT 24
Peak memory 249148 kb
Host smart-d8e3df36-b872-48ba-b131-4e4b3f21287a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
23926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1104123926
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1467192636
Short name T53
Test name
Test status
Simulation time 15684005037 ps
CPU time 1375.71 seconds
Started Jul 12 04:47:15 PM PDT 24
Finished Jul 12 05:10:12 PM PDT 24
Peak memory 289828 kb
Host smart-ed9f2ee0-0af7-4d4c-bdc4-a04e952bb4d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467192636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1467192636
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.252223578
Short name T236
Test name
Test status
Simulation time 198585296712 ps
CPU time 4249.52 seconds
Started Jul 12 04:47:13 PM PDT 24
Finished Jul 12 05:58:04 PM PDT 24
Peak memory 306756 kb
Host smart-a2e294a8-19e2-4613-afef-27a286035435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252223578 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.252223578
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2119453051
Short name T690
Test name
Test status
Simulation time 112500129773 ps
CPU time 2426.05 seconds
Started Jul 12 04:47:20 PM PDT 24
Finished Jul 12 05:27:47 PM PDT 24
Peak memory 284208 kb
Host smart-b0d83253-ee62-4f12-8e60-811d4098a6d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119453051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2119453051
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3527256134
Short name T382
Test name
Test status
Simulation time 1509354072 ps
CPU time 29.89 seconds
Started Jul 12 04:47:20 PM PDT 24
Finished Jul 12 04:47:51 PM PDT 24
Peak memory 257392 kb
Host smart-31e552eb-a7a3-490e-9e59-a65b80addc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35272
56134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3527256134
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3570343549
Short name T590
Test name
Test status
Simulation time 95329088 ps
CPU time 10.63 seconds
Started Jul 12 04:47:19 PM PDT 24
Finished Jul 12 04:47:30 PM PDT 24
Peak memory 249072 kb
Host smart-66387fc9-ef0d-42d9-b9c1-fdc92bad7495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
43549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3570343549
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2848922740
Short name T302
Test name
Test status
Simulation time 8599462300 ps
CPU time 842.13 seconds
Started Jul 12 04:47:19 PM PDT 24
Finished Jul 12 05:01:22 PM PDT 24
Peak memory 273032 kb
Host smart-224b8c64-45bf-473b-b346-f568a35c52ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848922740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2848922740
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3727177224
Short name T638
Test name
Test status
Simulation time 24462299374 ps
CPU time 1484.35 seconds
Started Jul 12 04:47:19 PM PDT 24
Finished Jul 12 05:12:04 PM PDT 24
Peak memory 273716 kb
Host smart-d4733059-e6e6-494b-8bf1-3adddcd582ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727177224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3727177224
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2262215829
Short name T291
Test name
Test status
Simulation time 2391925534 ps
CPU time 100.33 seconds
Started Jul 12 04:47:21 PM PDT 24
Finished Jul 12 04:49:02 PM PDT 24
Peak memory 254948 kb
Host smart-8b839d9c-5b55-44fb-ae10-6db025122ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262215829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2262215829
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.799707375
Short name T350
Test name
Test status
Simulation time 1936890348 ps
CPU time 33.97 seconds
Started Jul 12 04:47:19 PM PDT 24
Finished Jul 12 04:47:54 PM PDT 24
Peak memory 257212 kb
Host smart-44ea614f-c909-4872-9fec-b3c48dbfde90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79970
7375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.799707375
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2906872693
Short name T565
Test name
Test status
Simulation time 764436480 ps
CPU time 43.67 seconds
Started Jul 12 04:47:23 PM PDT 24
Finished Jul 12 04:48:07 PM PDT 24
Peak memory 249220 kb
Host smart-0880aba9-f457-41c2-99b2-0b9f0c8fd8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
72693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2906872693
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3965129889
Short name T612
Test name
Test status
Simulation time 609761802 ps
CPU time 37.47 seconds
Started Jul 12 04:47:21 PM PDT 24
Finished Jul 12 04:47:59 PM PDT 24
Peak memory 249208 kb
Host smart-03751099-b534-4d97-9f3b-e94c8d4468fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
29889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3965129889
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1681160161
Short name T240
Test name
Test status
Simulation time 123285251901 ps
CPU time 3451.11 seconds
Started Jul 12 04:47:21 PM PDT 24
Finished Jul 12 05:44:53 PM PDT 24
Peak memory 306224 kb
Host smart-27884f44-c5d7-452f-853a-31790a94c770
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681160161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1681160161
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.230710044
Short name T84
Test name
Test status
Simulation time 28143438798 ps
CPU time 1121.47 seconds
Started Jul 12 04:47:20 PM PDT 24
Finished Jul 12 05:06:02 PM PDT 24
Peak memory 271788 kb
Host smart-1e3141e3-d452-4891-8700-6423b548f05c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230710044 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.230710044
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1274582331
Short name T462
Test name
Test status
Simulation time 25983886311 ps
CPU time 1280.53 seconds
Started Jul 12 04:47:28 PM PDT 24
Finished Jul 12 05:08:49 PM PDT 24
Peak memory 289416 kb
Host smart-f495ed94-3971-4b7d-b918-fd5004c7807e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274582331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1274582331
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2394325
Short name T452
Test name
Test status
Simulation time 1325985058 ps
CPU time 78.26 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 04:48:46 PM PDT 24
Peak memory 257188 kb
Host smart-2b2bdcd6-e3f6-43a6-8f73-72831a819193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23943
25 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2394325
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.122897931
Short name T362
Test name
Test status
Simulation time 644117201 ps
CPU time 45.81 seconds
Started Jul 12 04:47:19 PM PDT 24
Finished Jul 12 04:48:06 PM PDT 24
Peak memory 249240 kb
Host smart-6fdac526-8f40-42a9-8ae6-4e9235e0e8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12289
7931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.122897931
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.744721167
Short name T321
Test name
Test status
Simulation time 17812104943 ps
CPU time 1526.23 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 05:12:54 PM PDT 24
Peak memory 290256 kb
Host smart-00595c6b-20b3-414d-ab0f-2122bc587e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744721167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.744721167
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.735514012
Short name T103
Test name
Test status
Simulation time 64424663291 ps
CPU time 1715.72 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 05:16:04 PM PDT 24
Peak memory 273640 kb
Host smart-dcb54b29-5657-47c2-9976-509d4ec3a450
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735514012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.735514012
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3024086396
Short name T641
Test name
Test status
Simulation time 6720442002 ps
CPU time 274.02 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 04:52:02 PM PDT 24
Peak memory 249336 kb
Host smart-327eb656-9bf9-4bbc-8080-ce3e87599928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024086396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3024086396
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.464819808
Short name T502
Test name
Test status
Simulation time 1000766492 ps
CPU time 44.15 seconds
Started Jul 12 04:47:20 PM PDT 24
Finished Jul 12 04:48:05 PM PDT 24
Peak memory 249256 kb
Host smart-ca7be9fc-d594-47d2-9071-b30c0a504016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46481
9808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.464819808
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.494064574
Short name T23
Test name
Test status
Simulation time 4805793918 ps
CPU time 76.55 seconds
Started Jul 12 04:47:22 PM PDT 24
Finished Jul 12 04:48:39 PM PDT 24
Peak memory 256872 kb
Host smart-eb42431c-16fc-4ca8-bec2-628c3de3d3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49406
4574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.494064574
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2005750089
Short name T181
Test name
Test status
Simulation time 797426576 ps
CPU time 46.15 seconds
Started Jul 12 04:47:31 PM PDT 24
Finished Jul 12 04:48:18 PM PDT 24
Peak memory 256708 kb
Host smart-2358bb99-2f19-4e40-b01b-dfe6e8d5bcbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
50089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2005750089
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2414073079
Short name T708
Test name
Test status
Simulation time 1540407751 ps
CPU time 45.36 seconds
Started Jul 12 04:47:19 PM PDT 24
Finished Jul 12 04:48:05 PM PDT 24
Peak memory 256508 kb
Host smart-c57b7515-9fc2-4d46-a7c0-d84f6440455b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24140
73079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2414073079
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1001921465
Short name T42
Test name
Test status
Simulation time 69705907712 ps
CPU time 1540.47 seconds
Started Jul 12 04:47:32 PM PDT 24
Finished Jul 12 05:13:13 PM PDT 24
Peak memory 289000 kb
Host smart-ca380814-e504-4c56-a3a8-fde34a1443b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001921465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1001921465
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2678537431
Short name T512
Test name
Test status
Simulation time 10716895044 ps
CPU time 292.11 seconds
Started Jul 12 04:47:33 PM PDT 24
Finished Jul 12 04:52:26 PM PDT 24
Peak memory 257048 kb
Host smart-22c974f0-b70f-43db-ae02-dfa6d57399aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
37431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2678537431
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2918274100
Short name T687
Test name
Test status
Simulation time 1069971457 ps
CPU time 33.72 seconds
Started Jul 12 04:47:25 PM PDT 24
Finished Jul 12 04:48:00 PM PDT 24
Peak memory 249676 kb
Host smart-468ea5fb-6662-47b1-91fe-11da80af32b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
74100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2918274100
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1622411192
Short name T175
Test name
Test status
Simulation time 59388267181 ps
CPU time 1452.27 seconds
Started Jul 12 04:47:30 PM PDT 24
Finished Jul 12 05:11:43 PM PDT 24
Peak memory 286020 kb
Host smart-4c6620d5-2246-43bc-9962-0c7e2a3c0000
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622411192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1622411192
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3647711207
Short name T347
Test name
Test status
Simulation time 151443075235 ps
CPU time 2051.36 seconds
Started Jul 12 04:47:33 PM PDT 24
Finished Jul 12 05:21:46 PM PDT 24
Peak memory 273580 kb
Host smart-52cb46a1-6c10-4c12-89aa-afb0ae55a79a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647711207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3647711207
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1927170154
Short name T619
Test name
Test status
Simulation time 5534311155 ps
CPU time 242.22 seconds
Started Jul 12 04:47:31 PM PDT 24
Finished Jul 12 04:51:33 PM PDT 24
Peak memory 249348 kb
Host smart-206c4bd4-fab7-4272-b664-4d5ad183324b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927170154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1927170154
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1675281354
Short name T407
Test name
Test status
Simulation time 2517705136 ps
CPU time 33.08 seconds
Started Jul 12 04:47:29 PM PDT 24
Finished Jul 12 04:48:03 PM PDT 24
Peak memory 249336 kb
Host smart-6076a134-0c42-4d5b-8771-869dee025cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16752
81354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1675281354
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1748033436
Short name T351
Test name
Test status
Simulation time 655174995 ps
CPU time 37.28 seconds
Started Jul 12 04:47:28 PM PDT 24
Finished Jul 12 04:48:06 PM PDT 24
Peak memory 257108 kb
Host smart-3ddc1db1-73e4-46c2-82dc-8ed59436fde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
33436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1748033436
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.278735649
Short name T694
Test name
Test status
Simulation time 91147267 ps
CPU time 10.48 seconds
Started Jul 12 04:47:31 PM PDT 24
Finished Jul 12 04:47:42 PM PDT 24
Peak memory 248784 kb
Host smart-4ea57236-8e25-4e18-b877-40ab196afbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27873
5649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.278735649
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1214841136
Short name T366
Test name
Test status
Simulation time 41360674 ps
CPU time 6.08 seconds
Started Jul 12 04:47:27 PM PDT 24
Finished Jul 12 04:47:34 PM PDT 24
Peak memory 252440 kb
Host smart-c4f3fd3b-2e1e-4f62-89ff-38309dbd237a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148
41136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1214841136
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2362489028
Short name T180
Test name
Test status
Simulation time 13656629686 ps
CPU time 1169.71 seconds
Started Jul 12 04:47:32 PM PDT 24
Finished Jul 12 05:07:03 PM PDT 24
Peak memory 286748 kb
Host smart-cfbb885e-4a75-42fe-b3c1-7c302ef05852
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362489028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2362489028
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.197831452
Short name T265
Test name
Test status
Simulation time 50301377862 ps
CPU time 1482.09 seconds
Started Jul 12 04:47:33 PM PDT 24
Finished Jul 12 05:12:16 PM PDT 24
Peak memory 290164 kb
Host smart-06fad6d8-b841-46f1-b422-534a29a3e9d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197831452 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.197831452
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2945427973
Short name T201
Test name
Test status
Simulation time 54073259 ps
CPU time 3.19 seconds
Started Jul 12 04:54:27 PM PDT 24
Finished Jul 12 04:54:31 PM PDT 24
Peak memory 249496 kb
Host smart-96034694-e6eb-4a90-8ba5-d1c0bc87cbef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2945427973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2945427973
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1119610671
Short name T65
Test name
Test status
Simulation time 277288984275 ps
CPU time 1918.18 seconds
Started Jul 12 04:45:17 PM PDT 24
Finished Jul 12 05:17:17 PM PDT 24
Peak memory 273796 kb
Host smart-231f38b2-5399-4300-89ef-c91b95859375
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119610671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1119610671
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.24689410
Short name T353
Test name
Test status
Simulation time 1621449492 ps
CPU time 18.6 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 249196 kb
Host smart-c23badff-5160-405d-9e22-d13112e48d7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=24689410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.24689410
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3808822389
Short name T266
Test name
Test status
Simulation time 5596349757 ps
CPU time 85.62 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 04:46:42 PM PDT 24
Peak memory 257424 kb
Host smart-9157fe1d-a2c9-47af-be71-cc4ff32d18d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38088
22389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3808822389
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1141901476
Short name T1
Test name
Test status
Simulation time 1014293898 ps
CPU time 21.46 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 04:45:35 PM PDT 24
Peak memory 257356 kb
Host smart-9a95ce87-5df2-46d6-8266-c00e01b5bbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11419
01476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1141901476
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1872465889
Short name T620
Test name
Test status
Simulation time 45591806552 ps
CPU time 1449.99 seconds
Started Jul 12 04:45:10 PM PDT 24
Finished Jul 12 05:09:22 PM PDT 24
Peak memory 273792 kb
Host smart-eed7c0dd-fed9-42aa-838b-d2efb721c791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872465889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1872465889
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.214527431
Short name T648
Test name
Test status
Simulation time 11402192994 ps
CPU time 653.1 seconds
Started Jul 12 04:45:14 PM PDT 24
Finished Jul 12 04:56:08 PM PDT 24
Peak memory 273056 kb
Host smart-c71a425f-e32a-46a0-85ba-06069b2af9e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214527431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.214527431
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2678006063
Short name T271
Test name
Test status
Simulation time 22208331059 ps
CPU time 453.44 seconds
Started Jul 12 04:45:09 PM PDT 24
Finished Jul 12 04:52:44 PM PDT 24
Peak memory 249336 kb
Host smart-cd4c56c4-42a6-4949-8590-a07b6f0b44eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678006063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2678006063
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2897738365
Short name T526
Test name
Test status
Simulation time 1732114122 ps
CPU time 33.24 seconds
Started Jul 12 04:45:08 PM PDT 24
Finished Jul 12 04:45:43 PM PDT 24
Peak memory 257276 kb
Host smart-a7c5a86c-9661-4a04-a106-e2b41443d8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28977
38365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2897738365
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2562333800
Short name T435
Test name
Test status
Simulation time 1450144368 ps
CPU time 24.3 seconds
Started Jul 12 04:45:19 PM PDT 24
Finished Jul 12 04:45:45 PM PDT 24
Peak memory 257152 kb
Host smart-ecdc9727-e600-4089-bd06-444059744781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
33800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2562333800
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3462809513
Short name T85
Test name
Test status
Simulation time 181269123 ps
CPU time 19.17 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 256652 kb
Host smart-91a3ea37-cad5-4d7d-b221-54ec9ca00874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34628
09513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3462809513
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.306635615
Short name T433
Test name
Test status
Simulation time 536403824 ps
CPU time 32.44 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 249236 kb
Host smart-b7e93eda-72bc-412d-9668-3f23f481370d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30663
5615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.306635615
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3445642616
Short name T78
Test name
Test status
Simulation time 53086542291 ps
CPU time 289.2 seconds
Started Jul 12 04:45:11 PM PDT 24
Finished Jul 12 04:50:01 PM PDT 24
Peak memory 257500 kb
Host smart-1e5f546a-433e-49ce-8b59-bb0011442441
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445642616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3445642616
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3469299127
Short name T204
Test name
Test status
Simulation time 19857926 ps
CPU time 3 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:20 PM PDT 24
Peak memory 249344 kb
Host smart-6f230a64-4f91-40bc-8628-d41c24b998a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3469299127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3469299127
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1738938011
Short name T30
Test name
Test status
Simulation time 28415853135 ps
CPU time 1615.85 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 05:12:14 PM PDT 24
Peak memory 273952 kb
Host smart-06ae965e-2900-4b37-a9e7-f25beca3ecd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738938011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1738938011
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3374824738
Short name T396
Test name
Test status
Simulation time 1303861654 ps
CPU time 8.17 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:26 PM PDT 24
Peak memory 249228 kb
Host smart-9cf4c7be-56e1-4376-9d47-10bafd5aea78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3374824738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3374824738
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1952122291
Short name T662
Test name
Test status
Simulation time 4585503364 ps
CPU time 198.43 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:48:47 PM PDT 24
Peak memory 256828 kb
Host smart-11eeed7b-35ba-4fb4-95fb-c7c75bd8199e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
22291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1952122291
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1670118440
Short name T478
Test name
Test status
Simulation time 20294196 ps
CPU time 2.88 seconds
Started Jul 12 04:45:20 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 240212 kb
Host smart-a67bca82-8478-44ef-b653-a0ed9b44528a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16701
18440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1670118440
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2976022917
Short name T324
Test name
Test status
Simulation time 207966625218 ps
CPU time 2722.93 seconds
Started Jul 12 04:45:25 PM PDT 24
Finished Jul 12 05:30:50 PM PDT 24
Peak memory 289912 kb
Host smart-3954db26-2a18-4c0b-8ef2-c7b3b707bb93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976022917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2976022917
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1371536051
Short name T503
Test name
Test status
Simulation time 198385552394 ps
CPU time 3077.59 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 05:36:38 PM PDT 24
Peak memory 290036 kb
Host smart-595a9c4f-b286-4c78-8e57-5a32e56e6343
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371536051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1371536051
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1258103876
Short name T295
Test name
Test status
Simulation time 9723252897 ps
CPU time 382.51 seconds
Started Jul 12 04:45:25 PM PDT 24
Finished Jul 12 04:51:49 PM PDT 24
Peak memory 249388 kb
Host smart-f55ffa45-1b43-49b7-8905-dfd441c1d799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258103876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1258103876
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1027684054
Short name T507
Test name
Test status
Simulation time 101761781 ps
CPU time 5.94 seconds
Started Jul 12 04:45:29 PM PDT 24
Finished Jul 12 04:45:37 PM PDT 24
Peak memory 254064 kb
Host smart-5f592624-de3d-4b1b-80c8-3dc54e17a587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10276
84054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1027684054
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3146261656
Short name T424
Test name
Test status
Simulation time 184236893 ps
CPU time 6.37 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:45:26 PM PDT 24
Peak memory 255528 kb
Host smart-59fd6547-f3de-433e-b270-2f239463ac0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31462
61656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3146261656
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1526161544
Short name T254
Test name
Test status
Simulation time 351093833 ps
CPU time 24.68 seconds
Started Jul 12 04:46:15 PM PDT 24
Finished Jul 12 04:46:41 PM PDT 24
Peak memory 249116 kb
Host smart-6f51340d-83e3-4610-a8e8-d139a2f99bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15261
61544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1526161544
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1377534576
Short name T546
Test name
Test status
Simulation time 1796624146 ps
CPU time 50.88 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 04:46:07 PM PDT 24
Peak memory 257384 kb
Host smart-97cdd0f4-6497-4ed3-be6d-25733d5f2682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13775
34576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1377534576
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1871801354
Short name T211
Test name
Test status
Simulation time 294182415 ps
CPU time 3.83 seconds
Started Jul 12 04:45:19 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 249572 kb
Host smart-7856e798-b55c-4c2b-a533-1cc754b9eb3f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1871801354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1871801354
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.287989501
Short name T631
Test name
Test status
Simulation time 315383696540 ps
CPU time 3250.91 seconds
Started Jul 12 04:45:26 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 290192 kb
Host smart-91a5344d-e020-4b4a-a1cc-fc73dc288c00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287989501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.287989501
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3555478673
Short name T218
Test name
Test status
Simulation time 730075354 ps
CPU time 30.62 seconds
Started Jul 12 04:45:19 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 249168 kb
Host smart-10810f52-8a49-48fd-b4d5-bb04248ba510
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3555478673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3555478673
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3767381767
Short name T277
Test name
Test status
Simulation time 1056127726 ps
CPU time 71.85 seconds
Started Jul 12 04:45:26 PM PDT 24
Finished Jul 12 04:46:39 PM PDT 24
Peak memory 256884 kb
Host smart-2b3f6e08-d081-4edf-9bda-ca473b3513ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
81767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3767381767
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2296187990
Short name T561
Test name
Test status
Simulation time 61744955 ps
CPU time 4.77 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 04:45:31 PM PDT 24
Peak memory 254024 kb
Host smart-86b37859-7874-432c-9e47-a13641bb8d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961
87990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2296187990
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4161979981
Short name T326
Test name
Test status
Simulation time 9875576178 ps
CPU time 965.25 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 05:01:34 PM PDT 24
Peak memory 289784 kb
Host smart-d54a8861-e302-4dfe-9280-fa44ff2517e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161979981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4161979981
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3817844937
Short name T440
Test name
Test status
Simulation time 184403575464 ps
CPU time 2899.09 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 05:33:39 PM PDT 24
Peak memory 288216 kb
Host smart-197370af-173d-4c94-a91a-7ae474187447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817844937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3817844937
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3590657948
Short name T312
Test name
Test status
Simulation time 20532374164 ps
CPU time 221.83 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:49:01 PM PDT 24
Peak memory 249352 kb
Host smart-69458bf1-2466-41fe-9843-b77d0256a633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590657948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3590657948
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2135361529
Short name T381
Test name
Test status
Simulation time 3666859311 ps
CPU time 52.75 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 04:46:09 PM PDT 24
Peak memory 256792 kb
Host smart-5e55080d-fc50-420d-8deb-dedd60e204b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21353
61529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2135361529
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1394457673
Short name T92
Test name
Test status
Simulation time 4334024470 ps
CPU time 64.55 seconds
Started Jul 12 04:45:22 PM PDT 24
Finished Jul 12 04:46:27 PM PDT 24
Peak memory 257480 kb
Host smart-5178d43c-c1a2-4258-b1e7-89c2afe50125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13944
57673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1394457673
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.216312343
Short name T578
Test name
Test status
Simulation time 584175664 ps
CPU time 17.86 seconds
Started Jul 12 04:45:25 PM PDT 24
Finished Jul 12 04:45:45 PM PDT 24
Peak memory 256936 kb
Host smart-02721ed3-685b-457d-90c7-1e4de00dc9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
2343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.216312343
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3739901261
Short name T677
Test name
Test status
Simulation time 1454847711 ps
CPU time 24.33 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:45:43 PM PDT 24
Peak memory 257352 kb
Host smart-5a38b744-df99-462a-bc0b-ccf597fa5fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37399
01261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3739901261
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.881307875
Short name T112
Test name
Test status
Simulation time 17885848742 ps
CPU time 1987.31 seconds
Started Jul 12 04:45:20 PM PDT 24
Finished Jul 12 05:18:29 PM PDT 24
Peak memory 306044 kb
Host smart-3c81c0cc-5619-4a1e-8983-ece93ca54123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881307875 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.881307875
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1059669027
Short name T213
Test name
Test status
Simulation time 87690249 ps
CPU time 3.17 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 04:45:40 PM PDT 24
Peak memory 249500 kb
Host smart-f6eb357f-1f72-4b07-9372-09d7a06e7a33
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1059669027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1059669027
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3313067128
Short name T640
Test name
Test status
Simulation time 271872131238 ps
CPU time 3042.42 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 282168 kb
Host smart-d24ebfb1-5b69-4caa-98dd-a3f78a73c350
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313067128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3313067128
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1984404813
Short name T473
Test name
Test status
Simulation time 208106319 ps
CPU time 10.53 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:45:39 PM PDT 24
Peak memory 249076 kb
Host smart-0a5866fd-4b76-48b6-8955-86a250af5cff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1984404813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1984404813
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.813976731
Short name T552
Test name
Test status
Simulation time 1628455615 ps
CPU time 164.02 seconds
Started Jul 12 04:45:19 PM PDT 24
Finished Jul 12 04:48:05 PM PDT 24
Peak memory 256952 kb
Host smart-91c813c0-5bdb-4d0e-81a1-b26861587c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81397
6731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.813976731
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1002486512
Short name T374
Test name
Test status
Simulation time 1498517491 ps
CPU time 47.98 seconds
Started Jul 12 04:45:17 PM PDT 24
Finished Jul 12 04:46:07 PM PDT 24
Peak memory 249640 kb
Host smart-c8b5646c-5f71-40f4-b3b7-a5e1c1c77025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10024
86512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1002486512
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.532989367
Short name T284
Test name
Test status
Simulation time 95033885763 ps
CPU time 1515.8 seconds
Started Jul 12 04:45:15 PM PDT 24
Finished Jul 12 05:10:32 PM PDT 24
Peak memory 273860 kb
Host smart-dc9f780d-8547-4b7b-be12-86d9dda98bae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532989367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.532989367
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2615193517
Short name T651
Test name
Test status
Simulation time 101394979281 ps
CPU time 1412.67 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 05:08:59 PM PDT 24
Peak memory 287880 kb
Host smart-492983e8-2ea0-484d-97b0-7a0c5e1e063b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615193517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2615193517
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.631905282
Short name T676
Test name
Test status
Simulation time 3173438408 ps
CPU time 129.4 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:47:27 PM PDT 24
Peak memory 249364 kb
Host smart-896c8d20-5860-4f2e-8dec-c0a27b13ee46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631905282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.631905282
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4268251254
Short name T497
Test name
Test status
Simulation time 1076123021 ps
CPU time 58.49 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:46:18 PM PDT 24
Peak memory 256684 kb
Host smart-3a7018a9-bcdc-4e9a-99af-2e3c1a5b96be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42682
51254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4268251254
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2777652705
Short name T70
Test name
Test status
Simulation time 694701596 ps
CPU time 39.76 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:46:00 PM PDT 24
Peak memory 248960 kb
Host smart-51a9720a-95c2-4e20-9ccf-2871655ab802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27776
52705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2777652705
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3253273396
Short name T485
Test name
Test status
Simulation time 224894588 ps
CPU time 7.41 seconds
Started Jul 12 04:45:14 PM PDT 24
Finished Jul 12 04:45:22 PM PDT 24
Peak memory 255632 kb
Host smart-ed5dcf97-fc1d-47be-892e-2067030e8bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32532
73396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3253273396
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3042647874
Short name T276
Test name
Test status
Simulation time 3188881936 ps
CPU time 59.39 seconds
Started Jul 12 04:45:22 PM PDT 24
Finished Jul 12 04:46:23 PM PDT 24
Peak memory 257396 kb
Host smart-5409d597-ff3e-451c-a7bd-ef0bcd83599f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042647874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3042647874
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2627969981
Short name T229
Test name
Test status
Simulation time 35883120794 ps
CPU time 3982.55 seconds
Started Jul 12 04:45:20 PM PDT 24
Finished Jul 12 05:51:44 PM PDT 24
Peak memory 331388 kb
Host smart-6dd08b53-281e-4d77-8285-ce56a686ef35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627969981 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2627969981
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.608486744
Short name T60
Test name
Test status
Simulation time 49307312 ps
CPU time 2.43 seconds
Started Jul 12 04:45:26 PM PDT 24
Finished Jul 12 04:45:30 PM PDT 24
Peak memory 249412 kb
Host smart-311a5065-7973-413e-90c5-99ac22dc8823
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=608486744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.608486744
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.383379948
Short name T529
Test name
Test status
Simulation time 24145906311 ps
CPU time 1296.61 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 05:07:06 PM PDT 24
Peak memory 289988 kb
Host smart-c4019de9-5f5d-4eef-a700-0daf8fb03667
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383379948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.383379948
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.200355004
Short name T533
Test name
Test status
Simulation time 329166911 ps
CPU time 15.75 seconds
Started Jul 12 04:45:32 PM PDT 24
Finished Jul 12 04:45:51 PM PDT 24
Peak memory 249228 kb
Host smart-48897a13-2dd0-4e0d-8b86-85af1d341913
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=200355004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.200355004
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3159986320
Short name T678
Test name
Test status
Simulation time 4829732292 ps
CPU time 300.81 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:50:30 PM PDT 24
Peak memory 256788 kb
Host smart-c43cffae-44f1-4a28-86c7-217ce5477870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31599
86320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3159986320
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3194871294
Short name T247
Test name
Test status
Simulation time 967964183 ps
CPU time 55.84 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:46:26 PM PDT 24
Peak memory 249080 kb
Host smart-66dd8b29-ead2-43f4-8a6c-6d3996065862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31948
71294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3194871294
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2626104131
Short name T68
Test name
Test status
Simulation time 225227924540 ps
CPU time 1078.94 seconds
Started Jul 12 04:45:21 PM PDT 24
Finished Jul 12 05:03:21 PM PDT 24
Peak memory 265864 kb
Host smart-9d6b318f-80ec-42b6-89ea-e268e8824eaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626104131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2626104131
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3397193423
Short name T82
Test name
Test status
Simulation time 83142721853 ps
CPU time 1434.98 seconds
Started Jul 12 04:45:24 PM PDT 24
Finished Jul 12 05:09:21 PM PDT 24
Peak memory 273972 kb
Host smart-d2f6dd93-199c-40f9-8b62-822e011e1622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397193423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3397193423
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.739243002
Short name T513
Test name
Test status
Simulation time 8370509082 ps
CPU time 351.18 seconds
Started Jul 12 04:45:27 PM PDT 24
Finished Jul 12 04:51:20 PM PDT 24
Peak memory 249284 kb
Host smart-2c56adb2-237b-4835-8359-cb13f46ca6a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739243002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.739243002
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1616784905
Short name T431
Test name
Test status
Simulation time 279276278 ps
CPU time 15.97 seconds
Started Jul 12 04:45:19 PM PDT 24
Finished Jul 12 04:45:37 PM PDT 24
Peak memory 249264 kb
Host smart-4af4da38-72e5-4bf2-b00c-bfa15ca4d5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16167
84905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1616784905
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3391417626
Short name T449
Test name
Test status
Simulation time 182208188 ps
CPU time 4.02 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:22 PM PDT 24
Peak memory 240928 kb
Host smart-6cbaec17-955c-4109-ba79-fa4e9c1cbf66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914
17626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3391417626
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1189625851
Short name T657
Test name
Test status
Simulation time 114912445 ps
CPU time 4.5 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:22 PM PDT 24
Peak memory 241012 kb
Host smart-17763d92-4a6f-42ce-aa1f-7f94bf2ca83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11896
25851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1189625851
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.29381704
Short name T672
Test name
Test status
Simulation time 353681433 ps
CPU time 27.72 seconds
Started Jul 12 04:45:18 PM PDT 24
Finished Jul 12 04:45:47 PM PDT 24
Peak memory 257356 kb
Host smart-91e18ab4-8e5a-4b21-91d0-e356fc2edf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.29381704
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2042009189
Short name T25
Test name
Test status
Simulation time 46345303895 ps
CPU time 2677.84 seconds
Started Jul 12 04:45:31 PM PDT 24
Finished Jul 12 05:30:12 PM PDT 24
Peak memory 282100 kb
Host smart-8894baab-b28f-49e4-ae62-1f2abe03d97d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042009189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2042009189
Directory /workspace/9.alert_handler_stress_all/latest
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