Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62669669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30267487

1

T1

129

T2

624

T3

84

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14161507	1			T1	73		T2	617		T3	25
values[0x0]	38578368	1			T1	191		T2	617		T3	166
values[0x1]	40197281	1			T1	189		T2	616		T3	155

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53706260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39230896

1

T1

172

T2

798

T3

114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	269406	1			T2	1		T6	9		T4	4
valid_sources[0x01]	285702	1			T1	2		T2	3		T3	1
valid_sources[0x02]	268275	1			T1	2		T2	8		T6	3
valid_sources[0x03]	277124	1			T2	9		T4	2		T5	1512
valid_sources[0x04]	265451	1			T1	5		T2	20		T6	2
valid_sources[0x05]	524286	1			T2	4		T6	1		T4	3
valid_sources[0x06]	283138	1			T2	7		T3	2		T6	1
valid_sources[0x07]	272607	1			T1	1		T2	13		T3	5
valid_sources[0x08]	268751	1			T2	9		T6	5		T4	6
valid_sources[0x09]	277509	1			T1	3		T2	8		T3	2
valid_sources[0x0a]	274416	1			T2	4		T3	3		T6	2
valid_sources[0x0b]	278472	1			T1	5		T2	6		T3	6
valid_sources[0x0c]	277967	1			T1	1		T2	5		T6	1
valid_sources[0x0d]	268537	1			T1	4		T2	4		T6	1
valid_sources[0x0e]	804037	1			T1	2		T2	1		T6	5
valid_sources[0x0f]	816465	1			T1	1		T2	2		T4	2
valid_sources[0x10]	288136	1			T1	7		T2	3		T6	1
valid_sources[0x11]	302984	1			T2	3		T3	1		T6	4
valid_sources[0x12]	272155	1			T2	5		T6	4		T4	2
valid_sources[0x13]	274206	1			T1	1		T2	5		T3	3
valid_sources[0x14]	856873	1			T1	3		T2	5		T3	4
valid_sources[0x15]	273015	1			T2	4		T3	8		T4	5
valid_sources[0x16]	263178	1			T1	2		T2	5		T6	3
valid_sources[0x17]	270567	1			T1	4		T2	1		T4	1
valid_sources[0x18]	266298	1			T2	7		T6	2		T4	8
valid_sources[0x19]	758596	1			T1	1		T2	5		T6	7
valid_sources[0x1a]	263476	1			T2	5		T6	2		T4	6
valid_sources[0x1b]	268751	1			T1	1		T2	10		T3	1
valid_sources[0x1c]	288343	1			T1	3		T2	3		T3	2
valid_sources[0x1d]	270367	1			T1	4		T2	5		T6	2
valid_sources[0x1e]	264815	1			T1	3		T2	14		T6	1
valid_sources[0x1f]	726790	1			T1	2		T2	4		T3	1
valid_sources[0x20]	279297	1			T2	8		T3	5		T6	8
valid_sources[0x21]	683079	1			T1	1		T2	11		T3	2
valid_sources[0x22]	271933	1			T1	1		T2	8		T3	1
valid_sources[0x23]	261421	1			T1	1		T2	7		T3	1
valid_sources[0x24]	270563	1			T1	2		T2	4		T3	1
valid_sources[0x25]	283100	1			T1	1		T2	2		T3	3
valid_sources[0x26]	282692	1			T1	4		T2	10		T3	1
valid_sources[0x27]	267133	1			T1	2		T2	1		T3	1
valid_sources[0x28]	270453	1			T1	2		T2	9		T3	1
valid_sources[0x29]	272781	1			T2	9		T4	3		T5	1830
valid_sources[0x2a]	273565	1			T1	3		T2	7		T3	3
valid_sources[0x2b]	271455	1			T1	5		T2	12		T3	3
valid_sources[0x2c]	268593	1			T1	1		T2	5		T4	3
valid_sources[0x2d]	274533	1			T1	3		T2	16		T4	2
valid_sources[0x2e]	270260	1			T2	9		T4	1		T5	2052
valid_sources[0x2f]	274956	1			T1	2		T2	15		T3	2
valid_sources[0x30]	662748	1			T2	2		T5	1670		T7	23
valid_sources[0x31]	274765	1			T1	1		T2	10		T3	3
valid_sources[0x32]	273183	1			T1	5		T2	6		T3	2
valid_sources[0x33]	271410	1			T1	2		T2	2		T3	2
valid_sources[0x34]	267060	1			T1	2		T2	6		T4	2
valid_sources[0x35]	275822	1			T1	1		T2	9		T3	2
valid_sources[0x36]	274993	1			T1	1		T2	7		T3	3
valid_sources[0x37]	263516	1			T2	17		T5	1592		T7	34
valid_sources[0x38]	582634	1			T2	8		T6	2		T4	3
valid_sources[0x39]	271469	1			T5	1690		T7	25		T8	927
valid_sources[0x3a]	283115	1			T1	4		T2	6		T3	4
valid_sources[0x3b]	279841	1			T1	1		T2	3		T4	1
valid_sources[0x3c]	269354	1			T2	8		T6	2		T4	5
valid_sources[0x3d]	274627	1			T1	1		T2	4		T3	1
valid_sources[0x3e]	268162	1			T2	10		T6	3		T4	4
valid_sources[0x3f]	667089	1			T1	4		T2	5		T3	1
valid_sources[0x40]	663823	1			T1	2		T2	4		T6	1
valid_sources[0x41]	978726	1			T1	2		T2	15		T3	3
valid_sources[0x42]	269148	1			T1	2		T2	9		T3	2
valid_sources[0x43]	272806	1			T1	2		T2	6		T5	1607
valid_sources[0x44]	270496	1			T1	3		T2	5		T3	1
valid_sources[0x45]	279628	1			T1	4		T2	4		T3	2
valid_sources[0x46]	277341	1			T1	2		T2	10		T3	7
valid_sources[0x47]	269091	1			T1	3		T2	5		T6	1
valid_sources[0x48]	270817	1			T2	5		T6	3		T4	2
valid_sources[0x49]	258609	1			T1	1		T2	9		T3	1
valid_sources[0x4a]	972888	1			T1	2		T2	6		T4	3
valid_sources[0x4b]	265149	1			T2	5		T3	1		T6	2
valid_sources[0x4c]	1088218	1			T1	1		T2	6		T3	1
valid_sources[0x4d]	282041	1			T1	5		T2	5		T6	5
valid_sources[0x4e]	276413	1			T1	1		T2	10		T3	2
valid_sources[0x4f]	276917	1			T1	2		T2	8		T3	1
valid_sources[0x50]	276325	1			T2	4		T3	1		T6	3
valid_sources[0x51]	278035	1			T1	3		T2	11		T6	2
valid_sources[0x52]	265754	1			T2	7		T6	2		T4	12
valid_sources[0x53]	266188	1			T1	2		T2	2		T3	2
valid_sources[0x54]	272204	1			T2	10		T3	9		T6	1
valid_sources[0x55]	270866	1			T1	4		T2	15		T6	1
valid_sources[0x56]	750938	1			T1	1		T2	4		T6	8
valid_sources[0x57]	282043	1			T1	9		T2	7		T6	2
valid_sources[0x58]	276531	1			T1	2		T2	10		T3	1
valid_sources[0x59]	667546	1			T1	4		T2	5		T3	3
valid_sources[0x5a]	274626	1			T1	3		T2	10		T3	1
valid_sources[0x5b]	265563	1			T2	5		T6	2		T4	7
valid_sources[0x5c]	277204	1			T1	2		T2	7		T3	1
valid_sources[0x5d]	268387	1			T1	2		T2	11		T6	2
valid_sources[0x5e]	280146	1			T2	1		T6	1		T4	3
valid_sources[0x5f]	275218	1			T2	9		T3	1		T6	2
valid_sources[0x60]	273925	1			T3	1		T6	1		T4	5
valid_sources[0x61]	272043	1			T1	8		T2	6		T6	2
valid_sources[0x62]	269035	1			T1	1		T2	5		T3	1
valid_sources[0x63]	872800	1			T2	8		T6	1		T4	8
valid_sources[0x64]	630408	1			T1	1		T2	6		T3	1
valid_sources[0x65]	260924	1			T2	5		T3	3		T6	2
valid_sources[0x66]	270777	1			T2	11		T3	1		T6	3
valid_sources[0x67]	275062	1			T2	8		T6	3		T4	4
valid_sources[0x68]	276728	1			T2	3		T3	6		T4	1
valid_sources[0x69]	272788	1			T1	2		T2	9		T3	2
valid_sources[0x6a]	756618	1			T1	1		T2	4		T3	2
valid_sources[0x6b]	276276	1			T1	1		T2	19		T6	2
valid_sources[0x6c]	274789	1			T1	5		T2	10		T6	1
valid_sources[0x6d]	269790	1			T1	1		T2	7		T3	2
valid_sources[0x6e]	267763	1			T2	8		T6	3		T4	3
valid_sources[0x6f]	273286	1			T1	5		T2	7		T3	8
valid_sources[0x70]	264447	1			T1	5		T2	3		T6	3
valid_sources[0x71]	275863	1			T1	2		T2	12		T5	1715
valid_sources[0x72]	281894	1			T2	9		T3	1		T6	6
valid_sources[0x73]	273826	1			T2	6		T6	1		T4	1
valid_sources[0x74]	274008	1			T2	12		T3	1		T6	1
valid_sources[0x75]	267087	1			T1	2		T2	3		T3	1
valid_sources[0x76]	276068	1			T2	5		T6	3		T4	4
valid_sources[0x77]	277680	1			T1	1		T2	8		T3	3
valid_sources[0x78]	275534	1			T1	1		T2	5		T6	7
valid_sources[0x79]	269933	1			T2	9		T3	5		T6	2
valid_sources[0x7a]	310410	1			T1	6		T2	6		T4	1
valid_sources[0x7b]	268580	1			T1	2		T2	6		T3	5
valid_sources[0x7c]	279042	1			T2	8		T6	7		T4	10
valid_sources[0x7d]	962596	1			T2	11		T3	3		T6	2
valid_sources[0x7e]	299071	1			T2	4		T3	3		T6	2
valid_sources[0x7f]	265659	1			T1	2		T2	10		T3	1
valid_sources[0x80]	275133	1			T1	3		T2	13		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6997835

1

T1

34

T2

312

T3

8

values[0x0]

all_enables

biggest_size

14713523

1

T1

70

T2

216

T3

46

values[0x1]

all_enables

biggest_size

8556129

1

T1

25

T2

96

T3

30