Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T25,T178
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13895	0	0
DisabledNoTrigBkwd_A	2147483647	782594	0	0
DisabledNoTrigFwd_A	2147483647	1588814411	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13895	0	0
T3	3351	383	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	560179	0	0	0
T16	579319	0	0	0
T17	396861	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	29229	0	0	0
T24	68805	0	0	0
T25	4481	920	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T71	4003	0	0	0
T178	4010	523	0	0
T197	0	427	0	0
T198	0	771	0	0
T199	0	932	0	0
T200	0	632	0	0
T201	0	1305	0	0
T202	0	354	0	0
T203	0	1214	0	0
T204	0	582	0	0
T205	0	597	0	0
T206	0	373	0	0
T207	0	1070	0	0
T208	0	706	0	0
T209	0	800	0	0
T210	0	918	0	0
T211	0	392	0	0
T212	0	254	0	0
T213	0	742	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	782594	0	0
T2	29172	22	0	0
T3	10053	8	0	0
T4	161214	0	0	0
T5	2085280	5	0	0
T6	14295	0	0	0
T7	3100080	2	0	0
T8	872968	202	0	0
T9	733472	0	0	0
T13	319568	2	0	0
T14	44260	0	0	0
T15	0	3531	0	0
T16	0	1146	0	0
T17	0	5743	0	0
T18	231804	0	0	0
T19	144820	38	0	0
T20	0	56	0	0
T21	0	46	0	0
T24	68805	60	0	0
T25	4481	18	0	0
T26	0	3876	0	0
T36	0	3	0	0
T37	0	4924	0	0
T38	0	4109	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588814411	0	0
T1	106184	12929	0	0
T2	58344	28587	0	0
T3	13404	10821	0	0
T4	214952	163644	0	0
T5	2085280	1058393	0	0
T6	19060	11080	0	0
T7	3100080	2170455	0	0
T8	872968	660341	0	0
T18	231804	189223	0	0
T19	144820	63728	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T3,T6,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T198,T200
1	1	Covered	T3,T6,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695077144	3688	0	0
DisabledNoTrigBkwd_A	695077144	234077	0	0
DisabledNoTrigFwd_A	695077144	374798097	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	3688	0	0
T3	3351	383	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T198	0	771	0	0
T200	0	632	0	0
T201	0	1305	0	0
T205	0	597	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	234077	0	0
T3	3351	8	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	2	0	0
T8	218242	202	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	139	0	0
T17	0	1193	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	29	0	0
T24	0	20	0	0
T26	0	2078	0	0
T36	0	3	0	0
T38	0	2230	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	374798097	0	0
T1	26546	3202	0	0
T2	14586	14526	0	0
T3	3351	2685	0	0
T4	53738	40911	0	0
T5	521320	520744	0	0
T6	4765	2102	0	0
T7	775020	2084	0	0
T8	218242	7546	0	0
T18	57951	43376	0	0
T19	36205	36153	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T18,T7
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T211
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695077144	1312	0	0
DisabledNoTrigBkwd_A	695077144	176683	0	0
DisabledNoTrigFwd_A	695077144	424398131	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1312	0	0
T14	44260	0	0	0
T15	560179	0	0	0
T16	579319	0	0	0
T17	396861	0	0	0
T20	29229	0	0	0
T24	68805	0	0	0
T25	4481	920	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T71	4003	0	0	0
T211	0	392	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	176683	0	0
T2	14586	5	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	0	2	0	0
T15	0	143	0	0
T17	0	1119	0	0
T18	57951	0	0	0
T19	36205	24	0	0
T20	0	3	0	0
T24	0	19	0	0
T25	0	18	0	0
T26	0	3	0	0
T37	0	1967	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	424398131	0	0
T1	26546	3230	0	0
T2	14586	2103	0	0
T3	3351	2699	0	0
T4	53738	40911	0	0
T5	521320	520046	0	0
T6	4765	2126	0	0
T7	775020	669264	0	0
T8	218242	216835	0	0
T18	57951	47860	0	0
T19	36205	2563	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T18,T7
1	1	Covered	T2,T6,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T178,T197,T202
1	1	Covered	T2,T6,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T19,T24

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695077144	5933	0	0
DisabledNoTrigBkwd_A	695077144	153879	0	0
DisabledNoTrigFwd_A	695077144	402707419	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	5933	0	0
T27	60779	0	0	0
T76	427030	0	0	0
T77	92565	0	0	0
T78	836757	0	0	0
T81	11452	0	0	0
T178	4010	523	0	0
T197	0	427	0	0
T202	0	354	0	0
T203	0	1214	0	0
T206	0	373	0	0
T207	0	1070	0	0
T209	0	800	0	0
T210	0	918	0	0
T212	0	254	0	0
T214	175035	0	0	0
T215	140757	0	0	0
T216	26836	0	0	0
T217	71266	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	153879	0	0
T5	521320	2	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	3036	0	0
T16	0	1146	0	0
T17	0	2080	0	0
T18	57951	0	0	0
T19	36205	3	0	0
T20	0	2	0	0
T24	68805	21	0	0
T25	4481	0	0	0
T26	0	3	0	0
T37	0	1861	0	0
T38	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	402707419	0	0
T1	26546	3244	0	0
T2	14586	9817	0	0
T3	3351	2713	0	0
T4	53738	40911	0	0
T5	521320	3004	0	0
T6	4765	2139	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	49058	0	0
T19	36205	22410	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T5,T18
1	1	Covered	T2,T5,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T204,T208
1	1	Covered	T2,T5,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695077144	2962	0	0
DisabledNoTrigBkwd_A	695077144	217955	0	0
DisabledNoTrigFwd_A	695077144	386910764	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	2962	0	0
T53	283672	0	0	0
T104	201862	0	0	0
T199	3329	932	0	0
T204	0	582	0	0
T208	0	706	0	0
T213	0	742	0	0
T218	452162	0	0	0
T219	17879	0	0	0
T220	25340	0	0	0
T221	775587	0	0	0
T222	824346	0	0	0
T223	210186	0	0	0
T224	90050	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	217955	0	0
T2	14586	17	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	3	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T15	0	213	0	0
T17	0	1351	0	0
T18	57951	0	0	0
T19	36205	11	0	0
T20	0	22	0	0
T21	0	46	0	0
T26	0	1792	0	0
T37	0	1096	0	0
T38	0	1876	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	386910764	0	0
T1	26546	3253	0	0
T2	14586	2141	0	0
T3	3351	2724	0	0
T4	53738	40911	0	0
T5	521320	14599	0	0
T6	4765	4713	0	0
T7	775020	724158	0	0
T8	218242	217728	0	0
T18	57951	48929	0	0
T19	36205	2602	0	0