Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T20
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T6,T19,T20
1	1	1	Covered	T6,T19,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T15
0	1	Covered	T15,T17,T21
1	0	Covered	T17,T22,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T20,T15
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T22,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T20
1	0	Not Covered
1	1	Covered	T15,T17,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T2,T3,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T5,T7,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T24,T15,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T5,T24,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T5,T25

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T5
Phase1St	198	Covered	T2,T3,T5
Phase2St	215	Covered	T2,T3,T5
Phase3St	233	Covered	T2,T3,T5
TerminalSt	249	Covered	T2,T3,T5
TimeoutSt	159	Covered	T6,T19,T20

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T6,T19,T20
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T15,T26,T27
Phase0St->Phase1St	198	Covered	T2,T3,T5
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T15,T28,T29
Phase1St->Phase2St	215	Covered	T2,T3,T5
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T15,T28,T30
Phase2St->Phase3St	233	Covered	T2,T3,T5
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T24,T31,T32
Phase3St->TerminalSt	249	Covered	T2,T3,T5
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T5,T7,T24
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T6,T20,T15
TimeoutSt->Phase0St	172	Covered	T15,T17,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T17,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T26,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T5,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T5,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T28,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T5,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T31,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T5,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T24,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1097	0	0
CheckAccumTrig0_A	2147483647	2380	0	0
CheckAccumTrig1_A	2147483647	116	0	0
CheckClr_A	2147483647	1139	0	0
CheckEn_A	2147483647	1252858729	0	0
CheckPhase0_A	2147483647	2728	0	0
CheckPhase1_A	2147483647	2676	0	0
CheckPhase2_A	2147483647	2612	0	0
CheckPhase3_A	2147483647	2568	0	0
CheckTimeout0_A	2147483647	4900	0	0
CheckTimeoutSt1_A	2147483647	509225	0	0
CheckTimeoutSt2_A	2147483647	4500	0	0
CheckTimeoutStTrig_A	2147483647	276	0	0
ErrorStAllEscAsserted_A	2147483647	5800	0	0
ErrorStIsTerminal_A	2147483647	4840	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1097	0	0
T4	214952	159	0	0
T5	2085280	0	0	0
T7	3100080	0	0	0
T8	872968	0	0	0
T9	733472	0	0	0
T11	0	251	0	0
T12	0	288	0	0
T13	639136	0	0	0
T14	177040	0	0	0
T18	231804	0	0	0
T19	144820	0	0	0
T25	17924	0	0	0
T34	0	124	0	0
T35	0	275	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2380	0	0
T2	29172	2	0	0
T3	10053	1	0	0
T4	161214	0	0	0
T5	2085280	3	0	0
T6	14295	0	0	0
T7	3100080	2	0	0
T8	872968	1	0	0
T9	733472	0	0	0
T13	319568	1	0	0
T14	44260	0	0	0
T15	0	31	0	0
T16	0	1	0	0
T17	0	19	0	0
T18	231804	0	0	0
T19	144820	2	0	0
T20	0	9	0	0
T22	0	1	0	0
T24	68805	13	0	0
T25	4481	1	0	0
T26	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116	0	0
T11	47110	0	0	0
T17	396861	1	0	0
T22	372215	1	0	0
T23	246688	1	0	0
T29	47503	0	0	0
T31	0	3	0	0
T40	11242	0	0	0
T41	81221	1	0	0
T42	85727	1	0	0
T43	59896	1	0	0
T44	972510	1	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	26515	0	0	0
T59	287063	0	0	0
T60	45741	0	0	0
T61	184488	0	0	0
T62	129021	0	0	0
T63	85034	0	0	0
T64	108144	0	0	0
T65	118607	0	0	0
T66	383216	0	0	0
T67	83490	0	0	0
T68	394512	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1139	0	0
T5	521320	0	0	0
T7	1550040	2	0	0
T8	436484	0	0	0
T9	366736	0	0	0
T13	319568	0	0	0
T14	88520	0	0	0
T15	1680537	15	0	0
T16	1158638	0	0	0
T17	793722	8	0	0
T18	57951	0	0	0
T19	72410	0	0	0
T20	87687	6	0	0
T22	0	4	0	0
T23	0	1	0	0
T24	206415	10	0	0
T25	8962	0	0	0
T26	852176	1	0	0
T28	0	6	0	0
T29	0	1	0	0
T31	0	2	0	0
T36	79612	0	0	0
T37	485154	0	0	0
T38	957168	1	0	0
T41	0	7	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0
T66	0	3	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	8006	0	0	0
T72	92598	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1252858729	0	0
T1	106184	12925	0	0
T2	58344	28585	0	0
T3	13404	10821	0	0
T4	3464	3072	0	0
T5	2085280	1058392	0	0
T6	19060	11079	0	0
T7	3100080	2170452	0	0
T8	872968	660341	0	0
T18	231804	189219	0	0
T19	144820	58841	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2728	0	0
T2	29172	2	0	0
T3	10053	1	0	0
T4	161214	0	0	0
T5	2085280	3	0	0
T6	14295	0	0	0
T7	3100080	2	0	0
T8	872968	1	0	0
T9	733472	0	0	0
T13	319568	1	0	0
T14	44260	0	0	0
T15	0	31	0	0
T16	0	1	0	0
T17	0	23	0	0
T18	231804	0	0	0
T19	144820	3	0	0
T20	0	12	0	0
T21	0	1	0	0
T22	0	2	0	0
T24	68805	13	0	0
T25	4481	1	0	0
T26	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2676	0	0
T2	29172	2	0	0
T3	10053	1	0	0
T4	161214	0	0	0
T5	2085280	3	0	0
T6	14295	0	0	0
T7	3100080	2	0	0
T8	872968	1	0	0
T9	733472	0	0	0
T13	319568	1	0	0
T14	44260	0	0	0
T15	0	29	0	0
T16	0	1	0	0
T17	0	23	0	0
T18	231804	0	0	0
T19	144820	3	0	0
T20	0	12	0	0
T21	0	1	0	0
T22	0	2	0	0
T24	68805	13	0	0
T25	4481	1	0	0
T26	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2612	0	0
T2	29172	2	0	0
T3	10053	1	0	0
T4	161214	0	0	0
T5	2085280	3	0	0
T6	14295	0	0	0
T7	3100080	2	0	0
T8	872968	1	0	0
T9	733472	0	0	0
T13	319568	1	0	0
T14	44260	0	0	0
T15	0	27	0	0
T16	0	1	0	0
T17	0	22	0	0
T18	231804	0	0	0
T19	144820	3	0	0
T20	0	12	0	0
T21	0	1	0	0
T22	0	2	0	0
T24	68805	13	0	0
T25	4481	1	0	0
T26	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2568	0	0
T2	29172	2	0	0
T3	10053	1	0	0
T4	161214	0	0	0
T5	2085280	3	0	0
T6	14295	0	0	0
T7	3100080	2	0	0
T8	872968	1	0	0
T9	733472	0	0	0
T13	319568	1	0	0
T14	44260	0	0	0
T15	0	27	0	0
T16	0	1	0	0
T17	0	22	0	0
T18	231804	0	0	0
T19	144820	3	0	0
T20	0	12	0	0
T21	0	1	0	0
T22	0	2	0	0
T24	68805	11	0	0
T25	4481	1	0	0
T26	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4900	0	0
T4	161214	0	0	0
T5	1563960	0	0	0
T6	14295	3	0	0
T7	2325060	0	0	0
T8	654726	0	0	0
T9	733472	0	0	0
T13	639136	0	0	0
T14	44260	0	0	0
T15	560179	18	0	0
T16	579319	0	0	0
T17	0	8	0	0
T18	173853	0	0	0
T19	144820	1	0	0
T20	29229	7	0	0
T21	0	2	0	0
T22	0	5	0	0
T23	0	4	0	0
T24	68805	0	0	0
T25	17924	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T36	39806	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T60	0	1	0	0
T63	0	2	0	0
T66	0	9	0	0
T69	0	3	0	0
T73	0	8	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	509225	0	0
T4	161214	0	0	0
T5	1563960	0	0	0
T6	14295	333	0	0
T7	2325060	0	0	0
T8	654726	0	0	0
T9	733472	0	0	0
T13	639136	0	0	0
T14	44260	0	0	0
T15	560179	3640	0	0
T16	579319	0	0	0
T17	0	752	0	0
T18	173853	0	0	0
T19	144820	0	0	0
T20	29229	861	0	0
T21	0	124	0	0
T22	0	344	0	0
T23	0	299	0	0
T24	68805	0	0	0
T25	17924	0	0	0
T27	0	883	0	0
T28	0	123	0	0
T36	39806	0	0	0
T41	0	9	0	0
T42	0	1	0	0
T44	0	60	0	0
T60	0	79	0	0
T63	0	919	0	0
T66	0	1442	0	0
T69	0	921	0	0
T73	0	582	0	0
T74	0	525	0	0
T75	0	284	0	0
T76	0	193	0	0
T77	0	157	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4500	0	0
T4	161214	0	0	0
T5	1563960	0	0	0
T6	14295	3	0	0
T7	2325060	0	0	0
T8	654726	0	0	0
T9	550104	0	0	0
T13	479352	0	0	0
T15	560179	15	0	0
T16	579319	0	0	0
T17	396861	4	0	0
T18	173853	0	0	0
T19	108615	0	0	0
T20	29229	4	0	0
T22	0	4	0	0
T23	0	3	0	0
T25	13443	0	0	0
T26	852176	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T31	0	1	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T44	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	0	9	0	0
T69	0	3	0	0
T71	4003	0	0	0
T72	46299	0	0	0
T73	0	6	0	0
T74	0	3	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	5	0	0
T79	0	2	0	0
T80	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276	0	0
T9	183368	0	0	0
T10	761767	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	1680537	2	0	0
T16	1737957	0	0	0
T17	1190583	1	0	0
T19	36205	0	0	0
T20	29229	0	0	0
T21	309234	1	0	0
T24	68805	0	0	0
T25	4481	0	0	0
T26	2556528	0	0	0
T28	380228	0	0	0
T36	119418	0	0	0
T37	727731	0	0	0
T38	1435752	0	0	0
T39	233578	0	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T51	0	1	0	0
T66	0	2	0	0
T71	8006	0	0	0
T72	138897	0	0	0
T73	48807	1	0	0
T75	0	1	0	0
T79	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5800	0	0
T4	214952	721	0	0
T5	2085280	0	0	0
T7	3100080	0	0	0
T8	872968	0	0	0
T9	733472	0	0	0
T11	0	1468	0	0
T12	0	1422	0	0
T13	639136	0	0	0
T14	177040	0	0	0
T18	231804	0	0	0
T19	144820	0	0	0
T25	17924	0	0	0
T34	0	756	0	0
T35	0	1433	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4840	0	0
T4	214952	601	0	0
T5	2085280	0	0	0
T7	3100080	0	0	0
T8	872968	0	0	0
T9	733472	0	0	0
T11	0	1228	0	0
T12	0	1182	0	0
T13	639136	0	0	0
T14	177040	0	0	0
T18	231804	0	0	0
T19	144820	0	0	0
T25	17924	0	0	0
T34	0	636	0	0
T35	0	1193	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	106184	105600	0	0
T2	58344	58104	0	0
T3	13404	13160	0	0
T4	1548	1160	0	0
T5	2085280	2085260	0	0
T6	19060	18852	0	0
T7	3100080	3099796	0	0
T8	872968	872928	0	0
T18	231804	231420	0	0
T19	144820	144612	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	106184	105600	0	0
T2	58344	58104	0	0
T3	13404	13160	0	0
T4	214952	163644	0	0
T5	2085280	2085260	0	0
T6	19060	18852	0	0
T7	3100080	3099796	0	0
T8	872968	872928	0	0
T18	231804	231420	0	0
T19	144820	144612	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T20,T15
1	0	1	Covered	T3,T18,T7
1	1	0	Covered	T19,T15,T17
1	1	1	Covered	T6,T20,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T15
0	1	Covered	T15,T21,T73
1	0	Covered	T22,T42,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T20,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T42,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T15
1	0	Not Covered
1	1	Covered	T15,T21,T73

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T15,T36
1	Covered	T3,T8,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T8,T24
1	Covered	T7,T15,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T17,T26,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T36,T17,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T24,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T8,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T7,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T24,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T7,T8
Phase1St	198	Covered	T3,T7,T8
Phase2St	215	Covered	T3,T7,T8
Phase3St	233	Covered	T3,T7,T8
TerminalSt	249	Covered	T3,T7,T8
TimeoutSt	159	Covered	T6,T20,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T3,T7,T8
IdleSt->TimeoutSt	159	Covered	T6,T20,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T27,T90
Phase0St->Phase1St	198	Covered	T3,T7,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T15,T27,T46
Phase1St->Phase2St	215	Covered	T3,T7,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T90,T89,T51
Phase2St->Phase3St	233	Covered	T3,T7,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T32,T91
Phase3St->TerminalSt	249	Covered	T3,T7,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T24,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T20,T15
TimeoutSt->Phase0St	172	Covered	T15,T21,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T21,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T27,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T7,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T7,T8,T24
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T27,T46
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T7,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T8,T24
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T90,T89,T51
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T7,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T7,T8,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T32,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T8,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T24,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T7,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695077144	304	0	0
CheckAccumTrig0_A	695077144	879	0	0
CheckAccumTrig1_A	695077144	43	0	0
CheckClr_A	695077144	411	0	0
CheckEn_A	694735639	296982259	0	0
CheckPhase0_A	695077144	979	0	0
CheckPhase1_A	695077144	961	0	0
CheckPhase2_A	695077144	947	0	0
CheckPhase3_A	695077144	933	0	0
CheckTimeout0_A	695077144	987	0	0
CheckTimeoutSt1_A	695077144	109219	0	0
CheckTimeoutSt2_A	695077144	872	0	0
CheckTimeoutStTrig_A	695077144	70	0	0
ErrorStAllEscAsserted_A	695077144	1428	0	0
ErrorStIsTerminal_A	695077144	1188	0	0
EscStateOut_A	694733303	694661181	0	0
u_state_regs_A	695077144	694903083	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	304	0	0
T4	53738	32	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	72	0	0
T12	0	80	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	34	0	0
T35	0	86	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	879	0	0
T3	3351	1	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	2	0	0
T8	218242	1	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	7	0	0
T17	0	9	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	5	0	0
T24	0	5	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	43	0	0
T11	47110	0	0	0
T22	372215	1	0	0
T23	246688	0	0	0
T40	11242	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T58	26515	0	0	0
T59	287063	0	0	0
T60	45741	0	0	0
T61	184488	0	0	0
T62	129021	0	0	0
T63	85034	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	411	0	0
T7	775020	2	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	560179	4	0	0
T17	0	4	0	0
T19	36205	0	0	0
T20	29229	4	0	0
T22	0	4	0	0
T24	68805	4	0	0
T25	4481	0	0	0
T41	0	6	0	0
T58	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694735639	296982259	0	0
T1	26546	3201	0	0
T2	14586	14525	0	0
T3	3351	2685	0	0
T4	866	768	0	0
T5	521320	520744	0	0
T6	4765	2102	0	0
T7	775020	2084	0	0
T8	218242	7546	0	0
T18	57951	43375	0	0
T19	36205	36152	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	979	0	0
T3	3351	1	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	2	0	0
T8	218242	1	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	7	0	0
T17	0	9	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	5	0	0
T24	0	5	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	961	0	0
T3	3351	1	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	2	0	0
T8	218242	1	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	6	0	0
T17	0	9	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	5	0	0
T24	0	5	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	947	0	0
T3	3351	1	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	2	0	0
T8	218242	1	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	6	0	0
T17	0	9	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	5	0	0
T24	0	5	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	933	0	0
T3	3351	1	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	2	0	0
T8	218242	1	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	6	0	0
T17	0	9	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	5	0	0
T24	0	5	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	987	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	13	0	0
T17	0	3	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	5	0	0
T25	4481	0	0	0
T42	0	1	0	0
T60	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	109219	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	111	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	2590	0	0
T17	0	562	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	15	0	0
T21	0	124	0	0
T22	0	344	0	0
T25	4481	0	0	0
T42	0	1	0	0
T60	0	79	0	0
T73	0	64	0	0
T74	0	525	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	872	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	12	0	0
T17	0	3	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	1	0	0
T22	0	4	0	0
T25	4481	0	0	0
T27	0	1	0	0
T60	0	1	0	0
T66	0	1	0	0
T74	0	3	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	70	0	0
T15	560179	1	0	0
T16	579319	0	0	0
T17	396861	0	0	0
T21	103078	1	0	0
T26	852176	0	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T66	0	1	0	0
T71	4003	0	0	0
T72	46299	0	0	0
T73	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1428	0	0
T4	53738	185	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	338	0	0
T12	0	341	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	202	0	0
T35	0	362	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1188	0	0
T4	53738	155	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	278	0	0
T12	0	281	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	172	0	0
T35	0	302	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694733303	694661181	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	387	290	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	694903083	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	53738	40911	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T20
1	0	1	Covered	T5,T18,T25
1	1	0	Covered	T20,T15,T17
1	1	1	Covered	T6,T20,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T15
0	1	Covered	T15,T75,T66
1	0	Covered	T41,T44,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T20,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T41,T44,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T15
1	0	Not Covered
1	1	Covered	T15,T75,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T24,T20,T15
1	Covered	T2,T19,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T13
1	Covered	T20,T15,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T13
1	Covered	T15,T22,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T13
1	Covered	T24,T15,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T19,T25,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T25,T24,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T19,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T25,T24,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T19,T13
Phase1St	198	Covered	T2,T19,T13
Phase2St	215	Covered	T2,T19,T13
Phase3St	233	Covered	T2,T19,T13
TerminalSt	249	Covered	T2,T19,T13
TimeoutSt	159	Covered	T6,T20,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T19,T13
IdleSt->TimeoutSt	159	Covered	T6,T20,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T26,T27
Phase0St->Phase1St	198	Covered	T2,T19,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T15,T29,T31
Phase1St->Phase2St	215	Covered	T2,T19,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T92,T93
Phase2St->Phase3St	233	Covered	T2,T19,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T94,T95,T96
Phase3St->TerminalSt	249	Covered	T2,T19,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T15,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T20,T15
TimeoutSt->Phase0St	172	Covered	T15,T75,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T75,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T19,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T19,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T29,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T19,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T19,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T19,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T19,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T94,T95,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T19,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T19,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T15,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T19,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695077144	283	0	0
CheckAccumTrig0_A	695077144	479	0	0
CheckAccumTrig1_A	695077144	31	0	0
CheckClr_A	695077144	238	0	0
CheckEn_A	694735639	346935124	0	0
CheckPhase0_A	695077144	570	0	0
CheckPhase1_A	695077144	557	0	0
CheckPhase2_A	695077144	547	0	0
CheckPhase3_A	695077144	535	0	0
CheckTimeout0_A	695077144	809	0	0
CheckTimeoutSt1_A	695077144	91665	0	0
CheckTimeoutSt2_A	695077144	705	0	0
CheckTimeoutStTrig_A	695077144	71	0	0
ErrorStAllEscAsserted_A	695077144	1460	0	0
ErrorStIsTerminal_A	695077144	1220	0	0
EscStateOut_A	694733303	694661181	0	0
u_state_regs_A	695077144	694903083	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	283	0	0
T4	53738	48	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	66	0	0
T12	0	75	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	28	0	0
T35	0	66	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	479	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	0	1	0	0
T15	0	15	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	31	0	0
T29	47503	0	0	0
T31	0	1	0	0
T41	81221	1	0	0
T42	85727	0	0	0
T43	59896	0	0	0
T44	972510	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	108144	0	0	0
T65	118607	0	0	0
T66	383216	0	0	0
T67	83490	0	0	0
T68	394512	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	238	0	0
T15	560179	10	0	0
T16	579319	0	0	0
T17	396861	2	0	0
T20	29229	1	0	0
T23	0	1	0	0
T26	852176	1	0	0
T29	0	1	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T66	0	2	0	0
T69	0	1	0	0
T71	4003	0	0	0
T72	46299	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694735639	346935124	0	0
T1	26546	3229	0	0
T2	14586	2103	0	0
T3	3351	2699	0	0
T4	866	768	0	0
T5	521320	520045	0	0
T6	4765	2126	0	0
T7	775020	669263	0	0
T8	218242	216835	0	0
T18	57951	47859	0	0
T19	36205	2563	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	570	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	0	1	0	0
T15	0	15	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T37	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	557	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	0	1	0	0
T15	0	14	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	547	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	0	1	0	0
T15	0	12	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	535	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	0	1	0	0
T15	0	12	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	809	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	3	0	0
T17	0	1	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T25	4481	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T66	0	3	0	0
T69	0	3	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	91665	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	111	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	1050	0	0
T17	0	62	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	846	0	0
T23	0	299	0	0
T25	4481	0	0	0
T27	0	437	0	0
T41	0	9	0	0
T66	0	1045	0	0
T69	0	921	0	0
T75	0	284	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	705	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T25	4481	0	0	0
T27	0	1	0	0
T66	0	2	0	0
T69	0	3	0	0
T76	0	1	0	0
T78	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	71	0	0
T15	560179	1	0	0
T16	579319	0	0	0
T17	396861	0	0	0
T21	103078	0	0	0
T26	852176	0	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T66	0	1	0	0
T71	4003	0	0	0
T72	46299	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1460	0	0
T4	53738	166	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	380	0	0
T12	0	367	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	186	0	0
T35	0	361	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1220	0	0
T4	53738	136	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	320	0	0
T12	0	307	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	156	0	0
T35	0	301	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694733303	694661181	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	387	290	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	694903083	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	53738	40911	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T6,T5,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T5,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T19,T24

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T20
1	0	1	Covered	T2,T36,T16
1	1	0	Covered	T19,T20,T15
1	1	1	Covered	T6,T17,T28

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T28
0	1	Covered	T17,T79,T83
1	0	Covered	T17,T23,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T17,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T23,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T28
1	0	Not Covered
1	1	Covered	T17,T79,T83

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T24,T20
1	Covered	T19,T20,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T24,T20
1	Covered	T5,T28,T61

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T19,T20
1	Covered	T24,T17,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T19,T24
1	Covered	T20,T15,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T19,T24,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T24,T20,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T24,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T24,T20,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T5,T19,T24
Phase1St	198	Covered	T5,T19,T24
Phase2St	215	Covered	T5,T19,T24
Phase3St	233	Covered	T5,T19,T24
TerminalSt	249	Covered	T5,T19,T24
TimeoutSt	159	Covered	T6,T17,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T5,T19,T24
IdleSt->TimeoutSt	159	Covered	T6,T17,T28
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T97,T98,T99
Phase0St->Phase1St	198	Covered	T5,T19,T24
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T51,T100
Phase1St->Phase2St	215	Covered	T5,T19,T24
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T30,T101
Phase2St->Phase3St	233	Covered	T5,T19,T24
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T28,T102
Phase3St->TerminalSt	249	Covered	T5,T19,T24
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T24,T20,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T28,T73
TimeoutSt->Phase0St	172	Covered	T17,T23,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T24
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T17,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T23,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T17,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T28,T73
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T98,T99,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T5,T19,T24
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T5,T19,T24
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T51,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T5,T19,T24
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T5,T19,T24
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T30,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T5,T19,T24
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T5,T19,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T28,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T5,T19,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T5,T19,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T24,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T19,T24
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695077144	249	0	0
CheckAccumTrig0_A	695077144	495	0	0
CheckAccumTrig1_A	695077144	18	0	0
CheckClr_A	695077144	217	0	0
CheckEn_A	694735639	303355430	0	0
CheckPhase0_A	695077144	570	0	0
CheckPhase1_A	695077144	557	0	0
CheckPhase2_A	695077144	538	0	0
CheckPhase3_A	695077144	532	0	0
CheckTimeout0_A	695077144	1376	0	0
CheckTimeoutSt1_A	695077144	123926	0	0
CheckTimeoutSt2_A	695077144	1292	0	0
CheckTimeoutStTrig_A	695077144	63	0	0
ErrorStAllEscAsserted_A	695077144	1520	0	0
ErrorStIsTerminal_A	695077144	1280	0	0
EscStateOut_A	694733303	694661181	0	0
u_state_regs_A	695077144	694903083	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	249	0	0
T4	53738	43	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	57	0	0
T12	0	67	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	27	0	0
T35	0	55	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	495	0	0
T5	521320	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	3	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T24	68805	7	0	0
T25	4481	0	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	18	0	0
T10	761767	0	0	0
T17	396861	1	0	0
T21	103078	0	0	0
T23	0	1	0	0
T26	852176	0	0	0
T28	380228	0	0	0
T31	0	2	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T39	233578	0	0	0
T72	46299	0	0	0
T73	48807	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	217	0	0
T15	560179	1	0	0
T16	579319	0	0	0
T17	396861	2	0	0
T20	29229	1	0	0
T24	68805	6	0	0
T28	0	6	0	0
T31	0	2	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T70	0	1	0	0
T71	4003	0	0	0
T72	46299	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694735639	303355430	0	0
T1	26546	3243	0	0
T2	14586	9816	0	0
T3	3351	2713	0	0
T4	866	768	0	0
T5	521320	3004	0	0
T6	4765	2139	0	0
T7	775020	774948	0	0
T8	218242	218232	0	0
T18	57951	49057	0	0
T19	36205	17524	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	570	0	0
T5	521320	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T24	68805	7	0	0
T25	4481	0	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	557	0	0
T5	521320	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T24	68805	7	0	0
T25	4481	0	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	538	0	0
T5	521320	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T24	68805	7	0	0
T25	4481	0	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	532	0	0
T5	521320	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	2	0	0
T24	68805	5	0	0
T25	4481	0	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1376	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T17	0	2	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T23	0	1	0	0
T25	4481	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0
T66	0	3	0	0
T73	0	3	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	123926	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	111	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T17	0	128	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T27	0	446	0	0
T28	0	123	0	0
T44	0	60	0	0
T63	0	919	0	0
T66	0	397	0	0
T73	0	518	0	0
T76	0	193	0	0
T77	0	157	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1292	0	0
T4	53738	0	0	0
T5	521320	0	0	0
T6	4765	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T31	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0
T66	0	3	0	0
T73	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	63	0	0
T10	761767	0	0	0
T17	396861	1	0	0
T21	103078	0	0	0
T26	852176	0	0	0
T28	380228	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T39	233578	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T72	46299	0	0	0
T73	48807	0	0	0
T79	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1520	0	0
T4	53738	199	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	405	0	0
T12	0	357	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	176	0	0
T35	0	383	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1280	0	0
T4	53738	169	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	345	0	0
T12	0	297	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	146	0	0
T35	0	323	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694733303	694661181	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	387	290	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	694903083	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	53738	40911	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T5,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T19,T20,T15
1	0	1	Covered	T2,T36,T37
1	1	0	Covered	T6,T15,T17
1	1	1	Covered	T19,T20,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T15
0	1	Covered	T19,T20,T17
1	0	Covered	T20,T15,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T20,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T15,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T15
1	0	Not Covered
1	1	Covered	T19,T20,T17

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T20,T61,T69

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T19,T20
1	Covered	T2,T17,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T20
1	Covered	T19,T15,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T20
1	Covered	T5,T15,T39

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T19,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T15,T37

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T19,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T19,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T5,T19
Phase1St	198	Covered	T2,T5,T19
Phase2St	215	Covered	T2,T5,T19
Phase3St	233	Covered	T2,T5,T19
TerminalSt	249	Covered	T2,T5,T19
TimeoutSt	159	Covered	T19,T20,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T5,T15
IdleSt->TimeoutSt	159	Covered	T19,T20,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T33,T78
Phase0St->Phase1St	198	Covered	T2,T5,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T29,T111
Phase1St->Phase2St	215	Covered	T2,T5,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T33,T29
Phase2St->Phase3St	233	Covered	T2,T5,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T112,T51,T113
Phase3St->TerminalSt	249	Covered	T2,T5,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T20,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T20,T15,T73
TimeoutSt->Phase0St	172	Covered	T19,T20,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T15,T73
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T33,T78
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T5,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T5,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T29,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T5,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T5,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T33,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T5,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T19,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T112,T51,T113
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T5,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T5,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695077144	261	0	0
CheckAccumTrig0_A	695077144	527	0	0
CheckAccumTrig1_A	695077144	24	0	0
CheckClr_A	695077144	273	0	0
CheckEn_A	694735639	305585916	0	0
CheckPhase0_A	695077144	609	0	0
CheckPhase1_A	695077144	601	0	0
CheckPhase2_A	695077144	580	0	0
CheckPhase3_A	695077144	568	0	0
CheckTimeout0_A	695077144	1728	0	0
CheckTimeoutSt1_A	695077144	184415	0	0
CheckTimeoutSt2_A	695077144	1631	0	0
CheckTimeoutStTrig_A	695077144	72	0	0
ErrorStAllEscAsserted_A	695077144	1392	0	0
ErrorStIsTerminal_A	695077144	1152	0	0
EscStateOut_A	694733303	694661181	0	0
u_state_regs_A	695077144	694903083	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	261	0	0
T4	53738	36	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	56	0	0
T12	0	66	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	35	0	0
T35	0	68	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	527	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	2	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T15	0	7	0	0
T17	0	2	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T22	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	24	0	0
T15	560179	1	0	0
T16	579319	0	0	0
T17	396861	0	0	0
T20	29229	1	0	0
T26	852176	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T71	4003	0	0	0
T72	46299	0	0	0
T76	0	1	0	0
T105	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	273	0	0
T5	521320	1	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	0	5	0	0
T17	0	1	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T20	0	2	0	0
T24	68805	0	0	0
T25	4481	0	0	0
T33	0	8	0	0
T38	0	1	0	0
T40	0	1	0	0
T58	0	1	0	0
T69	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694735639	305585916	0	0
T1	26546	3252	0	0
T2	14586	2141	0	0
T3	3351	2724	0	0
T4	866	768	0	0
T5	521320	14599	0	0
T6	4765	4712	0	0
T7	775020	724157	0	0
T8	218242	217728	0	0
T18	57951	48928	0	0
T19	36205	2602	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	609	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	2	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T15	0	7	0	0
T17	0	4	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	601	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	2	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T15	0	7	0	0
T17	0	4	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	580	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	2	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T15	0	7	0	0
T17	0	3	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	568	0	0
T2	14586	1	0	0
T3	3351	0	0	0
T4	53738	0	0	0
T5	521320	2	0	0
T6	4765	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T15	0	7	0	0
T17	0	3	0	0
T18	57951	0	0	0
T19	36205	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1728	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	560179	2	0	0
T16	579319	0	0	0
T17	0	2	0	0
T19	36205	1	0	0
T20	29229	5	0	0
T21	0	1	0	0
T24	68805	0	0	0
T25	4481	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T36	39806	0	0	0
T63	0	1	0	0
T66	0	3	0	0
T73	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	184415	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	560179	292	0	0
T16	579319	0	0	0
T17	0	134	0	0
T19	36205	680	0	0
T20	29229	498	0	0
T21	0	755	0	0
T24	68805	0	0	0
T25	4481	0	0	0
T27	0	19	0	0
T29	0	66	0	0
T36	39806	0	0	0
T63	0	283	0	0
T66	0	518	0	0
T73	0	630	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1631	0	0
T15	560179	1	0	0
T16	579319	0	0	0
T17	396861	0	0	0
T20	29229	2	0	0
T26	852176	0	0	0
T36	39806	0	0	0
T37	242577	0	0	0
T38	478584	0	0	0
T45	0	1	0	0
T66	0	3	0	0
T71	4003	0	0	0
T72	46299	0	0	0
T73	0	3	0	0
T78	0	3	0	0
T79	0	2	0	0
T80	0	2	0	0
T82	0	1	0	0
T83	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	72	0	0
T9	183368	0	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T15	560179	0	0	0
T16	579319	0	0	0
T17	0	2	0	0
T19	36205	1	0	0
T20	29229	2	0	0
T21	0	1	0	0
T24	68805	0	0	0
T25	4481	0	0	0
T29	0	1	0	0
T36	39806	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T63	0	1	0	0
T73	0	1	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1392	0	0
T4	53738	171	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	345	0	0
T12	0	357	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	192	0	0
T35	0	327	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	1152	0	0
T4	53738	141	0	0
T5	521320	0	0	0
T7	775020	0	0	0
T8	218242	0	0	0
T9	183368	0	0	0
T11	0	285	0	0
T12	0	297	0	0
T13	159784	0	0	0
T14	44260	0	0	0
T18	57951	0	0	0
T19	36205	0	0	0
T25	4481	0	0	0
T34	0	162	0	0
T35	0	267	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694733303	694661181	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	387	290	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695077144	694903083	0	0
T1	26546	26400	0	0
T2	14586	14526	0	0
T3	3351	3290	0	0
T4	53738	40911	0	0
T5	521320	521315	0	0
T6	4765	4713	0	0
T7	775020	774949	0	0
T8	218242	218232	0	0
T18	57951	57855	0	0
T19	36205	36153	0	0