Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	72191	1			T3	9		T19	3220		T15	9
class_i[0x1]	52045	1			T15	5043		T9	17		T16	1366
class_i[0x2]	54661	1			T3	23		T7	2405		T9	1
class_i[0x3]	85260	1			T9	6		T16	1		T20	40

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	66929	1			T3	10		T7	669		T19	826
alert[0x1]	66671	1			T3	4		T7	608		T19	833
alert[0x2]	65669	1			T3	12		T7	552		T19	817
alert[0x3]	64888	1			T3	6		T7	576		T19	744

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

263901

1

T3

23

T7

2405

T19

3220

esc_ping_fail

256

1

T3

9

T9

7

T10

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	66858	1			T3	7		T7	669		T19	826
esc_integrity_fail	alert[0x1]	66603	1			T3	3		T7	608		T19	833
esc_integrity_fail	alert[0x2]	65610	1			T3	9		T7	552		T19	817
esc_integrity_fail	alert[0x3]	64830	1			T3	4		T7	576		T19	744
esc_ping_fail	alert[0x0]	71	1			T3	3		T9	2		T10	1
esc_ping_fail	alert[0x1]	68	1			T3	1		T9	2		T10	1
esc_ping_fail	alert[0x2]	59	1			T3	3		T9	3		T10	2
esc_ping_fail	alert[0x3]	58	1			T3	2		T188	2		T289	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	72112	1			T19	3220		T15	9		T16	715
esc_integrity_fail	class_i[0x1]	51994	1			T15	5043		T9	17		T16	1366
esc_integrity_fail	class_i[0x2]	54580	1			T3	23		T7	2405		T16	3
esc_integrity_fail	class_i[0x3]	85215	1			T16	1		T20	40		T54	3
esc_ping_fail	class_i[0x0]	79	1			T3	9		T188	9		T286	5
esc_ping_fail	class_i[0x1]	51	1			T10	4		T289	5		T295	2
esc_ping_fail	class_i[0x2]	81	1			T9	1		T188	2		T286	1
esc_ping_fail	class_i[0x3]	45	1			T9	6		T296	1		T219	3